/* ---------------------------------------------------------------------------- | |
* ATMEL Microcontroller Software Support | |
* ---------------------------------------------------------------------------- | |
* Copyright (c) 2009, Atmel Corporation | |
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* All rights reserved. | |
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* modification, are permitted provided that the following conditions are met: | |
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* this list of conditions and the disclaimer below. | |
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*/ | |
/* | |
Title: Memories implementation | |
*/ | |
//------------------------------------------------------------------------------ | |
// Headers | |
//------------------------------------------------------------------------------ | |
#include <board.h> | |
//------------------------------------------------------------------------------ | |
// Exported functions | |
//------------------------------------------------------------------------------ | |
//------------------------------------------------------------------------------ | |
/// Dummy function to initialize and configure the SDRAM | |
//------------------------------------------------------------------------------ | |
void BOARD_ConfigureSdram(unsigned char busWidth) | |
{ | |
} | |
//------------------------------------------------------------------------------ | |
/// Configures the EBI for NandFlash access. Pins must be configured after or | |
/// before calling this function. | |
//------------------------------------------------------------------------------ | |
void BOARD_ConfigureNandFlash(unsigned char busWidth) | |
{ | |
AT91PS_HSMC4 pHSMC4 = AT91C_BASE_HSMC4; | |
AT91PS_HSMC4_CS pSMC = AT91C_BASE_HSMC4_CS1; | |
// Open EBI clock | |
AT91C_BASE_PMC->PMC_PCER = (1<< AT91C_ID_HSMC4); | |
#ifdef CHIP_NAND_CTRL | |
// Enable the Nand Flash Controller | |
pHSMC4 ->HSMC4_CTRL = AT91C_HSMC4_NFCEN; | |
#endif | |
pSMC->HSMC4_SETUP = 0 | |
| ((0 << 0) & AT91C_HSMC4_NWE_SETUP) | |
| ((1 << 8) & AT91C_HSMC4_NCS_WR_SETUP) | |
| ((0 << 16) & AT91C_HSMC4_NRD_SETUP) | |
| ((1 << 24) & AT91C_HSMC4_NCS_RD_SETUP); | |
pSMC->HSMC4_PULSE = 0 | |
| ((2 << 0) & AT91C_HSMC4_NWE_PULSE) | |
| ((3 << 8) & AT91C_HSMC4_NCS_WR_PULSE) | |
| ((3 << 16) & AT91C_HSMC4_NRD_PULSE) | |
| ((4 << 24) & AT91C_HSMC4_NCS_RD_PULSE); | |
pSMC->HSMC4_CYCLE = 0 | |
| ((4 << 0) & AT91C_HSMC4_NWE_CYCLE) | |
| ((7 << 16) & AT91C_HSMC4_NRD_CYCLE); | |
pSMC->HSMC4_TIMINGS = 0 | |
| ((1 << 0) & AT91C_HSMC4_TCLR) // CLE to REN | |
| ((2 << 4) & AT91C_HSMC4_TADL) // ALE to Data | |
| ((1 << 8) & AT91C_HSMC4_TAR) // ALE to REN | |
| ((1 << 16) & AT91C_HSMC4_TRR) // Ready to REN | |
| ((2 << 24) & AT91C_HSMC4_TWB) // WEN to REN | |
| (7<<28) | |
|(AT91C_HSMC4_NFSEL) // Nand Flash Timing | |
; | |
if (busWidth == 8) { | |
pSMC->HSMC4_MODE = AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS | AT91C_HSMC4_READ_MODE | AT91C_HSMC4_WRITE_MODE; | |
} | |
else if (busWidth == 16) { | |
pSMC->HSMC4_MODE = AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS | AT91C_HSMC4_READ_MODE | AT91C_HSMC4_WRITE_MODE; | |
} | |
} | |