# ############################################################################## | |
# Created by Base System Builder Wizard for Xilinx EDK 10.1.01 Build EDK_K_SP1.3 | |
# Fri May 09 11:01:33 2008 | |
# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1 | |
# Family: virtex4 | |
# Device: xc4vfx12 | |
# Package: ff668 | |
# Speed Grade: -10 | |
# Processor: ppc405_0 | |
# Processor clock frequency: 200.00 MHz | |
# Bus clock frequency: 100.00 MHz | |
# Total Off Chip Memory : 1 MB | |
# - SRAM = 1 MB | |
# ############################################################################## | |
PARAMETER VERSION = 2.1.0 | |
PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I | |
PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O | |
PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3] | |
PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4] | |
PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I | |
PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1] | |
PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0] | |
PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O | |
PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O | |
PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O | |
PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I | |
PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [9:29] | |
PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3] | |
PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O | |
PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31] | |
PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0] | |
PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0] | |
PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O | |
PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O | |
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 | |
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST | |
BEGIN ppc405_virtex4 | |
PARAMETER INSTANCE = ppc405_0 | |
PARAMETER HW_VER = 2.01.a | |
PARAMETER C_FASTEST_PLB_CLOCK = DPLB0 | |
PARAMETER C_APU_CONTROL = 0b0000000000000001 | |
PARAMETER C_IDCR_BASEADDR = 0b0100000000 | |
PARAMETER C_IDCR_HIGHADDR = 0b0111111111 | |
BUS_INTERFACE JTAGPPC = jtagppc_0_0 | |
BUS_INTERFACE IPLB0 = plb | |
BUS_INTERFACE DPLB0 = plb | |
BUS_INTERFACE RESETPPC = ppc_reset_bus | |
PORT CPMC405CLOCK = proc_clk_s | |
PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ | |
END | |
BEGIN jtagppc_cntlr | |
PARAMETER INSTANCE = jtagppc_0 | |
PARAMETER HW_VER = 2.01.a | |
BUS_INTERFACE JTAGPPC0 = jtagppc_0_0 | |
END | |
BEGIN plb_v46 | |
PARAMETER INSTANCE = plb | |
PARAMETER C_DCR_INTFCE = 0 | |
PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100 | |
PARAMETER HW_VER = 1.02.a | |
PORT PLB_Clk = sys_clk_s | |
PORT SYS_Rst = sys_bus_reset | |
END | |
BEGIN xps_uartlite | |
PARAMETER INSTANCE = RS232_Uart | |
PARAMETER HW_VER = 1.00.a | |
PARAMETER C_BAUDRATE = 9600 | |
PARAMETER C_DATA_BITS = 8 | |
PARAMETER C_ODD_PARITY = 0 | |
PARAMETER C_USE_PARITY = 0 | |
PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000 | |
PARAMETER C_BASEADDR = 0x84000000 | |
PARAMETER C_HIGHADDR = 0x8400ffff | |
BUS_INTERFACE SPLB = plb | |
PORT RX = fpga_0_RS232_Uart_RX | |
PORT TX = fpga_0_RS232_Uart_TX | |
PORT Interrupt = RS232_Uart_Interrupt | |
END | |
BEGIN xps_gpio | |
PARAMETER INSTANCE = LEDs_4Bit | |
PARAMETER HW_VER = 1.00.a | |
PARAMETER C_GPIO_WIDTH = 4 | |
PARAMETER C_IS_DUAL = 0 | |
PARAMETER C_IS_BIDIR = 1 | |
PARAMETER C_ALL_INPUTS = 0 | |
PARAMETER C_BASEADDR = 0x81400000 | |
PARAMETER C_HIGHADDR = 0x8140ffff | |
BUS_INTERFACE SPLB = plb | |
PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO | |
END | |
BEGIN xps_gpio | |
PARAMETER INSTANCE = LEDs_Positions | |
PARAMETER HW_VER = 1.00.a | |
PARAMETER C_GPIO_WIDTH = 5 | |
PARAMETER C_IS_DUAL = 0 | |
PARAMETER C_IS_BIDIR = 1 | |
PARAMETER C_ALL_INPUTS = 0 | |
PARAMETER C_BASEADDR = 0x81420000 | |
PARAMETER C_HIGHADDR = 0x8142ffff | |
BUS_INTERFACE SPLB = plb | |
PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO | |
END | |
BEGIN xps_sysace | |
PARAMETER INSTANCE = SysACE_CompactFlash | |
PARAMETER HW_VER = 1.00.a | |
PARAMETER C_MEM_WIDTH = 16 | |
PARAMETER C_BASEADDR = 0x83600000 | |
PARAMETER C_HIGHADDR = 0x8360ffff | |
BUS_INTERFACE SPLB = plb | |
PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK | |
PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA & SysACE_CompactFlash_SysACE_MPA | |
PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD | |
PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN | |
PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN | |
PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN | |
PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ | |
END | |
BEGIN xps_mch_emc | |
PARAMETER INSTANCE = SRAM | |
PARAMETER HW_VER = 1.01.a | |
PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000 | |
PARAMETER C_NUM_BANKS_MEM = 1 | |
PARAMETER C_MAX_MEM_WIDTH = 32 | |
PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1 | |
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 | |
PARAMETER C_MEM0_WIDTH = 32 | |
PARAMETER C_SYNCH_MEM_0 = 1 | |
PARAMETER C_TCEDV_PS_MEM_0 = 0 | |
PARAMETER C_TWC_PS_MEM_0 = 0 | |
PARAMETER C_TAVDV_PS_MEM_0 = 0 | |
PARAMETER C_TWP_PS_MEM_0 = 0 | |
PARAMETER C_THZCE_PS_MEM_0 = 0 | |
PARAMETER C_TLZWE_PS_MEM_0 = 0 | |
PARAMETER C_MEM0_BASEADDR = 0xfff00000 | |
PARAMETER C_MEM0_HIGHADDR = 0xffffffff | |
BUS_INTERFACE SPLB = plb | |
PORT Mem_A = fpga_0_SRAM_Mem_A_split | |
PORT Mem_BEN = fpga_0_SRAM_Mem_BEN | |
PORT Mem_WEN = fpga_0_SRAM_Mem_WEN | |
PORT Mem_DQ = fpga_0_SRAM_Mem_DQ | |
PORT Mem_OEN = fpga_0_SRAM_Mem_OEN | |
PORT Mem_CEN = fpga_0_SRAM_Mem_CEN | |
PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN | |
PORT RdClk = sys_clk_s | |
END | |
BEGIN util_bus_split | |
PARAMETER INSTANCE = SRAM_util_bus_split_0 | |
PARAMETER HW_VER = 1.00.a | |
PARAMETER C_SIZE_IN = 32 | |
PARAMETER C_LEFT_POS = 9 | |
PARAMETER C_SPLIT = 30 | |
PORT Sig = fpga_0_SRAM_Mem_A_split | |
PORT Out1 = fpga_0_SRAM_Mem_A | |
END | |
BEGIN clock_generator | |
PARAMETER INSTANCE = clock_generator_0 | |
PARAMETER HW_VER = 2.01.a | |
PARAMETER C_EXT_RESET_HIGH = 1 | |
PARAMETER C_CLKIN_FREQ = 100000000 | |
PARAMETER C_CLKOUT0_FREQ = 200000000 | |
PARAMETER C_CLKOUT0_BUF = TRUE | |
PARAMETER C_CLKOUT0_PHASE = 0 | |
PARAMETER C_CLKOUT0_GROUP = NONE | |
PARAMETER C_CLKOUT1_FREQ = 100000000 | |
PARAMETER C_CLKOUT1_BUF = TRUE | |
PARAMETER C_CLKOUT1_PHASE = 0 | |
PARAMETER C_CLKOUT1_GROUP = NONE | |
PORT CLKOUT0 = proc_clk_s | |
PORT CLKOUT1 = sys_clk_s | |
PORT CLKIN = dcm_clk_s | |
PORT LOCKED = Dcm_all_locked | |
PORT RST = net_gnd | |
END | |
BEGIN proc_sys_reset | |
PARAMETER INSTANCE = proc_sys_reset_0 | |
PARAMETER HW_VER = 2.00.a | |
PARAMETER C_EXT_RESET_HIGH = 0 | |
BUS_INTERFACE RESETPPC0 = ppc_reset_bus | |
PORT Slowest_sync_clk = sys_clk_s | |
PORT Dcm_locked = Dcm_all_locked | |
PORT Ext_Reset_In = sys_rst_s | |
PORT Bus_Struct_Reset = sys_bus_reset | |
PORT Peripheral_Reset = sys_periph_reset | |
END | |
BEGIN xps_intc | |
PARAMETER INSTANCE = xps_intc_0 | |
PARAMETER HW_VER = 1.00.a | |
PARAMETER C_BASEADDR = 0x81800000 | |
PARAMETER C_HIGHADDR = 0x8180ffff | |
BUS_INTERFACE SPLB = plb | |
PORT Irq = EICC405EXTINPUTIRQ | |
PORT Intr = RS232_Uart_Interrupt | |
END | |