| /** | |
| * \file | |
| * | |
| * \brief SAM3S clock configuration. | |
| * | |
| * Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved. | |
| * | |
| * \asf_license_start | |
| * | |
| * \page License | |
| * | |
| * Redistribution and use in source and binary forms, with or without | |
| * modification, are permitted provided that the following conditions are met: | |
| * | |
| * 1. Redistributions of source code must retain the above copyright notice, | |
| * this list of conditions and the following disclaimer. | |
| * | |
| * 2. Redistributions in binary form must reproduce the above copyright notice, | |
| * this list of conditions and the following disclaimer in the documentation | |
| * and/or other materials provided with the distribution. | |
| * | |
| * 3. The name of Atmel may not be used to endorse or promote products derived | |
| * from this software without specific prior written permission. | |
| * | |
| * 4. This software may only be redistributed and used in connection with an | |
| * Atmel microcontroller product. | |
| * | |
| * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED | |
| * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
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| * \asf_license_stop | |
| * | |
| */ | |
| #ifndef CONF_CLOCK_H_INCLUDED | |
| #define CONF_CLOCK_H_INCLUDED | |
| // ===== System Clock (MCK) Source Options | |
| //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC | |
| //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL | |
| //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS | |
| //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC | |
| //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC | |
| //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC | |
| //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL | |
| //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS | |
| #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK | |
| //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLBCK | |
| // ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES)) | |
| //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 | |
| #define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 | |
| //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 | |
| //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 | |
| //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 | |
| //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 | |
| //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 | |
| //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 | |
| // ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) | |
| // Use mul and div effective values here. | |
| #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL | |
| #define CONFIG_PLL0_MUL 32 | |
| #define CONFIG_PLL0_DIV 3 | |
| // ===== PLL1 (B) Options (Fpll = (Fclk * PLL_mul) / PLL_div) | |
| // Use mul and div effective values here. | |
| #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL | |
| #define CONFIG_PLL1_MUL 16 | |
| #define CONFIG_PLL1_DIV 2 | |
| // ===== USB Clock Source Options (Fusb = FpllX / USB_div) | |
| // Use div effective value here. | |
| //#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 | |
| //#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 | |
| //#define CONFIG_USBCLK_DIV 2 | |
| // ===== Target frequency (System clock) | |
| // - XTAL frequency: 12MHz | |
| // - System clock source: PLLA | |
| // - System clock prescaler: 2 (divided by 2) | |
| // - PLLA source: XTAL | |
| // - PLLA output: XTAL * 32 / 3 | |
| // - System clock is: 12 * 32 / 3 / 2 = 64MHz | |
| // ===== Target frequency (USB Clock) | |
| // - USB clock source: PLLB | |
| // - USB clock divider: 2 (divided by 2) | |
| // - PLLB output: XTAL * 16 / 2 | |
| // - USB clock: 12 * 16 / 2 / 2 = 48MHz | |
| #endif /* CONF_CLOCK_H_INCLUDED */ |