/** | |
* \file | |
* | |
* \brief SAM3X clock configuration. | |
* | |
* Copyright (c) 2011 - 2012 Atmel Corporation. All rights reserved. | |
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*/ | |
#ifndef CONF_CLOCK_H_INCLUDED | |
#define CONF_CLOCK_H_INCLUDED | |
// ===== System Clock (MCK) Source Options | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS | |
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK | |
//#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK | |
// ===== System Clock (MCK) Prescaler Options (Fmck = Fsys / (SYSCLK_PRES)) | |
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_1 | |
#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2 | |
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4 | |
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8 | |
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16 | |
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32 | |
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64 | |
//#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3 | |
// ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div) | |
// Use mul and div effective values here. | |
#define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL | |
#define CONFIG_PLL0_MUL 14 | |
#define CONFIG_PLL0_DIV 1 | |
// ===== UPLL (UTMI) Hardware fixed at 480 MHz. | |
// ===== USB Clock Source Options (Fusb = FpllX / USB_div) | |
// Use div effective value here. | |
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0 | |
//#define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL | |
//#define CONFIG_USBCLK_DIV 1 | |
// ===== Target frequency (System clock) | |
// - XTAL frequency: 12MHz | |
// - System clock source: PLLA | |
// - System clock prescaler: 2 (divided by 2) | |
// - PLLA source: XTAL | |
// - PLLA output: XTAL * 14 / 1 | |
// - System clock is: 12 * 14 / 1 /2 = 84MHz | |
// ===== Target frequency (USB Clock) | |
// - USB clock source: UPLL | |
// - USB clock divider: 1 (not divided) | |
// - UPLL frequency: 480MHz | |
// - USB clock: 480 / 1 = 480MHz | |
#endif /* CONF_CLOCK_H_INCLUDED */ |