/*******************************************************************************
*                                                                              *
* Copyright 2013 Altera Corporation. All Rights Reserved.                      *
*                                                                              *
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/* Altera - ALT_EMAC */

#ifndef __ALTERA_ALT_EMAC_H__
#define __ALTERA_ALT_EMAC_H__

#ifdef __cplusplus
extern "C"
{
#endif  /* __cplusplus */

/*
 * Component : EMAC Module - ALT_EMAC
 * EMAC Module
 * 
 * Registers in the EMAC module.
 * 
 */
/*
 * Register Group : GMAC Register Group - ALT_EMAC_GMAC
 * GMAC Register Group
 * 
 * GMAC Register Group
 * 
 */
/*
 * Register : Register 0 (MAC Configuration Register) - MAC_Configuration
 * 
 * The MAC Configuration register establishes receive and transmit operating modes.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                    
 * :--------|:-------|:------|:------------------------------------------------
 *  [1:0]   | RW     | 0x0   | Preamble Length for Transmit Frames            
 *  [2]     | RW     | 0x0   | Receiver Enable                                
 *  [3]     | RW     | 0x0   | Transmitter Enable                             
 *  [4]     | RW     | 0x0   | Deferral Check                                 
 *  [6:5]   | RW     | 0x0   | Back-Off Limit                                 
 *  [7]     | RW     | 0x0   | Automatic Pad or CRC Stripping                 
 *  [8]     | RW     | 0x0   | Link Up or Down                                
 *  [9]     | RW     | 0x0   | Disable Retry                                  
 *  [10]    | RW     | 0x0   | Checksum Offload                               
 *  [11]    | RW     | 0x0   | Duplex Mode                                    
 *  [12]    | RW     | 0x0   | Loopback Mode                                  
 *  [13]    | RW     | 0x0   | Disable Receive Own                            
 *  [14]    | RW     | 0x0   | Speed                                          
 *  [15]    | RW     | 0x0   | Port Select                                    
 *  [16]    | RW     | 0x0   | Disable Carrier Sense During Transmission      
 *  [19:17] | RW     | 0x0   | Inter-Frame Gap                                
 *  [20]    | RW     | 0x0   | Jumbo Frame Enable                             
 *  [21]    | RW     | 0x0   | Frame Burst Enable                             
 *  [22]    | RW     | 0x0   | Jabber Disable                                 
 *  [23]    | RW     | 0x0   | Watchdog Disable                               
 *  [24]    | RW     | 0x0   | Transmit Configuration in RGMII, SGMII, or SMII
 *  [25]    | RW     | 0x0   | CRC Stripping of Type Frames                   
 *  [26]    | ???    | 0x0   | *UNDEFINED*                                    
 *  [27]    | RW     | 0x0   | IEEE 802.3as support for 2K packets Enable     
 *  [31:28] | ???    | 0x0   | *UNDEFINED*                                    
 * 
 */
/*
 * Field : Preamble Length for Transmit Frames - prelen
 * 
 * These bits control the number of preamble bytes that are added to the beginning
 * of every Transmit frame. The preamble reduction occurs only when the MAC is
 * operating
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description     
 * :-------------------------------------------|:------|:-----------------
 *  ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES | 0x0   | Preamble 7 Bytes
 *  ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES | 0x1   | Preamble 5 Bytes
 *  ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES | 0x2   | Preamble 3 Bytes
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN
 * 
 * Preamble 7 Bytes
 */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN
 * 
 * Preamble 5 Bytes
 */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES  0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN
 * 
 * Preamble 3 Bytes
 */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES  0x2

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET_MSK    0x00000003
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_CLR_MSK    0xfffffffc
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field. */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_PRELEN field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_GET(value) (((value) & 0x00000003) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET(value) (((value) << 0) & 0x00000003)

/*
 * Field : Receiver Enable - re
 * 
 * When this bit is set, the receiver state machine of the MAC is enabled for
 * receiving frames from the GMII or MII. When this bit is reset, the MAC receive
 * state machine is disabled after the completion of the reception of the current
 * frame, and does not receive any further frames from the GMII or MII.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                       
 * :--------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD | 0x0   | MAC receive state machine disabled
 *  ALT_EMAC_GMAC_MAC_CFG_RE_E_END  | 0x1   | MAC receive state machine enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE
 * 
 * MAC receive state machine disabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE
 * 
 * MAC receive state machine enabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_RE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_RE_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_RE_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_RE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_RE register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_RE_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_RE register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_RE_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_RE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_RE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_RE field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_RE_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_RE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_RE_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Transmitter Enable - te
 * 
 * When this bit is set, the transmit state machine of the MAC is enabled for
 * transmission on the GMII or MII. When this bit is reset, the MAC transmit state
 * machine is disabled after the completion of the transmission of the current
 * frame, and does not transmit any further frames.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                        
 * :--------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD | 0x0   | MAC transmit state machine disabled
 *  ALT_EMAC_GMAC_MAC_CFG_TE_E_END  | 0x1   | MAC transmit state machine disabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE
 * 
 * MAC transmit state machine disabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE
 * 
 * MAC transmit state machine disabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_TE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TE_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TE_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TE register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_TE_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TE register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_TE_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_TE field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_TE_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_TE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_TE_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Deferral Check - dc
 * 
 * When this bit is set, the deferral check function is enabled in the MAC. The MAC
 * issues a Frame Abort status, along with the excessive deferral error bit set in
 * the transmit frame status, when the transmit state machine is deferred for more
 * than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for
 * 1000 Mbps operation, or if the Jumbo frame mode is enabled in the 10 or 100 Mbps
 * mode, the threshold for deferral is 155,680 bits times. Deferral begins when the
 * transmitter is ready to transmit, but is prevented because of an active carrier
 * sense signal (CRS) on GMII or MII. Defer time is not cumulative. When the
 * transmitter defers for 10,000 bit times, it transmits, collides, backs off, and
 * then defers again after completion of back-off. The deferral timer resets to 0
 * and restarts.
 * 
 * When this bit is reset, the deferral check function is disabled and the MAC
 * defers until the CRS signal goes inactive. This bit is applicable only in the
 * half-duplex mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description            
 * :--------------------------------|:------|:------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_DC_E_END  | 0x1   | Deferral Check Enabled 
 *  ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD | 0x0   | Deferral Check Disabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC
 * 
 * Deferral Check Enabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_DC_E_END  0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC
 * 
 * Deferral Check Disabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD 0x0

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DC_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DC_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DC_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DC register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_DC_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DC register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_DC_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DC_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_DC field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_DC_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_DC register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_DC_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Back-Off Limit - bl
 * 
 * The Back-Off limit determines the random integer number (r) of slot time delays
 * (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the
 * MAC waits before rescheduling a transmission attempt during retries after a
 * collision. This bit is applicable only in the half-duplex mode.
 * 
 * * 00: k = min (n, 10)
 * 
 * * 01: k = min (n, 8)
 * 
 * * 10: k = min (n, 4)
 * 
 * * 11: k = min (n, 1)
 * 
 * where <i> n </i>= retransmission attempt. The random integer <i> r </i> takes
 * the value in the
 * 
 * range 0 <= r < kth power of 2
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description    
 * :---------------------------------------|:------|:----------------
 *  ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10 | 0x0   | k = min (n, 10)
 *  ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8 | 0x1   | k = min (n, 8) 
 *  ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4 | 0x2   | k = min (n, 4) 
 *  ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1 | 0x3   | k = min (n, 1) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
 * 
 * k = min (n, 10)
 */
#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
 * 
 * k = min (n, 8)
 */
#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8  0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
 * 
 * k = min (n, 4)
 */
#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4  0x2
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL
 * 
 * k = min (n, 1)
 */
#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1  0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
#define ALT_EMAC_GMAC_MAC_CFG_BL_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
#define ALT_EMAC_GMAC_MAC_CFG_BL_MSB        6
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
#define ALT_EMAC_GMAC_MAC_CFG_BL_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BL register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_BL_SET_MSK    0x00000060
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BL register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_BL_CLR_MSK    0xffffff9f
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_BL register field. */
#define ALT_EMAC_GMAC_MAC_CFG_BL_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_BL field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_BL_GET(value) (((value) & 0x00000060) >> 5)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_BL register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_BL_SET(value) (((value) << 5) & 0x00000060)

/*
 * Field : Automatic Pad or CRC Stripping - acs
 * 
 * When this bit is set, the MAC strips the Pad or FCS field on the incoming frames
 * only if the value of the length field is less than 1,536 bytes. All received
 * frames with length field greater than or equal to 1,536 bytes are passed to the
 * application without stripping the Pad or FCS field.
 * 
 * When this bit is reset, the MAC passes all incoming frames, without modifying
 * them, to the Host.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                        
 * :---------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD | 0x0   | Disable Automatic Pad CRC Stripping
 *  ALT_EMAC_GMAC_MAC_CFG_ACS_E_END  | 0x1   | Enable Automatic Pad CRC Stripping 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS
 * 
 * Disable Automatic Pad CRC Stripping
 */
#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS
 * 
 * Enable Automatic Pad CRC Stripping
 */
#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_ACS_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_ACS_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_ACS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_ACS register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_ACS register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_ACS_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_ACS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_ACS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_ACS field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_ACS_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_ACS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Link Up or Down - lud
 * 
 * This bit indicates whether the link is up or down during the transmission of
 * configuration in the RGMII, SGMII, or SMII interface
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description
 * :---------------------------------|:------|:------------
 *  ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD | 0x0   | Link Down  
 *  ALT_EMAC_GMAC_MAC_CFG_LUD_E_END  | 0x1   | Link Up    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD
 * 
 * Link Down
 */
#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD
 * 
 * Link Up
 */
#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_LUD_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_LUD_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_LUD_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LUD register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LUD register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_LUD_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_LUD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_LUD_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_LUD field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_LUD_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_LUD register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Disable Retry - dr
 * 
 * When this bit is set, the MAC attempts only one transmission. When a collision
 * occurs on the GMII or MII interface, the MAC ignores the current frame
 * transmission and reports a Frame Abort with excessive collision error in the
 * transmit frame status.
 * 
 * When this bit is reset, the MAC attempts retries based on the settings of the BL
 * field (Bits [6:5]). This bit is applicable only in the half-duplex mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                      
 * :--------------------------------|:------|:----------------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD | 0x1   | MAC attempts one transmission    
 *  ALT_EMAC_GMAC_MAC_CFG_DR_E_END  | 0x0   | MAC attempts retries per bl Field
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR
 * 
 * MAC attempts one transmission
 */
#define ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD 0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR
 * 
 * MAC attempts retries per bl Field
 */
#define ALT_EMAC_GMAC_MAC_CFG_DR_E_END  0x0

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DR_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DR_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DR register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_DR_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DR register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_DR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DR register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DR_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_DR field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_DR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_DR register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_DR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Checksum Offload - ipc
 * 
 * When this bit is set, the MAC calculates the 16-bit ones complement of the ones
 * complement sum of all received Ethernet frame payloads. It also checks whether
 * the IPv4 Header checksum (assumed to be bytes 2526 or 2930 (VLAN-tagged) of the
 * received Ethernet frame) is correct for the received frame and gives the status
 * in the receive status word. The MAC also appends the 16-bit checksum calculated
 * for the IP header datagram payload (bytes after the IPv4 header) and appends it
 * to the Ethernet frame transferred to the application (when Type 2 COE is
 * deselected).
 * 
 * When this bit is reset, this function is disabled.
 * 
 * When Type 2 COE is selected, this bit, when set, enables the IPv4 header
 * checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking.
 * When this bit is reset, the COE function in the receiver is disabled and the
 * corresponding PCE and IP HCE status bits are always cleared.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description      
 * :---------------------------------|:------|:------------------
 *  ALT_EMAC_GMAC_MAC_CFG_IPC_E_END  | 0x1   | Checksum Enabled 
 *  ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD | 0x0   | Checksum Disabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC
 * 
 * Checksum Enabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_END     0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC
 * 
 * Checksum Disabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD    0x0

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_IPC_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_IPC_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_IPC_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IPC register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IPC register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_IPC_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_IPC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_IPC_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_IPC field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_IPC_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_IPC register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : Duplex Mode - dm
 * 
 * When this bit is set, the MAC operates in the full-duplex mode where it can
 * transmit and receive simultaneously.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description             
 * :--------------------------------|:------|:-------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_DM_E_END  | 0x1   | MAC Full Duplex Enabled 
 *  ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD | 0x0   | MAC Full Duplex Disabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM
 * 
 * MAC Full Duplex Enabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_DM_E_END  0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM
 * 
 * MAC Full Duplex Disabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD 0x0

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DM_MSB        11
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DM register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_DM_SET_MSK    0x00000800
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DM register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_DM_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DM register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_DM field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_DM_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_DM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_DM_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Loopback Mode - lm
 * 
 * When this bit is set, the MAC operates in the loopback mode at GMII or MII. The
 * (G)MII Receive clock input is required for the loopback to work properly,
 * because the Transmit clock is not looped-back internally.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description      
 * :--------------------------------|:------|:------------------
 *  ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD | 0x0   | Disable Loop Back
 *  ALT_EMAC_GMAC_MAC_CFG_LM_E_END  | 0x1   | Enable Loop Back 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM
 * 
 * Disable Loop Back
 */
#define ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM
 * 
 * Enable Loop Back
 */
#define ALT_EMAC_GMAC_MAC_CFG_LM_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
#define ALT_EMAC_GMAC_MAC_CFG_LM_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
#define ALT_EMAC_GMAC_MAC_CFG_LM_MSB        12
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
#define ALT_EMAC_GMAC_MAC_CFG_LM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LM register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_LM_SET_MSK    0x00001000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LM register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_LM_CLR_MSK    0xffffefff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_LM register field. */
#define ALT_EMAC_GMAC_MAC_CFG_LM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_LM field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_LM_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_LM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_LM_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Disable Receive Own - do
 * 
 * When this bit is set, the MAC disables the reception of frames when the
 * gmii_txen_o is asserted in the half-duplex mode.
 * 
 * When this bit is reset, the MAC receives all packets that are given by the PHY
 * while transmitting.
 * 
 * This bit is not applicable if the MAC is operating in the full-duplex mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                     
 * :--------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_DO_E_END  | 0x0   | MAC Enables Reception of Frames 
 *  ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD | 0x1   | MAC Disables Reception of Frames
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO
 * 
 * MAC Enables Reception of Frames
 */
#define ALT_EMAC_GMAC_MAC_CFG_DO_E_END  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO
 * 
 * MAC Disables Reception of Frames
 */
#define ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD 0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DO_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DO_MSB        13
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DO_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DO register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_DO_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DO register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_DO_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DO register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DO_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_DO field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_DO_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_DO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_DO_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : Speed - fes
 * 
 * This bit selects the speed in the RMII/RGMII interface:
 * 
 * * 0: 10 Mbps
 * 
 * * 1: 100 Mbps
 * 
 * This bit generates link speed encoding when TC (Bit 24) is set in the RGMII,
 * SMII, or SGMII mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description     
 * :-------------------------------------|:------|:-----------------
 *  ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10  | 0x0   | Speed = 10 Mbps 
 *  ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100 | 0x1   | Speed = 100 Mbps
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES
 * 
 * Speed = 10 Mbps
 */
#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10     0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES
 * 
 * Speed = 100 Mbps
 */
#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
#define ALT_EMAC_GMAC_MAC_CFG_FES_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
#define ALT_EMAC_GMAC_MAC_CFG_FES_MSB        14
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
#define ALT_EMAC_GMAC_MAC_CFG_FES_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_FES register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_FES_SET_MSK    0x00004000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_FES register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_FES_CLR_MSK    0xffffbfff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_FES register field. */
#define ALT_EMAC_GMAC_MAC_CFG_FES_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_FES field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_FES_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_FES register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_FES_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : Port Select - ps
 * 
 * This bit selects between GMII and MII
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description    
 * :---------------------------------------|:------|:----------------
 *  ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL | 0x0   | GMII 1000 Mbps 
 *  ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL | 0x1   | MII 10/100 Mbps
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS
 * 
 * GMII 1000 Mbps
 */
#define ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS
 * 
 * MII 10/100 Mbps
 */
#define ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_PS_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_PS_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_PS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PS register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_PS_SET_MSK    0x00008000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PS register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_PS_CLR_MSK    0xffff7fff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_PS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_PS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_PS field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_PS_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_PS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_PS_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Disable Carrier Sense During Transmission - dcrs
 * 
 * When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal
 * during frame transmission in the half-duplex mode. This request results in no
 * errors generated because of Loss of Carrier or No Carrier during such
 * transmission. When this bit is low, the MAC transmitter generates such errors
 * because of Carrier Sense and can even abort the transmissions.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                     
 * :----------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD | 0x0   | MAC Tx Gen. Err. No Carrier     
 *  ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END  | 0x1   | MAC Tx Ignores (G)MII Crs Signal
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS
 * 
 * MAC Tx Gen. Err. No Carrier
 */
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS
 * 
 * MAC Tx Ignores (G)MII Crs Signal
 */
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field. */
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_DCRS field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_DCRS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Inter-Frame Gap - ifg
 * 
 * These bits control the minimum IFG between frames during transmission.
 * 
 * In the half-duplex mode, the minimum IFG can be configured only for 64 bit times
 * (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum
 * IFG supported is 80 bit times (and above).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                 
 * :------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES | 0x0   | Inter Frame Gap 96 bit times
 *  ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES | 0x1   | Inter Frame Gap 88 bit times
 *  ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES | 0x2   | Inter Frame Gap 80 bit times
 *  ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES | 0x3   | Inter Frame Gap 72 bit times
 *  ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES | 0x4   | Inter Frame Gap 64 bit times
 *  ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES | 0x5   | Inter Frame Gap 56 bit times
 *  ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES | 0x6   | Inter Frame Gap 48 bit times
 *  ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES | 0x7   | Inter Frame Gap 40 bit times
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
 * 
 * Inter Frame Gap 96 bit times
 */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
 * 
 * Inter Frame Gap 88 bit times
 */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES   0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
 * 
 * Inter Frame Gap 80 bit times
 */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES   0x2
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
 * 
 * Inter Frame Gap 72 bit times
 */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES   0x3
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
 * 
 * Inter Frame Gap 64 bit times
 */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES   0x4
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
 * 
 * Inter Frame Gap 56 bit times
 */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES   0x5
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
 * 
 * Inter Frame Gap 48 bit times
 */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES   0x6
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG
 * 
 * Inter Frame Gap 40 bit times
 */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES   0x7

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_WIDTH      3
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IFG register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET_MSK    0x000e0000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IFG register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_CLR_MSK    0xfff1ffff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_IFG register field. */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_IFG field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_GET(value) (((value) & 0x000e0000) >> 17)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_IFG register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET(value) (((value) << 17) & 0x000e0000)

/*
 * Field : Jumbo Frame Enable - je
 * 
 * When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes
 * for VLAN tagged frames) without reporting a giant frame error in the receive
 * frame status.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description             
 * :--------------------------------|:------|:-------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD | 0x0   | Report Jumbo Frame Error
 *  ALT_EMAC_GMAC_MAC_CFG_JE_E_END  | 0x1   | Ignore Jumbo Frame Error
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE
 * 
 * Report Jumbo Frame Error
 */
#define ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE
 * 
 * Ignore Jumbo Frame Error
 */
#define ALT_EMAC_GMAC_MAC_CFG_JE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_JE_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_JE_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_JE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JE register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_JE_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JE register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_JE_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_JE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_JE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_JE field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_JE_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_JE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_JE_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Frame Burst Enable - be
 * 
 * When this bit is set, the MAC allows frame bursting during transmission in the
 * GMII half-duplex mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description           
 * :--------------------------------|:------|:-----------------------
 *  ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD | 0x0   | Frame Burst Enable OFF
 *  ALT_EMAC_GMAC_MAC_CFG_BE_E_END  | 0x1   | Frame Burst Enable ON 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE
 * 
 * Frame Burst Enable OFF
 */
#define ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE
 * 
 * Frame Burst Enable ON
 */
#define ALT_EMAC_GMAC_MAC_CFG_BE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_BE_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_BE_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_BE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BE register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_BE_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BE register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_BE_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_BE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_BE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_BE field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_BE_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_BE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_BE_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Jabber Disable - jd
 * 
 * When this bit is set, the MAC disables the jabber timer on the transmitter. The
 * MAC can transfer frames of up to 16,384 bytes.
 * 
 * When this bit is reset, the MAC cuts off the transmitter if the application
 * sends out more than 2,048 bytes of data (10,240 if JE is set high) during
 * transmission.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description           
 * :--------------------------------|:------|:-----------------------
 *  ALT_EMAC_GMAC_MAC_CFG_JD_E_END  | 0x0   | MAC cuts off TX > 2048
 *  ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD | 0x1   | Jabber Timer Disabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD
 * 
 * MAC cuts off TX > 2048
 */
#define ALT_EMAC_GMAC_MAC_CFG_JD_E_END  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD
 * 
 * Jabber Timer Disabled
 */
#define ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD 0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_JD_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_JD_MSB        22
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_JD_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JD register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_JD_SET_MSK    0x00400000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JD register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_JD_CLR_MSK    0xffbfffff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_JD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_JD_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_JD field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_JD_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_JD register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_JD_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : Watchdog Disable - wd
 * 
 * When this bit is set, the MAC disables the watchdog timer on the receiver. The
 * MAC can receive frames of up to 16,384 bytes.
 * 
 * When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if
 * JE is set high) of the frame being received. The MAC cuts off any bytes received
 * after 2,048 bytes.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                  
 * :--------------------------------|:------|:------------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_WD_E_END  | 0x0   | Enable MAC cutoff > 2048Bytes
 *  ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD | 0x1   | Disable Watchdog             
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD
 * 
 * Enable MAC cutoff > 2048Bytes
 */
#define ALT_EMAC_GMAC_MAC_CFG_WD_E_END  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD
 * 
 * Disable Watchdog
 */
#define ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD 0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_WD_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_WD_MSB        23
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_WD_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_WD register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_WD_SET_MSK    0x00800000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_WD register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_WD_CLR_MSK    0xff7fffff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_WD register field. */
#define ALT_EMAC_GMAC_MAC_CFG_WD_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_WD field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_WD_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_WD register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_WD_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : Transmit Configuration in RGMII, SGMII, or SMII - tc
 * 
 * When set, this bit enables the transmission of duplex mode, link speed, and link
 * up or down information to the PHY in the RGMII. When this bit is reset, no such
 * information is driven to the PHY.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                   
 * :--------------------------------|:------|:-------------------------------
 *  ALT_EMAC_GMAC_MAC_CFG_TC_E_END  | 0x1   | Enables Transmission of duplex
 *  ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD | 0x0   | Disables Transmission to Phy  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC
 * 
 * Enables Transmission of duplex
 */
#define ALT_EMAC_GMAC_MAC_CFG_TC_E_END  0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC
 * 
 * Disables Transmission to Phy
 */
#define ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD 0x0

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TC_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TC_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TC_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TC register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_TC_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TC register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_TC_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TC register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TC_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_TC field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_TC_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_TC register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_TC_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : CRC Stripping of Type Frames - cst
 * 
 * When set, the last 4 bytes (FCS) of all frames of Ether type (type field greater
 * than 0x0600) are stripped and dropped before forwarding the frame to the
 * application. This function is not valid when the IP Checksum Engine (Type 1) is
 * enabled in the MAC receiver.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description           
 * :---------------------------------|:------|:-----------------------
 *  ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD | 0x0   | Strip Ether Frames Off
 *  ALT_EMAC_GMAC_MAC_CFG_CST_E_END  | 0x1   | Strip Ether Frames On 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST
 * 
 * Strip Ether Frames Off
 */
#define ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST
 * 
 * Strip Ether Frames On
 */
#define ALT_EMAC_GMAC_MAC_CFG_CST_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
#define ALT_EMAC_GMAC_MAC_CFG_CST_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
#define ALT_EMAC_GMAC_MAC_CFG_CST_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
#define ALT_EMAC_GMAC_MAC_CFG_CST_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_CST register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_CST_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_CST register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_CST_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_CST register field. */
#define ALT_EMAC_GMAC_MAC_CFG_CST_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_CST field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_CST_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_CST register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_CST_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : IEEE 802.3as support for 2K packets Enable - twokpe
 * 
 * When set, the MAC considers all frames, with up to 2,000 bytes length, as normal
 * packets. When Bit 20 (Jumbo Enable) is not set, the MAC considers all received
 * frames of size more than 2K bytes as Giant frames.
 * 
 * When this bit is reset and Bit 20 (Jumbo Enable) is not set, the MAC considers
 * all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as
 * Giant frames.
 * 
 * When Bit 20 (Jumbo Enable) is set, setting this bit has no effect on Giant Frame
 * status.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value. */
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field. */
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_CFG_TWOKPE field value from a register. */
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET(value) (((value) << 27) & 0x08000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_CFG.
 */
struct ALT_EMAC_GMAC_MAC_CFG_s
{
    uint32_t  prelen :  2;  /* Preamble Length for Transmit Frames */
    uint32_t  re     :  1;  /* Receiver Enable */
    uint32_t  te     :  1;  /* Transmitter Enable */
    uint32_t  dc     :  1;  /* Deferral Check */
    uint32_t  bl     :  2;  /* Back-Off Limit */
    uint32_t  acs    :  1;  /* Automatic Pad or CRC Stripping */
    uint32_t  lud    :  1;  /* Link Up or Down */
    uint32_t  dr     :  1;  /* Disable Retry */
    uint32_t  ipc    :  1;  /* Checksum Offload */
    uint32_t  dm     :  1;  /* Duplex Mode */
    uint32_t  lm     :  1;  /* Loopback Mode */
    uint32_t  do_    :  1;  /* Disable Receive Own */
    uint32_t  fes    :  1;  /* Speed */
    uint32_t  ps     :  1;  /* Port Select */
    uint32_t  dcrs   :  1;  /* Disable Carrier Sense During Transmission */
    uint32_t  ifg    :  3;  /* Inter-Frame Gap */
    uint32_t  je     :  1;  /* Jumbo Frame Enable */
    uint32_t  be     :  1;  /* Frame Burst Enable */
    uint32_t  jd     :  1;  /* Jabber Disable */
    uint32_t  wd     :  1;  /* Watchdog Disable */
    uint32_t  tc     :  1;  /* Transmit Configuration in RGMII, SGMII, or SMII */
    uint32_t  cst    :  1;  /* CRC Stripping of Type Frames */
    uint32_t         :  1;  /* *UNDEFINED* */
    uint32_t  twokpe :  1;  /* IEEE 802.3as support for 2K packets Enable */
    uint32_t         :  4;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_CFG. */
typedef volatile struct ALT_EMAC_GMAC_MAC_CFG_s  ALT_EMAC_GMAC_MAC_CFG_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_CFG register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_CFG_OFST        0x0
/* The address of the ALT_EMAC_GMAC_MAC_CFG register. */
#define ALT_EMAC_GMAC_MAC_CFG_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_CFG_OFST))

/*
 * Register : Register 1 (MAC Frame Filter) - MAC_Frame_Filter
 * 
 * The MAC Frame Filter register contains the filter controls for receiving frames.
 * Some of the controls from this register go to the address check block of the
 * MAC, which performs the first level of address filtering. The second level of
 * filtering is performed on the incoming frame, based on other controls such as
 * Pass Bad Frames and Pass Control Frames.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Promiscuous Mode                 
 *  [1]     | RW     | 0x0   | Hash Unicast                     
 *  [2]     | RW     | 0x0   | Hash Multicast                   
 *  [3]     | RW     | 0x0   | DA Inverse Filtering             
 *  [4]     | RW     | 0x0   | Pass All Multicast               
 *  [5]     | RW     | 0x0   | Disable Broadcast Frames         
 *  [7:6]   | RW     | 0x0   | Pass Control Frames              
 *  [8]     | RW     | 0x0   | SA Inverse Filtering             
 *  [9]     | RW     | 0x0   | Source Address Filter Enable     
 *  [10]    | RW     | 0x0   | Hash or Perfect Filter           
 *  [15:11] | ???    | 0x0   | *UNDEFINED*                      
 *  [16]    | RW     | 0x0   | VLAN Tag Filter Enable           
 *  [19:17] | ???    | 0x0   | *UNDEFINED*                      
 *  [20]    | RW     | 0x0   | Layer 3 and Layer 4 Filter Enable
 *  [21]    | RW     | 0x0   | Drop non-TCP/UDP over IP Frames  
 *  [30:22] | ???    | 0x0   | *UNDEFINED*                      
 *  [31]    | RW     | 0x0   | Receive All                      
 * 
 */
/*
 * Field : Promiscuous Mode - pr
 * 
 * When this bit is set, the Address Filter block passes all incoming frames
 * regardless of its destination or source address. The SA or DA Filter Fails
 * status bits of the Receive Status Word are always cleared when PR is set.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description               
 * :------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END  | 0x1   | All Incoming Frames Passed
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD | 0x0   | Clear SA DA Status Bits   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PR
 * 
 * All Incoming Frames Passed
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END  0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PR
 * 
 * Clear SA DA Status Bits
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD 0x0

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PR field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Hash Unicast - huc
 * 
 * When set, MAC performs destination address filtering of unicast frames according
 * to the hash table.
 * 
 * When reset, the MAC performs a perfect destination address filtering for unicast
 * frames, that is, it compares the DA field with the values programmed in DA
 * registers.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END  | 0x1   | MAC Filters with Hash Table
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD | 0x0   | MAC Filters with Compare   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HUC
 * 
 * MAC Filters with Hash Table
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END     0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HUC
 * 
 * MAC Filters with Compare
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD    0x0

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Hash Multicast - hmc
 * 
 * When set, MAC performs destination address filtering of received multicast
 * frames according to the hash table.
 * 
 * When reset, the MAC performs a perfect destination address filtering for
 * multicast frames, that is, it compares the DA field with the values programmed
 * in DA registers.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD | 0x0   | MAC Filters with Hash Table
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END  | 0x1   | MAC Filters with Compare   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HMC
 * 
 * MAC Filters with Hash Table
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HMC
 * 
 * MAC Filters with Compare
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : DA Inverse Filtering - daif
 * 
 * When this bit is set, the Address Check block operates in inverse filtering mode
 * for the DA address comparison for both unicast and multicast frames.
 * 
 * When reset, normal filtering of frames is performed.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                       
 * :--------------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD | 0x0   | Normal Inverse Filter             
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END  | 0x1   | Address Check Block Inverse Filter
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF
 * 
 * Normal Inverse Filter
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF
 * 
 * Address Check Block Inverse Filter
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Pass All Multicast - pm
 * 
 * When set, this bit indicates that all received frames with a multicast
 * destination address (first bit in the destination address field is '1') are
 * passed.
 * 
 * When reset, filtering of multicast frame depends on HMC bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description               
 * :------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD | 0x0   | Allows Filter of MC Frames
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END  | 0x1   | All Rcvd MC Frames Pass   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PM
 * 
 * Allows Filter of MC Frames
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PM
 * 
 * All Rcvd MC Frames Pass
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PM field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Disable Broadcast Frames - dbf
 * 
 * When this bit is set, the AFM block filters all incoming broadcast frames. In
 * addition, it overrides all other filter settings.
 * 
 * When this bit is reset, the AFM block passes all received broadcast frames.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                
 * :-------------------------------------|:------|:----------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD | 0x0   | Pass All Broadcast Frames  
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END  | 0x1   | Filter All Broadcast Frames
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DBF
 * 
 * Pass All Broadcast Frames
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DBF
 * 
 * Filter All Broadcast Frames
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Pass Control Frames - pcf
 * 
 * These bits control the forwarding of all control frames (including unicast and
 * multicast PAUSE frames).
 * 
 * * 00: MAC filters all control frames from reaching the application.
 * 
 * * 01: MAC forwards all control frames except PAUSE control frames to application
 *   even if they fail the Address filter.
 * 
 * * 10: MAC forwards all control frames to application even if they fail the
 *   Address Filter.
 * 
 * * 11: MAC forwards control frames that pass the Address Filter.
 * 
 * The following conditions should be true for the PAUSE control frames processing:
 * 
 * * Condition 1: The MAC is in the full-duplex mode and flow control is enabled by
 *   setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1.
 * 
 * * Condition 2: The destination address (DA) of the received frame matches the
 *   special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register
 *   6 (Flow Control Register) is set.
 * 
 * * Condition 3: The Type field of the received frame is 0x8808 and the OPCODE
 *   field is 0x0001.
 * 
 * This field should be set to 01 only when the Condition 1 is true, that is, the
 * MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled.
 * Otherwise, the PAUSE frame filtering may be inconsistent. When Condition 1 is
 * false, the PAUSE frames are considered as generic control frames. Therefore, to
 * pass all control frames (including PAUSE control frames) when the full-duplex
 * mode and flow control is not enabled, you should set the PCF field to 10 or 11
 * (as required by the application).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                                  
 * :---------------------------------------------|:------|:----------------------------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR | 0x0   | MAC filters all control frames               
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE | 0x1   | MAC forwards all control frames except PAUSE 
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL   | 0x2   | MAC forwards all control frames fail addrflt 
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS   | 0x3   | MAC forwards control frames that pass addrflt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
 * 
 * MAC filters all control frames
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
 * 
 * MAC forwards all control frames except PAUSE
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE    0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
 * 
 * MAC forwards all control frames fail addrflt
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL      0x2
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
 * 
 * MAC forwards control frames that pass addrflt
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS      0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET_MSK    0x000000c0
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_CLR_MSK    0xffffff3f
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_GET(value) (((value) & 0x000000c0) >> 6)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET(value) (((value) << 6) & 0x000000c0)

/*
 * Field : SA Inverse Filtering - saif
 * 
 * When this bit is set, the Address Check block operates in inverse filtering mode
 * for the SA address comparison. The frames whose SA matches the SA registers are
 * marked as failing the SA Address filter.
 * 
 * When this bit is reset, frames whose SA does not match the SA registers are
 * marked as failing the SA Address filter.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description    
 * :--------------------------------------|:------|:----------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD | 0x0   | SA Nomatch Fail
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END  | 0x1   | SA Match Fail  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF
 * 
 * SA Nomatch Fail
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF
 * 
 * SA Match Fail
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Source Address Filter Enable - saf
 * 
 * When this bit is set, the MAC compares the SA field of the received frames with
 * the values programmed in the enabled SA registers. If the comparison matches,
 * then the SA Match bit of RxStatus Word is set high. When this bit is set high
 * and the SA filter fails, the MAC drops the frame.
 * 
 * When this bit is reset, the MAC forwards the received frame to the application
 * and with the updated SA Match bit of the RxStatus depending on the SA address
 * comparison.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description  
 * :-------------------------------------|:------|:--------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD | 0x0   | SA Filter Off
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END  | 0x1   | SA Filter On 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAF
 * 
 * SA Filter Off
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAF
 * 
 * SA Filter On
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Hash or Perfect Filter - hpf
 * 
 * When this bit is set, it configures the address filter to pass a frame if it
 * matches either the perfect filtering or the hash filtering as set by the HMC or
 * HUC bits.
 * 
 * When this bit is low and the HUC or HMC bit is set, the frame is passed only if
 * it matches the Hash filter.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description               
 * :-------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD | 0x0   | Hash or Perfect Filter off
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END  | 0x1   | Hash or Perfect Filter on 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HPF
 * 
 * Hash or Perfect Filter off
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HPF
 * 
 * Hash or Perfect Filter on
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : VLAN Tag Filter Enable - vtfe
 * 
 * When set, this bit enables the MAC to drop VLAN tagged frames that do not match
 * the VLAN Tag comparison.
 * 
 * When reset, the MAC forwards all frames irrespective of the match status of the
 * VLAN Tag.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                  
 * :----------------------------------------|:------|:----------------------------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP | 0x0   | Forward all frames irrespective of the match 
 * :                                        |       | status of the VLAN tag                       
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP   | 0x1   | Drop VLAN tagged frames that do not match the
 * :                                        |       | VLAN Tag comparison                          
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE
 * 
 * Forward all frames irrespective of the match status of the VLAN tag
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE
 * 
 * Drop VLAN tagged frames that do not match the VLAN Tag comparison
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Layer 3 and Layer 4 Filter Enable - ipfe
 * 
 * When set, this bit enables the MAC to drop frames that do not match the enabled
 * Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for
 * matching, this bit does not have any effect.
 * 
 * When reset, the MAC forwards all frames irrespective of the match status of the
 * Layer 3 and Layer 4 filters.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                    
 * :----------------------------------------|:------|:------------------------------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP | 0x0   | Forward all frames irrespective of the match   
 * :                                        |       | status of Layer 3 and Layer 4 filters          
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP   | 0x1   | Drop frames that do not match the enabled Layer
 * :                                        |       | 3 and Layer 4 filters                          
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE
 * 
 * Forward all frames irrespective of the match status of Layer 3 and Layer 4
 * filters
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE
 * 
 * Drop frames that do not match the enabled Layer 3 and Layer 4 filters
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Drop non-TCP/UDP over IP Frames - dntu
 * 
 * When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames.
 * The MAC forward only those frames that are processed by the Layer 4 filter.
 * 
 * When reset, this bit enables the MAC to forward all non-TCP or UDP over IP
 * frames.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                              
 * :----------------------------------------|:------|:------------------------------------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP | 0x0   | Forward all non-TCP or UDP over IP frames
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP   | 0x1   | Drop non-TCP or UDP over IP frames       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU
 * 
 * Forward all non-TCP or UDP over IP frames
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU
 * 
 * Drop non-TCP or UDP over IP frames
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Receive All - ra
 * 
 * When this bit is set, the MAC Receiver block passes all received frames,
 * irrespective of whether they pass the address filter or not, to the Application.
 * The result of the SA or DA filtering is updated (pass or fail) in the
 * corresponding bits in the Receive Status Word.
 * 
 * When this bit is reset, the Receiver block passes only those frames to the
 * Application that pass the SA or DA address filter.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description    
 * :------------------------------------|:------|:----------------
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD | 0x0   | Receive All off
 *  ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END  | 0x1   | Receive All On 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_RA
 * 
 * Receive All off
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_RA
 * 
 * Receive All On
 */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RA field value from a register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_FRM_FLT.
 */
struct ALT_EMAC_GMAC_MAC_FRM_FLT_s
{
    uint32_t  pr   :  1;  /* Promiscuous Mode */
    uint32_t  huc  :  1;  /* Hash Unicast */
    uint32_t  hmc  :  1;  /* Hash Multicast */
    uint32_t  daif :  1;  /* DA Inverse Filtering */
    uint32_t  pm   :  1;  /* Pass All Multicast */
    uint32_t  dbf  :  1;  /* Disable Broadcast Frames */
    uint32_t  pcf  :  2;  /* Pass Control Frames */
    uint32_t  saif :  1;  /* SA Inverse Filtering */
    uint32_t  saf  :  1;  /* Source Address Filter Enable */
    uint32_t  hpf  :  1;  /* Hash or Perfect Filter */
    uint32_t       :  5;  /* *UNDEFINED* */
    uint32_t  vtfe :  1;  /* VLAN Tag Filter Enable */
    uint32_t       :  3;  /* *UNDEFINED* */
    uint32_t  ipfe :  1;  /* Layer 3 and Layer 4 Filter Enable */
    uint32_t  dntu :  1;  /* Drop non-TCP/UDP over IP Frames */
    uint32_t       :  9;  /* *UNDEFINED* */
    uint32_t  ra   :  1;  /* Receive All */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_FRM_FLT. */
typedef volatile struct ALT_EMAC_GMAC_MAC_FRM_FLT_s  ALT_EMAC_GMAC_MAC_FRM_FLT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_FRM_FLT register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_OFST        0x4
/* The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register. */
#define ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_FRM_FLT_OFST))

/*
 * Register : Register 4 (GMII Address Register) - GMII_Address
 * 
 * The GMII Address register controls the management cycles to the external PHY
 * through the management interface.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description           
 * :--------|:-------|:------|:-----------------------
 *  [0]     | RW     | 0x0   | GMII Busy             
 *  [1]     | RW     | 0x0   | GMII Write            
 *  [5:2]   | RW     | 0x0   | CSR Clock Range       
 *  [10:6]  | RW     | 0x0   | GMII Register         
 *  [15:11] | RW     | 0x0   | Physical Layer Address
 *  [31:16] | ???    | 0x0   | *UNDEFINED*           
 * 
 */
/*
 * Field : GMII Busy - gb
 * 
 * This bit should read logic 0 before writing to Register 4 and Register 5. During
 * a PHY or RevMII register access, the software sets this bit to 1'b1 to indicate
 * that a Read or Write access is in progress.
 * 
 * The Register 5 is invalid until this bit is cleared by the MAC. Therefore,
 * Register 5 (GMII Data) should be kept valid until the MAC clears this bit during
 * a PHY Write operation. Similarly for a read operation, the contents of Register
 * 5 are not valid until this bit is cleared.
 * 
 * The subsequent read or write operation should happen only after the previous
 * operation is complete. Because there is no acknowledgment from the PHY to MAC
 * after a read or write operation is completed, there is no change in the
 * functionality of this bit even when the PHY is not present.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description
 * :----------------------------------|:------|:------------
 *  ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD | 0x0   | Not Busy   
 *  ALT_EMAC_GMAC_GMII_ADDR_GB_E_END  | 0x1   | Busy       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GB
 * 
 * Not Busy
 */
#define ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GB
 * 
 * Busy
 */
#define ALT_EMAC_GMAC_GMII_ADDR_GB_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GB_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GB_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GB_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GB register field value. */
#define ALT_EMAC_GMAC_GMII_ADDR_GB_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GB register field value. */
#define ALT_EMAC_GMAC_GMII_ADDR_GB_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GB register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GB_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GB field value from a register. */
#define ALT_EMAC_GMAC_GMII_ADDR_GB_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_GMII_ADDR_GB register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_GMII_ADDR_GB_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : GMII Write - gw
 * 
 * When set, this bit indicates to the PHY or RevMII that this is a Write operation
 * using the GMII Data register. If this bit is not set, it indicates that this is
 * a Read operation, that is, placing the data in the GMII Data register.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description         
 * :----------------------------------|:------|:---------------------
 *  ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD | 0x0   | Gmii Write Operation
 *  ALT_EMAC_GMAC_GMII_ADDR_GW_E_END  | 0x1   | Gmii Read Operation 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GW
 * 
 * Gmii Write Operation
 */
#define ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GW
 * 
 * Gmii Read Operation
 */
#define ALT_EMAC_GMAC_GMII_ADDR_GW_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GW_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GW_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GW_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GW register field value. */
#define ALT_EMAC_GMAC_GMII_ADDR_GW_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GW register field value. */
#define ALT_EMAC_GMAC_GMII_ADDR_GW_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GW register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GW_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GW field value from a register. */
#define ALT_EMAC_GMAC_GMII_ADDR_GW_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_GMII_ADDR_GW register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_GMII_ADDR_GW_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : CSR Clock Range - cr
 * 
 * The CSR Clock Range selection determines the frequency of the MDC clock
 * according to the l3_sp_clk frequency used in your design. The suggested range of
 * l3_sp_clk frequency applicable for each value (when Bit[5] = 0) ensures that the
 * MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.
 * 
 * When Bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE
 * 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower
 * value. For example, when l3_sp_clk is of 100 MHz frequency and you program these
 * bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the
 * limit of IEEE 802.3 specified range. Only use the values larger than 7 if the
 * interfacing chips support faster MDC clocks.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                     
 * :----------------------------------------|:------|:-------------------------------------------------
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42      | 0x0   | l3_sp_clk 60-100Mhz  and MDC clock =            
 * :                                        |       | l3_sp_clk/42                                    
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62      | 0x1   | l3_sp_clk 100-150Mhz and MDC clock =            
 * :                                        |       | l3_sp_clk/62                                    
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16      | 0x2   | l3_sp_clk 25-35Mhz and MDC clock  = l3_sp_clk/16
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26      | 0x3   | l3_sp_clk 35-60Mhz and MDC clock  = l3_sp_clk/26
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102     | 0x4   | l3_sp_clk 150-250Mhz and MDC clock =            
 * :                                        |       | l3_sp_clk/102                                   
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124     | 0x5   | l3_sp_clk 250-300Mhz and MDC clock =            
 * :                                        |       | l3_sp_clk/124                                   
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4       | 0x8   | l3_sp_clk/4                                     
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6       | 0x9   | l3_sp_clk/6                                     
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8       | 0xa   | l3_sp_clk/8                                     
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10      | 0xb   | l3_sp_clk/10                                    
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12      | 0xc   | l3_sp_clk/12                                    
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14      | 0xd   | l3_sp_clk/14                                    
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN | 0xe   | l3_sp_clk/16                                    
 *  ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18      | 0xf   | l3_sp_clk/18                                    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk 60-100Mhz  and MDC clock =  l3_sp_clk/42
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42      0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk 100-150Mhz and MDC clock =  l3_sp_clk/62
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62      0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk 25-35Mhz and MDC clock  = l3_sp_clk/16
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16      0x2
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk 35-60Mhz and MDC clock  = l3_sp_clk/26
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26      0x3
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk 150-250Mhz and MDC clock = l3_sp_clk/102
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102     0x4
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk 250-300Mhz and MDC clock = l3_sp_clk/124
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124     0x5
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk/4
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4       0x8
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk/6
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6       0x9
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk/8
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8       0xa
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk/10
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10      0xb
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk/12
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12      0xc
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk/14
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14      0xd
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk/16
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN 0xe
/*
 * Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
 * 
 * l3_sp_clk/18
 */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18      0xf

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_WIDTH      4
/* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_CR register field value. */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_SET_MSK    0x0000003c
/* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_CR register field value. */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_CLR_MSK    0xffffffc3
/* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_CR register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_GMII_ADDR_CR field value from a register. */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_GET(value) (((value) & 0x0000003c) >> 2)
/* Produces a ALT_EMAC_GMAC_GMII_ADDR_CR register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_GMII_ADDR_CR_SET(value) (((value) << 2) & 0x0000003c)

/*
 * Field : GMII Register - gr
 * 
 * These bits select the desired GMII register in the selected PHY device.
 * 
 * For RevMII, these bits select the desired CSR register in the RevMII Registers
 * set.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GR_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GR_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GR_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GR register field value. */
#define ALT_EMAC_GMAC_GMII_ADDR_GR_SET_MSK    0x000007c0
/* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GR register field value. */
#define ALT_EMAC_GMAC_GMII_ADDR_GR_CLR_MSK    0xfffff83f
/* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GR register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_GR_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_GMII_ADDR_GR field value from a register. */
#define ALT_EMAC_GMAC_GMII_ADDR_GR_GET(value) (((value) & 0x000007c0) >> 6)
/* Produces a ALT_EMAC_GMAC_GMII_ADDR_GR register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_GMII_ADDR_GR_SET(value) (((value) << 6) & 0x000007c0)

/*
 * Field : Physical Layer Address - pa
 * 
 * This field indicates which of the 32 possible PHY devices are being accessed.
 * 
 * For RevMII, this field gives the PHY Address of the RevMII block.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_PA_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_PA_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_PA_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_PA register field value. */
#define ALT_EMAC_GMAC_GMII_ADDR_PA_SET_MSK    0x0000f800
/* The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_PA register field value. */
#define ALT_EMAC_GMAC_GMII_ADDR_PA_CLR_MSK    0xffff07ff
/* The reset value of the ALT_EMAC_GMAC_GMII_ADDR_PA register field. */
#define ALT_EMAC_GMAC_GMII_ADDR_PA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_GMII_ADDR_PA field value from a register. */
#define ALT_EMAC_GMAC_GMII_ADDR_PA_GET(value) (((value) & 0x0000f800) >> 11)
/* Produces a ALT_EMAC_GMAC_GMII_ADDR_PA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_GMII_ADDR_PA_SET(value) (((value) << 11) & 0x0000f800)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_GMII_ADDR.
 */
struct ALT_EMAC_GMAC_GMII_ADDR_s
{
    uint32_t  gb :  1;  /* GMII Busy */
    uint32_t  gw :  1;  /* GMII Write */
    uint32_t  cr :  4;  /* CSR Clock Range */
    uint32_t  gr :  5;  /* GMII Register */
    uint32_t  pa :  5;  /* Physical Layer Address */
    uint32_t     : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_GMII_ADDR. */
typedef volatile struct ALT_EMAC_GMAC_GMII_ADDR_s  ALT_EMAC_GMAC_GMII_ADDR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_GMII_ADDR register from the beginning of the component. */
#define ALT_EMAC_GMAC_GMII_ADDR_OFST        0x10
/* The address of the ALT_EMAC_GMAC_GMII_ADDR register. */
#define ALT_EMAC_GMAC_GMII_ADDR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GMII_ADDR_OFST))

/*
 * Register : Register 5 (GMII Data Register) - GMII_Data
 * 
 * The GMII Data register stores Write data to be written to the PHY register
 * located at the address specified in Register 4 (GMII Address Register). This
 * register also stores the Read data from the PHY register located at the address
 * specified by Register 4.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description
 * :--------|:-------|:------|:------------
 *  [15:0]  | RW     | 0x0   | GMII Data  
 *  [31:16] | ???    | 0x0   | *UNDEFINED*
 * 
 */
/*
 * Field : GMII Data - gd
 * 
 * This field contains the 16-bit data value read from the PHY or RevMII after a
 * Management Read operation or the 16-bit data value to be written to the PHY or
 * RevMII before a Management Write operation.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
#define ALT_EMAC_GMAC_GMII_DATA_GD_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
#define ALT_EMAC_GMAC_GMII_DATA_GD_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
#define ALT_EMAC_GMAC_GMII_DATA_GD_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_GMII_DATA_GD register field value. */
#define ALT_EMAC_GMAC_GMII_DATA_GD_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_GMII_DATA_GD register field value. */
#define ALT_EMAC_GMAC_GMII_DATA_GD_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_GMII_DATA_GD register field. */
#define ALT_EMAC_GMAC_GMII_DATA_GD_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_GMII_DATA_GD field value from a register. */
#define ALT_EMAC_GMAC_GMII_DATA_GD_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_GMII_DATA_GD register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_GMII_DATA_GD_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_GMII_DATA.
 */
struct ALT_EMAC_GMAC_GMII_DATA_s
{
    uint32_t  gd : 16;  /* GMII Data */
    uint32_t     : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_GMII_DATA. */
typedef volatile struct ALT_EMAC_GMAC_GMII_DATA_s  ALT_EMAC_GMAC_GMII_DATA_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_GMII_DATA register from the beginning of the component. */
#define ALT_EMAC_GMAC_GMII_DATA_OFST        0x14
/* The address of the ALT_EMAC_GMAC_GMII_DATA register. */
#define ALT_EMAC_GMAC_GMII_DATA_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GMII_DATA_OFST))

/*
 * Register : Register 6 (Flow Control Register) - Flow_Control
 * 
 * The Flow Control register controls the generation and reception of the Control
 * (Pause Command) frames by the MAC's Flow control block. A Write to a register
 * with the Busy bit set to '1' triggers the Flow Control block to generate a Pause
 * Control frame. The fields of the control frame are selected as specified in the
 * 802.3x specification, and the Pause Time value from this register is used in the
 * Pause Time field of the control frame. The Busy bit remains set until the
 * control frame is transferred onto the cable. The Host must make sure that the
 * Busy bit is cleared before writing to the register.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                               
 * :--------|:-------|:------|:-------------------------------------------
 *  [0]     | RW     | 0x0   | Flow Control Busy or Backpressure Activate
 *  [1]     | RW     | 0x0   | Transmit Flow Control Enable              
 *  [2]     | RW     | 0x0   | Receive Flow Control Enable               
 *  [3]     | RW     | 0x0   | Unicast Pause Frame Detect                
 *  [5:4]   | RW     | 0x0   | Pause Low Threshold                       
 *  [6]     | ???    | 0x0   | *UNDEFINED*                               
 *  [7]     | RW     | 0x0   | Disable Zero-Quanta Pause                 
 *  [15:8]  | ???    | 0x0   | *UNDEFINED*                               
 *  [31:16] | RW     | 0x0   | Pause Time                                
 * 
 */
/*
 * Field : Flow Control Busy or Backpressure Activate - fca_bpa
 * 
 * This bit initiates a Pause Control frame in the full-duplex mode and activates
 * the backpressure function in the half-duplex mode if the TFE bit is set.
 * 
 * In the full-duplex mode, this bit should be read as 1'b0 before writing to the
 * Flow Control register. To initiate a Pause control frame, the Application must
 * set this bit to 1'b1. During a transfer of the Control Frame, this bit continues
 * to be set to signify that a frame transmission is in progress. After the
 * completion of Pause control frame transmission, the MAC resets this bit to 1'b0.
 * The Flow Control register should not be written to until this bit is cleared.
 * 
 * In the half-duplex mode, when this bit is set (and TFE is set), then
 * backpressure is asserted by the MAC. During backpressure, when the MAC receives
 * a new frame, the transmitter starts sending a JAM pattern resulting in a
 * collision. This control register bit is logically ORed with the mti_flowctrl_i
 * input signal for the backpressure function. When the MAC is configured for the
 * full-duplex mode, the BPA is automatically disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                  
 * :--------------------------------------|:------|:------------------------------
 *  ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD | 0x0   | Pause Ctrl Frame and BPA off 
 *  ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END  | 0x1   | Init Pause Ctrl Frame and BPA
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA
 * 
 * Pause Ctrl Frame and BPA off
 */
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA
 * 
 * Init Pause Ctrl Frame and BPA
 */
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA field value from a register. */
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Transmit Flow Control Enable - tfe
 * 
 * In the full-duplex mode, when this bit is set, the MAC enables the flow control
 * operation to transmit Pause frames. When this bit is reset, the flow control
 * operation in the MAC is disabled, and the MAC does not transmit any Pause
 * frames.
 * 
 * In half-duplex mode, when this bit is set, the MAC enables the back-pressure
 * operation. When this bit is reset, the back-pressure feature is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                  
 * :----------------------------------|:------|:------------------------------
 *  ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD | 0x0   | Transmit Flow Control Disable
 *  ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END  | 0x1   | Transmit Flow Control Enable 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE
 * 
 * Transmit Flow Control Disable
 */
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE
 * 
 * Transmit Flow Control Enable
 */
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_TFE field value from a register. */
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_FLOW_CTL_TFE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Receive Flow Control Enable - rfe
 * 
 * When this bit is set, the MAC decodes the received Pause frame and disables its
 * transmitter for a specified (Pause) time. When this bit is reset, the decode
 * function of the Pause frame is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                         
 * :----------------------------------|:------|:-------------------------------------
 *  ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD | 0x0   | Decode Func. of Pause Frame Disabled
 *  ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END  | 0x1   | MAC decodes the received Pause      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE
 * 
 * Decode Func. of Pause Frame Disabled
 */
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE
 * 
 * MAC decodes the received Pause
 */
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_RFE field value from a register. */
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_FLOW_CTL_RFE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Unicast Pause Frame Detect - up
 * 
 * When this bit is set, then in addition to the detecting Pause frames with the
 * unique multicast address, the MAC detects the Pause frames with the station's
 * unicast address specified in the MAC Address0 High Register and MAC Address0 Low
 * Register. When this bit is reset, the MAC detects only a Pause frame with the
 * unique multicast address specified in the 802.3x standard.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                  
 * :---------------------------------|:------|:------------------------------
 *  ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD | 0x0   | MAC Detects Pause MCA        
 *  ALT_EMAC_GMAC_FLOW_CTL_UP_E_END  | 0x1   | MAC Detects Pause MCA and UCA
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP
 * 
 * MAC Detects Pause MCA
 */
#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP
 * 
 * MAC Detects Pause MCA and UCA
 */
#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_UP_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_UP_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_UP_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_UP register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_UP register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_UP_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_UP register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_UP_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_UP field value from a register. */
#define ALT_EMAC_GMAC_FLOW_CTL_UP_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_FLOW_CTL_UP register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Pause Low Threshold - plt
 * 
 * This field configures the threshold of the PAUSE timer at which the input flow
 * control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic
 * retransmission of PAUSE Frame.
 * 
 * The threshold values should be always less than the Pause Time configured in
 * Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a
 * second PAUSE frame is automatically transmitted if the mti_flowctrl_i signal is
 * asserted at 228 (256 - 28) slot times after the first PAUSE frame is
 * transmitted.
 * 
 * The slot time is defined as the time taken to transmit 512 bits (64 bytes) on
 * the GMII or MII interface.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                
 * :-------------------------------------------|:------|:----------------------------
 *  ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4   | 0x0   | Pause time - 4 slot times  
 *  ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28  | 0x1   | Pause time - 28 slot times 
 *  ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144 | 0x2   | Pause time - 144 slot times
 *  ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256 | 0x3   | Pause time - 256 slot times
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
 * 
 * Pause time - 4 slot times
 */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
 * 
 * Pause time - 28 slot times
 */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28   0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
 * 
 * Pause time - 144 slot times
 */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144  0x2
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT
 * 
 * Pause time - 256 slot times
 */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256  0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET_MSK    0x00000030
/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_CLR_MSK    0xffffffcf
/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_PLT field value from a register. */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_GET(value) (((value) & 0x00000030) >> 4)
/* Produces a ALT_EMAC_GMAC_FLOW_CTL_PLT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET(value) (((value) << 4) & 0x00000030)

/*
 * Field : Disable Zero-Quanta Pause - dzpq
 * 
 * When this bit is set, it disables the automatic generation of the Zero-Quanta
 * Pause Control frames on the de-assertion of the flow-control signal from the
 * FIFO layer (MTL or external sideband flow control signal
 * sbd_flowctrl_i/mti_flowctrl_i).
 * 
 * When this bit is reset, normal operation with automatic Zero-Quanta Pause
 * Control frame generation is enabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                           
 * :-----------------------------------|:------|:---------------------------------------
 *  ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END  | 0x1   | Disable Auto Gen. of Zero-Quanta Pause
 *  ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD | 0x0   | Enable Auto Gen. of Zero-Quanta Pause 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ
 * 
 * Disable Auto Gen. of Zero-Quanta Pause
 */
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END   0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ
 * 
 * Enable Auto Gen. of Zero-Quanta Pause
 */
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD  0x0

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_DZPQ field value from a register. */
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Pause Time - pt
 * 
 * This field holds the value to be used in the Pause Time field in the transmit
 * control frame. Because the Pause Time bits are double-synchronized to the (G)MII
 * clock domain, then consecutive writes to this register should be performed only
 * after at least four clock cycles in the destination clock domain.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_PT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_PT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_PT_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PT register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET_MSK    0xffff0000
/* The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PT register field value. */
#define ALT_EMAC_GMAC_FLOW_CTL_PT_CLR_MSK    0x0000ffff
/* The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PT register field. */
#define ALT_EMAC_GMAC_FLOW_CTL_PT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_FLOW_CTL_PT field value from a register. */
#define ALT_EMAC_GMAC_FLOW_CTL_PT_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_EMAC_GMAC_FLOW_CTL_PT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET(value) (((value) << 16) & 0xffff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_FLOW_CTL.
 */
struct ALT_EMAC_GMAC_FLOW_CTL_s
{
    uint32_t  fca_bpa :  1;  /* Flow Control Busy or Backpressure Activate */
    uint32_t  tfe     :  1;  /* Transmit Flow Control Enable */
    uint32_t  rfe     :  1;  /* Receive Flow Control Enable */
    uint32_t  up      :  1;  /* Unicast Pause Frame Detect */
    uint32_t  plt     :  2;  /* Pause Low Threshold */
    uint32_t          :  1;  /* *UNDEFINED* */
    uint32_t  dzpq    :  1;  /* Disable Zero-Quanta Pause */
    uint32_t          :  8;  /* *UNDEFINED* */
    uint32_t  pt      : 16;  /* Pause Time */
};

/* The typedef declaration for register ALT_EMAC_GMAC_FLOW_CTL. */
typedef volatile struct ALT_EMAC_GMAC_FLOW_CTL_s  ALT_EMAC_GMAC_FLOW_CTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_FLOW_CTL register from the beginning of the component. */
#define ALT_EMAC_GMAC_FLOW_CTL_OFST        0x18
/* The address of the ALT_EMAC_GMAC_FLOW_CTL register. */
#define ALT_EMAC_GMAC_FLOW_CTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_FLOW_CTL_OFST))

/*
 * Register : Register 7 (VLAN Tag Register) - VLAN_Tag
 * 
 * The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN
 * frames. The MAC compares the 13th and 14th bytes of the receiving frame
 * (Length/Type) with 16'h8100, and the following two bytes are compared with the
 * VLAN tag. If a match occurs, the MAC sets the received VLAN bit in the receive
 * frame status. The legal length of the frame is increased from 1,518 bytes to
 * 1,522 bytes.
 * 
 * Because the VLAN Tag register is double-synchronized to the (G)MII clock domain,
 * then consecutive writes to these register should be performed only after at
 * least four clock cycles in the destination clock domain.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                           
 * :--------|:-------|:------|:---------------------------------------
 *  [15:0]  | RW     | 0x0   | VLAN Tag Identifier for Receive Frames
 *  [16]    | RW     | 0x0   | Enable 12-Bit VLAN Tag Comparison     
 *  [17]    | RW     | 0x0   | VLAN Tag Inverse Match Enable         
 *  [18]    | RW     | 0x0   | Enable S-VLAN                         
 *  [19]    | RW     | 0x0   | VLAN Tag Hash Table Match Enable      
 *  [31:20] | ???    | 0x0   | *UNDEFINED*                           
 * 
 */
/*
 * Field : VLAN Tag Identifier for Receive Frames - vl
 * 
 * This field contains the 802.1Q VLAN tag to identify the VLAN frames and is
 * compared to the 15th and 16th bytes of the frames being received for VLAN
 * frames. The following list describes the bits of this field:
 * 
 * * Bits [15:13]: User Priority
 * 
 * * Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI)
 * 
 * * Bits[11:0]: VLAN tag's VLAN Identifier (VID) field
 * 
 * When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison.
 * 
 * If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the
 * fifteenth and 16th bytes for VLAN tag comparison, and declares all frames with a
 * Type field value of 0x8100 or 0x88a8 as VLAN frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VL_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VL_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VL register field value. */
#define ALT_EMAC_GMAC_VLAN_TAG_VL_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VL register field value. */
#define ALT_EMAC_GMAC_VLAN_TAG_VL_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VL register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VL_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VL field value from a register. */
#define ALT_EMAC_GMAC_VLAN_TAG_VL_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_VLAN_TAG_VL register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VLAN_TAG_VL_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Enable 12-Bit VLAN Tag Comparison - etv
 * 
 * When this bit is set, a 12-bit VLAN identifier is used for comparing and
 * filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are
 * compared with the corresponding field in the received VLAN-tagged frame.
 * Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are
 * used for hash-based VLAN filtering.
 * 
 * When this bit is reset, all 16 bits of the 15th and 16th bytes of the received
 * VLAN frame are used for comparison and VLAN hash filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                    
 * :----------------------------------|:------|:--------------------------------
 *  ALT_EMAC_GMAC_VLAN_TAG_ETV_E_DISD | 0x0   | Disable 12-Bit VLAN Tag Compare
 *  ALT_EMAC_GMAC_VLAN_TAG_ETV_E_END  | 0x1   | Enable 12-Bit VLAN Tag Compare 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_VLAN_TAG_ETV
 * 
 * Disable 12-Bit VLAN Tag Compare
 */
#define ALT_EMAC_GMAC_VLAN_TAG_ETV_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_VLAN_TAG_ETV
 * 
 * Enable 12-Bit VLAN Tag Compare
 */
#define ALT_EMAC_GMAC_VLAN_TAG_ETV_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_ETV_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_ETV_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_ETV_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_ETV register field value. */
#define ALT_EMAC_GMAC_VLAN_TAG_ETV_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_ETV register field value. */
#define ALT_EMAC_GMAC_VLAN_TAG_ETV_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_ETV register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_ETV_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_VLAN_TAG_ETV field value from a register. */
#define ALT_EMAC_GMAC_VLAN_TAG_ETV_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_VLAN_TAG_ETV register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VLAN_TAG_ETV_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : VLAN Tag Inverse Match Enable - vtim
 * 
 * When set, this bit enables the VLAN Tag inverse matching. The frames that do not
 * have matching VLAN Tag are marked as matched.
 * 
 * When reset, this bit enables the VLAN Tag perfect matching. The frames with
 * matched VLAN Tag are marked as matched.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_MSB        17
/* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_SET_MSK    0x00020000
/* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_CLR_MSK    0xfffdffff
/* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VTIM register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VTIM field value from a register. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_EMAC_GMAC_VLAN_TAG_VTIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTIM_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Enable S-VLAN - esvl
 * 
 * When this bit is set, the MAC transmitter and receiver also consider the S-VLAN
 * (Type = 0x88A8) frames as valid VLAN tagged frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value. */
#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value. */
#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_ESVL register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_VLAN_TAG_ESVL field value from a register. */
#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_VLAN_TAG_ESVL register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VLAN_TAG_ESVL_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : VLAN Tag Hash Table Match Enable - vthm
 * 
 * When set, the most significant four bits of the VLAN tag's CRC are used to index
 * the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN
 * Hash Table register, corresponding to the index, indicates that the frame
 * matched the VLAN hash table.
 * 
 * When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used
 * for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used
 * for comparison.
 * 
 * When reset, the VLAN Hash Match operation is not performed.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_VLAN_TAG_VTHM register field. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_VLAN_TAG_VTHM field value from a register. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_VLAN_TAG_VTHM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VLAN_TAG_VTHM_SET(value) (((value) << 19) & 0x00080000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_VLAN_TAG.
 */
struct ALT_EMAC_GMAC_VLAN_TAG_s
{
    uint32_t  vl   : 16;  /* VLAN Tag Identifier for Receive Frames */
    uint32_t  etv  :  1;  /* Enable 12-Bit VLAN Tag Comparison */
    uint32_t  vtim :  1;  /* VLAN Tag Inverse Match Enable */
    uint32_t  esvl :  1;  /* Enable S-VLAN */
    uint32_t  vthm :  1;  /* VLAN Tag Hash Table Match Enable */
    uint32_t       : 12;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_VLAN_TAG. */
typedef volatile struct ALT_EMAC_GMAC_VLAN_TAG_s  ALT_EMAC_GMAC_VLAN_TAG_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_VLAN_TAG register from the beginning of the component. */
#define ALT_EMAC_GMAC_VLAN_TAG_OFST        0x1c
/* The address of the ALT_EMAC_GMAC_VLAN_TAG register. */
#define ALT_EMAC_GMAC_VLAN_TAG_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_TAG_OFST))

/*
 * Register : Register 8 (Version Register) - Version
 * 
 * The Version registers identifies the version of the EMAC. This register contains
 * two bytes: one specified by Synopsys to identify the core release number, and
 * the other specified by Altera.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description              
 * :--------|:-------|:------|:--------------------------
 *  [7:0]   | R      | 0x37  | ALT_EMAC_GMAC_VER_SNPSVER
 *  [15:8]  | R      | 0x10  | ALT_EMAC_GMAC_VER_USERVER
 *  [31:16] | ???    | 0x0   | *UNDEFINED*              
 * 
 */
/*
 * Field : snpsver
 * 
 * Synopsys-defined Version (3.7)
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
#define ALT_EMAC_GMAC_VER_SNPSVER_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
#define ALT_EMAC_GMAC_VER_SNPSVER_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
#define ALT_EMAC_GMAC_VER_SNPSVER_WIDTH      8
/* The mask used to set the ALT_EMAC_GMAC_VER_SNPSVER register field value. */
#define ALT_EMAC_GMAC_VER_SNPSVER_SET_MSK    0x000000ff
/* The mask used to clear the ALT_EMAC_GMAC_VER_SNPSVER register field value. */
#define ALT_EMAC_GMAC_VER_SNPSVER_CLR_MSK    0xffffff00
/* The reset value of the ALT_EMAC_GMAC_VER_SNPSVER register field. */
#define ALT_EMAC_GMAC_VER_SNPSVER_RESET      0x37
/* Extracts the ALT_EMAC_GMAC_VER_SNPSVER field value from a register. */
#define ALT_EMAC_GMAC_VER_SNPSVER_GET(value) (((value) & 0x000000ff) >> 0)
/* Produces a ALT_EMAC_GMAC_VER_SNPSVER register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VER_SNPSVER_SET(value) (((value) << 0) & 0x000000ff)

/*
 * Field : userver
 * 
 * Altera-defined Version
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VER_USERVER register field. */
#define ALT_EMAC_GMAC_VER_USERVER_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VER_USERVER register field. */
#define ALT_EMAC_GMAC_VER_USERVER_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_VER_USERVER register field. */
#define ALT_EMAC_GMAC_VER_USERVER_WIDTH      8
/* The mask used to set the ALT_EMAC_GMAC_VER_USERVER register field value. */
#define ALT_EMAC_GMAC_VER_USERVER_SET_MSK    0x0000ff00
/* The mask used to clear the ALT_EMAC_GMAC_VER_USERVER register field value. */
#define ALT_EMAC_GMAC_VER_USERVER_CLR_MSK    0xffff00ff
/* The reset value of the ALT_EMAC_GMAC_VER_USERVER register field. */
#define ALT_EMAC_GMAC_VER_USERVER_RESET      0x10
/* Extracts the ALT_EMAC_GMAC_VER_USERVER field value from a register. */
#define ALT_EMAC_GMAC_VER_USERVER_GET(value) (((value) & 0x0000ff00) >> 8)
/* Produces a ALT_EMAC_GMAC_VER_USERVER register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VER_USERVER_SET(value) (((value) << 8) & 0x0000ff00)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_VER.
 */
struct ALT_EMAC_GMAC_VER_s
{
    const uint32_t  snpsver :  8;  /* ALT_EMAC_GMAC_VER_SNPSVER */
    const uint32_t  userver :  8;  /* ALT_EMAC_GMAC_VER_USERVER */
    uint32_t                : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_VER. */
typedef volatile struct ALT_EMAC_GMAC_VER_s  ALT_EMAC_GMAC_VER_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_VER register from the beginning of the component. */
#define ALT_EMAC_GMAC_VER_OFST        0x20
/* The address of the ALT_EMAC_GMAC_VER register. */
#define ALT_EMAC_GMAC_VER_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VER_OFST))

/*
 * Register : Register 9 (Debug Register) - Debug
 * 
 * The Debug register gives the status of all main blocks of the transmit and
 * receive data-paths and the FIFOs. An all-zero status indicates that the MAC is
 * in idle state (and FIFOs are empty) and no activity is going on in the data-
 * paths.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                    
 * :--------|:-------|:------|:------------------------------------------------
 *  [0]     | R      | 0x0   | MAC GMII or MII Receive Protocol Engine Status 
 *  [2:1]   | R      | 0x0   | MAC Receive Frame Controller FIFO Status       
 *  [3]     | ???    | 0x0   | *UNDEFINED*                                    
 *  [4]     | R      | 0x0   | MTL Rx FIFO Write Controller Active Status     
 *  [6:5]   | R      | 0x0   | MTL Rx FIFO Read Controller State              
 *  [7]     | ???    | 0x0   | *UNDEFINED*                                    
 *  [9:8]   | R      | 0x0   | MTL Rx FIFO Fill-level Status                  
 *  [15:10] | ???    | 0x0   | *UNDEFINED*                                    
 *  [16]    | R      | 0x0   | MAC GMII or MII Transmit Protocol Engine Status
 *  [18:17] | R      | 0x0   | MAC Transmit Frame Controller Status           
 *  [19]    | R      | 0x0   | MAC transmitter in PAUSE                       
 *  [21:20] | R      | 0x0   | MTL Tx FIFO Read Controller Status             
 *  [22]    | R      | 0x0   | MTL Tx FIFO Write Controller Active Status     
 *  [23]    | ???    | 0x0   | *UNDEFINED*                                    
 *  [24]    | R      | 0x0   | MTL Tx FIFO Not Empty Status                   
 *  [25]    | R      | 0x0   | MTL TxStatus FIFO Full Status                  
 *  [31:26] | ???    | 0x0   | *UNDEFINED*                                    
 * 
 */
/*
 * Field : MAC GMII or MII Receive Protocol Engine Status - rpests
 * 
 * When high, this bit indicates that the MAC GMII or MII receive protocol engine
 * is actively receiving data and not in IDLE state.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description           
 * :---------------------------------|:------|:-----------------------
 *  ALT_EMAC_GMAC_DBG_RPESTS_E_INACT | 0x0   | Idle State            
 *  ALT_EMAC_GMAC_DBG_RPESTS_E_ACT   | 0x1   | Protocol Engine Active
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RPESTS
 * 
 * Idle State
 */
#define ALT_EMAC_GMAC_DBG_RPESTS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RPESTS
 * 
 * Protocol Engine Active
 */
#define ALT_EMAC_GMAC_DBG_RPESTS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
#define ALT_EMAC_GMAC_DBG_RPESTS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
#define ALT_EMAC_GMAC_DBG_RPESTS_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
#define ALT_EMAC_GMAC_DBG_RPESTS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_DBG_RPESTS register field value. */
#define ALT_EMAC_GMAC_DBG_RPESTS_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_DBG_RPESTS register field value. */
#define ALT_EMAC_GMAC_DBG_RPESTS_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_DBG_RPESTS register field. */
#define ALT_EMAC_GMAC_DBG_RPESTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_RPESTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_RPESTS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_DBG_RPESTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_RPESTS_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : MAC Receive Frame Controller FIFO Status - rfcfcsts
 * 
 * When high, this field indicates the active state of the small FIFO Read and
 * Write controllers of the MAC Receive Frame Controller Module.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                         
 * :-----------------------------------|:------|:-------------------------------------
 *  ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT | 0x0   | Disable Active State FIFO Read Write
 *  ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT   | 0x1   | Enable Active State FIFO Read Write 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RFCFCSTS
 * 
 * Disable Active State FIFO Read Write
 */
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RFCFCSTS
 * 
 * Enable Active State FIFO Read Write
 */
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_DBG_RFCFCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_SET_MSK    0x00000006
/* The mask used to clear the ALT_EMAC_GMAC_DBG_RFCFCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_CLR_MSK    0xfffffff9
/* The reset value of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_RFCFCSTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_GET(value) (((value) & 0x00000006) >> 1)
/* Produces a ALT_EMAC_GMAC_DBG_RFCFCSTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_SET(value) (((value) << 1) & 0x00000006)

/*
 * Field : MTL Rx FIFO Write Controller Active Status - rwcsts
 * 
 * When high, this bit indicates that the MTL Rx FIFO Write Controller is active
 * and is transferring a received frame to the FIFO.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                             
 * :---------------------------------|:------|:-----------------------------------------
 *  ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT | 0x0   | MTL Rx Fifo Controller Non-Active Status
 *  ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT   | 0x1   | MTL Rx Fifo Controller Active Status    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RWCSTS
 * 
 * MTL Rx Fifo Controller Non-Active Status
 */
#define ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RWCSTS
 * 
 * MTL Rx Fifo Controller Active Status
 */
#define ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RWCSTS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RWCSTS_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RWCSTS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_DBG_RWCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_RWCSTS_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_DBG_RWCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_RWCSTS_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_DBG_RWCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RWCSTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_RWCSTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_RWCSTS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_DBG_RWCSTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_RWCSTS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : MTL Rx FIFO Read Controller State - rrcsts
 * 
 * This field gives the state of the Rx FIFO read Controller
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                        
 * :-------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE      | 0x0   | IDLE State                         
 *  ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA | 0x1   | Reading Frame Data                 
 *  ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT | 0x2   | Reading Frame Status (or timestamp)
 *  ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS | 0x3   | Flushing Frame Data and Status     
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
 * 
 * IDLE State
 */
#define ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE         0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
 * 
 * Reading Frame Data
 */
#define ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA    0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
 * 
 * Reading Frame Status (or timestamp)
 */
#define ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT    0x2
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
 * 
 * Flushing Frame Data and Status
 */
#define ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS    0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RRCSTS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RRCSTS_MSB        6
/* The width in bits of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RRCSTS_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_DBG_RRCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_RRCSTS_SET_MSK    0x00000060
/* The mask used to clear the ALT_EMAC_GMAC_DBG_RRCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_RRCSTS_CLR_MSK    0xffffff9f
/* The reset value of the ALT_EMAC_GMAC_DBG_RRCSTS register field. */
#define ALT_EMAC_GMAC_DBG_RRCSTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_RRCSTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_RRCSTS_GET(value) (((value) & 0x00000060) >> 5)
/* Produces a ALT_EMAC_GMAC_DBG_RRCSTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_RRCSTS_SET(value) (((value) << 5) & 0x00000060)

/*
 * Field : MTL Rx FIFO Fill-level Status - rxfsts
 * 
 * This field gives the status of the fill-level of the Rx FIFO.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                     
 * :----------------------------------------|:------|:-------------------------------------------------
 *  ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY  | 0x0   | Rx FIFO Empty                                   
 *  ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL | 0x1   | Rx FIFO fill-level below flow-control deactivate
 * :                                        |       | thres.                                          
 *  ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL  | 0x2   | Rx FIFO fill-level above flow-control activate  
 * :                                        |       | thres.                                          
 *  ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL   | 0x3   | Rx FIFO Full                                    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
 * 
 * Rx FIFO Empty
 */
#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
 * 
 * Rx FIFO fill-level below flow-control deactivate thres.
 */
#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL 0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
 * 
 * Rx FIFO fill-level above flow-control activate thres.
 */
#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL  0x2
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
 * 
 * Rx FIFO Full
 */
#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL   0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
#define ALT_EMAC_GMAC_DBG_RXFSTS_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
#define ALT_EMAC_GMAC_DBG_RXFSTS_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
#define ALT_EMAC_GMAC_DBG_RXFSTS_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_DBG_RXFSTS register field value. */
#define ALT_EMAC_GMAC_DBG_RXFSTS_SET_MSK    0x00000300
/* The mask used to clear the ALT_EMAC_GMAC_DBG_RXFSTS register field value. */
#define ALT_EMAC_GMAC_DBG_RXFSTS_CLR_MSK    0xfffffcff
/* The reset value of the ALT_EMAC_GMAC_DBG_RXFSTS register field. */
#define ALT_EMAC_GMAC_DBG_RXFSTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_RXFSTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_RXFSTS_GET(value) (((value) & 0x00000300) >> 8)
/* Produces a ALT_EMAC_GMAC_DBG_RXFSTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_RXFSTS_SET(value) (((value) << 8) & 0x00000300)

/*
 * Field : MAC GMII or MII Transmit Protocol Engine Status - tpests
 * 
 * When high, this bit indicates that the MAC GMII or MII transmit protocol engine
 * is actively transmitting data and is not in the IDLE state.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description               
 * :--------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_DBG_TPESTS_E_DISD | 0x0   | Idle State                
 *  ALT_EMAC_GMAC_DBG_TPESTS_E_END  | 0x1   | Actively Transmitting Data
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TPESTS
 * 
 * Idle State
 */
#define ALT_EMAC_GMAC_DBG_TPESTS_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TPESTS
 * 
 * Actively Transmitting Data
 */
#define ALT_EMAC_GMAC_DBG_TPESTS_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
#define ALT_EMAC_GMAC_DBG_TPESTS_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
#define ALT_EMAC_GMAC_DBG_TPESTS_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
#define ALT_EMAC_GMAC_DBG_TPESTS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_DBG_TPESTS register field value. */
#define ALT_EMAC_GMAC_DBG_TPESTS_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_DBG_TPESTS register field value. */
#define ALT_EMAC_GMAC_DBG_TPESTS_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_DBG_TPESTS register field. */
#define ALT_EMAC_GMAC_DBG_TPESTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_TPESTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_TPESTS_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_DBG_TPESTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_TPESTS_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : MAC Transmit Frame Controller Status - tfcsts
 * 
 * This field indicates the state of the MAC Transmit Frame Controller block
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description               
 * :-----------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE    | 0x0   | Idle State                
 *  ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG | 0x1   | Waiting Prev. State or IFG
 *  ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE | 0x2   | Generating Tx Pause       
 *  ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM | 0x3   | Tx Input Frame            
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
 * 
 * Idle State
 */
#define ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE     0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
 * 
 * Waiting Prev. State or IFG
 */
#define ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG  0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
 * 
 * Generating Tx Pause
 */
#define ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE  0x2
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
 * 
 * Tx Input Frame
 */
#define ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM  0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TFCSTS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TFCSTS_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TFCSTS_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_DBG_TFCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_TFCSTS_SET_MSK    0x00060000
/* The mask used to clear the ALT_EMAC_GMAC_DBG_TFCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_TFCSTS_CLR_MSK    0xfff9ffff
/* The reset value of the ALT_EMAC_GMAC_DBG_TFCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TFCSTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_TFCSTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_TFCSTS_GET(value) (((value) & 0x00060000) >> 17)
/* Produces a ALT_EMAC_GMAC_DBG_TFCSTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_TFCSTS_SET(value) (((value) << 17) & 0x00060000)

/*
 * Field : MAC transmitter in PAUSE - txpaused
 * 
 * When high, this bit indicates that the MAC transmitter is in the PAUSE condition
 * (in the full-duplex only mode) and hence does not schedule any frame for
 * transmission.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                    
 * :---------------------------------|:------|:--------------------------------
 *  ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS | 0x0   | MAC Transmitter Pause Disabled 
 *  ALT_EMAC_GMAC_DBG_TXPAUSED_E_END | 0x1   | MAC Transmitter Pause Condition
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXPAUSED
 * 
 * MAC Transmitter Pause Disabled
 */
#define ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXPAUSED
 * 
 * MAC Transmitter Pause Condition
 */
#define ALT_EMAC_GMAC_DBG_TXPAUSED_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
#define ALT_EMAC_GMAC_DBG_TXPAUSED_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
#define ALT_EMAC_GMAC_DBG_TXPAUSED_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
#define ALT_EMAC_GMAC_DBG_TXPAUSED_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_DBG_TXPAUSED register field value. */
#define ALT_EMAC_GMAC_DBG_TXPAUSED_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_DBG_TXPAUSED register field value. */
#define ALT_EMAC_GMAC_DBG_TXPAUSED_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_DBG_TXPAUSED register field. */
#define ALT_EMAC_GMAC_DBG_TXPAUSED_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_TXPAUSED field value from a register. */
#define ALT_EMAC_GMAC_DBG_TXPAUSED_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_DBG_TXPAUSED register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_TXPAUSED_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : MTL Tx FIFO Read Controller Status - trcsts
 * 
 * This field indicates the state of the Tx FIFO Read Controller
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                     
 * :--------------------------------------|:------|:-------------------------------------------------
 *  ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE       | 0x0   | Idle State                                      
 *  ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE    | 0x1   | Read State (transferring data to the MAC        
 * :                                      |       | transmitter)                                    
 *  ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT | 0x2   | Waiting for TxStatus from the MAC transmitter   
 *  ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT   | 0x3   | Writing the received TxStatus or flushing the Tx
 * :                                      |       | FIFO                                            
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
 * 
 * Idle State
 */
#define ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE         0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
 * 
 * Read State (transferring data to the MAC transmitter)
 */
#define ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE      0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
 * 
 * Waiting for TxStatus from the MAC transmitter
 */
#define ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT   0x2
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
 * 
 * Writing the received TxStatus or flushing the Tx FIFO
 */
#define ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT     0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TRCSTS_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TRCSTS_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TRCSTS_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_DBG_TRCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_TRCSTS_SET_MSK    0x00300000
/* The mask used to clear the ALT_EMAC_GMAC_DBG_TRCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_TRCSTS_CLR_MSK    0xffcfffff
/* The reset value of the ALT_EMAC_GMAC_DBG_TRCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TRCSTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_TRCSTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_TRCSTS_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_EMAC_GMAC_DBG_TRCSTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_TRCSTS_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : MTL Tx FIFO Write Controller Active Status - twcsts
 * 
 * When high, this bit indicates that the MTL Tx FIFO Write Controller is active
 * and transferring data to the Tx FIFO.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description                
 * :---------------------------------|:------|:----------------------------
 *  ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT | 0x0   | Tx FIFO Write Ctrl Inactive
 *  ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT   | 0x1   | Tx FIFO Write Ctrl Active  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TWCSTS
 * 
 * Tx FIFO Write Ctrl Inactive
 */
#define ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TWCSTS
 * 
 * Tx FIFO Write Ctrl Active
 */
#define ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TWCSTS_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TWCSTS_MSB        22
/* The width in bits of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TWCSTS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_DBG_TWCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_TWCSTS_SET_MSK    0x00400000
/* The mask used to clear the ALT_EMAC_GMAC_DBG_TWCSTS register field value. */
#define ALT_EMAC_GMAC_DBG_TWCSTS_CLR_MSK    0xffbfffff
/* The reset value of the ALT_EMAC_GMAC_DBG_TWCSTS register field. */
#define ALT_EMAC_GMAC_DBG_TWCSTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_TWCSTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_TWCSTS_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_EMAC_GMAC_DBG_TWCSTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_TWCSTS_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : MTL Tx FIFO Not Empty Status - txfsts
 * 
 * When high, this bit indicates that the MTL Tx FIFO is not empty and some data is
 * left for transmission.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                             | Value | Description          
 * :---------------------------------|:------|:----------------------
 *  ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT | 0x0   | MTL Tx FIFO Empty    
 *  ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT   | 0x1   | MTL Tx FIFO Not Empty
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXFSTS
 * 
 * MTL Tx FIFO Empty
 */
#define ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXFSTS
 * 
 * MTL Tx FIFO Not Empty
 */
#define ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
#define ALT_EMAC_GMAC_DBG_TXFSTS_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
#define ALT_EMAC_GMAC_DBG_TXFSTS_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
#define ALT_EMAC_GMAC_DBG_TXFSTS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_DBG_TXFSTS register field value. */
#define ALT_EMAC_GMAC_DBG_TXFSTS_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_DBG_TXFSTS register field value. */
#define ALT_EMAC_GMAC_DBG_TXFSTS_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_DBG_TXFSTS register field. */
#define ALT_EMAC_GMAC_DBG_TXFSTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_TXFSTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_TXFSTS_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_DBG_TXFSTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_TXFSTS_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : MTL TxStatus FIFO Full Status - txstsfsts
 * 
 * When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the
 * MTL cannot accept any more frames for transmission.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                      
 * :------------------------------------|:------|:----------------------------------
 *  ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT | 0x0   | MTL TxStatus FIFO Not Full Status
 *  ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT   | 0x1   | MTL TxStatus FIFO Full Status    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXSTSFSTS
 * 
 * MTL TxStatus FIFO Not Full Status
 */
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_DBG_TXSTSFSTS
 * 
 * MTL TxStatus FIFO Full Status
 */
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value. */
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value. */
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field. */
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_DBG_TXSTSFSTS field value from a register. */
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET(value) (((value) << 25) & 0x02000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_DBG.
 */
struct ALT_EMAC_GMAC_DBG_s
{
    const uint32_t  rpests    :  1;  /* MAC GMII or MII Receive Protocol Engine Status */
    const uint32_t  rfcfcsts  :  2;  /* MAC Receive Frame Controller FIFO Status */
    uint32_t                  :  1;  /* *UNDEFINED* */
    const uint32_t  rwcsts    :  1;  /* MTL Rx FIFO Write Controller Active Status */
    const uint32_t  rrcsts    :  2;  /* MTL Rx FIFO Read Controller State */
    uint32_t                  :  1;  /* *UNDEFINED* */
    const uint32_t  rxfsts    :  2;  /* MTL Rx FIFO Fill-level Status */
    uint32_t                  :  6;  /* *UNDEFINED* */
    const uint32_t  tpests    :  1;  /* MAC GMII or MII Transmit Protocol Engine Status */
    const uint32_t  tfcsts    :  2;  /* MAC Transmit Frame Controller Status */
    const uint32_t  txpaused  :  1;  /* MAC transmitter in PAUSE */
    const uint32_t  trcsts    :  2;  /* MTL Tx FIFO Read Controller Status */
    const uint32_t  twcsts    :  1;  /* MTL Tx FIFO Write Controller Active Status */
    uint32_t                  :  1;  /* *UNDEFINED* */
    const uint32_t  txfsts    :  1;  /* MTL Tx FIFO Not Empty Status */
    const uint32_t  txstsfsts :  1;  /* MTL TxStatus FIFO Full Status */
    uint32_t                  :  6;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_DBG. */
typedef volatile struct ALT_EMAC_GMAC_DBG_s  ALT_EMAC_GMAC_DBG_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_DBG register from the beginning of the component. */
#define ALT_EMAC_GMAC_DBG_OFST        0x24
/* The address of the ALT_EMAC_GMAC_DBG register. */
#define ALT_EMAC_GMAC_DBG_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_DBG_OFST))

/*
 * Register : Register 12 (LPI Control and Status Register) - LPI_Control_Status
 * 
 * The LPI Control and Status Register controls the LPI functions and provides the
 * LPI interrupt status. The status bits are cleared when this register is read.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description           
 * :--------|:-------|:------|:-----------------------
 *  [0]     | R      | 0x0   | Transmit LPI Entry    
 *  [1]     | R      | 0x0   | Transmit LPI Exit     
 *  [2]     | R      | 0x0   | Receive LPI Entry     
 *  [3]     | R      | 0x0   | Receive LPI Exit      
 *  [7:4]   | ???    | 0x0   | *UNDEFINED*           
 *  [8]     | R      | 0x0   | Transmit LPI State    
 *  [9]     | R      | 0x0   | Receive LPI State     
 *  [15:10] | ???    | 0x0   | *UNDEFINED*           
 *  [16]    | RW     | 0x0   | LPI Enable            
 *  [17]    | RW     | 0x0   | PHY Link Status       
 *  [18]    | RW     | 0x0   | PHY Link Status Enable
 *  [19]    | RW     | 0x0   | LPI TX Automate       
 *  [31:20] | ???    | 0x0   | *UNDEFINED*           
 * 
 */
/*
 * Field : Transmit LPI Entry - tlpien
 * 
 * When set, this bit indicates that the MAC Transmitter has entered the LPI state
 * because of the setting of the LPIEN bit. This bit is cleared by a read into this
 * register.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                      
 * :------------------------------------------|:------|:----------------------------------
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT | 0x0   | MAC Transmitter Not in LPI State 
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT   | 0x1   | MAC Transmitter Entered LPI State
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN
 * 
 * MAC Transmitter Not in LPI State
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN
 * 
 * MAC Transmitter Entered LPI State
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN field value from a register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Transmit LPI Exit - tlpiex
 * 
 * When set, this bit indicates that the MAC transmitter has exited the LPI state
 * after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This
 * bit is cleared by a read into this register.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                     
 * :------------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT | 0x0   | MAC Transmitter Non LPI State   
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT   | 0x1   | MAC Transmitter Exited LPI State
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX
 * 
 * MAC Transmitter Non LPI State
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX
 * 
 * MAC Transmitter Exited LPI State
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX field value from a register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Receive LPI Entry - rlpien
 * 
 * When set, this bit indicates that the MAC Receiver has received an LPI pattern
 * and entered the LPI state. This bit is cleared by a read into this register.
 * 
 * Note:
 * 
 * This bit may not get set if the MAC stops receiving the LPI pattern for a very
 * short duration, such as, less than 3 clock cycles of l3_sp_clk.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                  
 * :------------------------------------------|:------|:------------------------------
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT | 0x0   | MAC Receiver Not In LPI State
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT   | 0x1   | MAC Receiver In LPI State    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN
 * 
 * MAC Receiver Not In LPI State
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN
 * 
 * MAC Receiver In LPI State
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN field value from a register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Receive LPI Exit - rlpiex
 * 
 * When set, this bit indicates that the MAC Receiver has stopped receiving the LPI
 * pattern on the GMII or MII interface, exited the LPI state, and resumed the
 * normal reception. This bit is cleared by a read into this register.
 * 
 * Note:
 * 
 * This bit may not get set if the MAC stops receiving the LPI pattern for a very
 * short duration, such as, less than 3 clock cycles of l3_sp_clk.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                          
 * :------------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT | 0x0   | MAC RX receiving LPI Patterns        
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT   | 0x1   | MAC RX Stopped receiving LPI Patterns
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX
 * 
 * MAC RX receiving LPI Patterns
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX
 * 
 * MAC RX Stopped receiving LPI Patterns
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX field value from a register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Transmit LPI State - tlpist
 * 
 * When set, this bit indicates that the MAC is transmitting the LPI pattern on the
 * GMII or MII interface.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                 
 * :------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT | 0x0   | MAC Transmitting LPI Pattern
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT   | 0x1   | MAC Transmitting LPI Pattern
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST
 * 
 * MAC Transmitting LPI Pattern
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST
 * 
 * MAC Transmitting LPI Pattern
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST field value from a register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Receive LPI State - rlpist
 * 
 * When set, this bit indicates that the MAC is receiving the LPI pattern on the
 * GMII or MII interface.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                     
 * :------------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT | 0x0   | MAC is not receiving LPI Pattern
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT   | 0x1   | MAC receiving LPI Pattern       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST
 * 
 * MAC is not receiving LPI Pattern
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST
 * 
 * MAC receiving LPI Pattern
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST field value from a register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : LPI Enable - lpien
 * 
 * When set, this bit instructs the MAC Transmitter to enter the LPI state. When
 * reset, this bit instructs the MAC to exit the LPI state and resume normal
 * transmission.
 * 
 * This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state
 * because of the arrival of a new packet for transmission.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                     
 * :----------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD | 0x0   | MAC Transmitter exit LPI State  
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END  | 0x1   | MAC Transmitter enters LPI State
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN
 * 
 * MAC Transmitter exit LPI State
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN
 * 
 * MAC Transmitter enters LPI State
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN field value from a register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : PHY Link Status - pls
 * 
 * This bit indicates the link status of the PHY. The MAC Transmitter asserts the
 * LPI pattern only when the link status is up (okay) at least for the time
 * indicated by the LPI LS TIMER.
 * 
 * When set, the link is considered to be okay (up) and when reset, the link is
 * considered to be down.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description   
 * :--------------------------------------|:------|:---------------
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD | 0x0   | Link Down     
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END  | 0x1   | Link Up (okay)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS
 * 
 * Link Down
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS
 * 
 * Link Up (okay)
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_MSB        17
/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET_MSK    0x00020000
/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS field value from a register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : PHY Link Status Enable - plsen
 * 
 * This bit enables the link status received on the RGMII receive paths to be used
 * for activating the LPI LS TIMER.
 * 
 * When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII
 * Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared,
 * the MAC ignores the link-status bits of Register 54 and takes only the PLS bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD | 0x0   | MAC Ignores Link Status Bits
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END  | 0x1   | MAC Uses Link Status Bits   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN
 * 
 * MAC Ignores Link Status Bits
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN
 * 
 * MAC Uses Link Status Bits
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN field value from a register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : LPI TX Automate - lpitxa
 * 
 * This bit controls the behavior of the MAC when it is entering or coming out of
 * the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE
 * configuration in which the Tx clock gating is done during the LPI mode.
 * 
 * If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only
 * after all outstanding frames (in the core) and pending frames (in the
 * application interface) have been transmitted. The MAC comes out of the LPI mode
 * when the application sends any frame for transmission or the application issues
 * a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit
 * when it exits the LPI state. If TX FIFO Flush is set, in Bit 20 of Register 6
 * (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the
 * LPI mode.
 * 
 * When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it
 * is entering or coming out of the LPI mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description             
 * :-----------------------------------------|:------|:-------------------------
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD | 0x0   | LPI TX Automate Disabled
 *  ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END  | 0x1   | LPI TX Automate Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA
 * 
 * LPI TX Automate Disabled
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA
 * 
 * LPI TX Automate Enabled
 */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA field value from a register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET(value) (((value) << 19) & 0x00080000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT.
 */
struct ALT_EMAC_GMAC_LPI_CTL_STAT_s
{
    const uint32_t  tlpien :  1;  /* Transmit LPI Entry */
    const uint32_t  tlpiex :  1;  /* Transmit LPI Exit */
    const uint32_t  rlpien :  1;  /* Receive LPI Entry */
    const uint32_t  rlpiex :  1;  /* Receive LPI Exit */
    uint32_t               :  4;  /* *UNDEFINED* */
    const uint32_t  tlpist :  1;  /* Transmit LPI State */
    const uint32_t  rlpist :  1;  /* Receive LPI State */
    uint32_t               :  6;  /* *UNDEFINED* */
    uint32_t        lpien  :  1;  /* LPI Enable */
    uint32_t        pls    :  1;  /* PHY Link Status */
    uint32_t        plsen  :  1;  /* PHY Link Status Enable */
    uint32_t        lpitxa :  1;  /* LPI TX Automate */
    uint32_t               : 12;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT. */
typedef volatile struct ALT_EMAC_GMAC_LPI_CTL_STAT_s  ALT_EMAC_GMAC_LPI_CTL_STAT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LPI_CTL_STAT register from the beginning of the component. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_OFST        0x30
/* The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register. */
#define ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_CTL_STAT_OFST))

/*
 * Register : Register 13 (LPI Timers Control Register) - LPI_Timers_Control
 * 
 * The LPI Timers Control register controls the timeout values in the LPI states.
 * It specifies the time for which the MAC transmits the LPI pattern and also the
 * time for which the MAC waits before resuming the normal transmission.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description 
 * :--------|:-------|:------|:-------------
 *  [15:0]  | RW     | 0x0   | LPI TW Timer
 *  [25:16] | RW     | 0x3e8 | LPI LS Timer
 *  [31:26] | ???    | 0x0   | *UNDEFINED* 
 * 
 */
/*
 * Field : LPI TW Timer - twt
 * 
 * This field specifies the minimum time (in microseconds) for which the MAC waits
 * after it stops transmitting the LPI pattern to the PHY and before it resumes the
 * normal transmission. The TLPIEX status bit is set after the expiry of this
 * timer.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT field value from a register. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : LPI LS Timer - lst
 * 
 * This field specifies the minimum time (in milliseconds) for which the link
 * status from the PHY should be up (OKAY) before the LPI pattern can be
 * transmitted to the PHY. The MAC does not transmit the LPI pattern even when the
 * LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count.
 * The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE
 * standard.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_WIDTH      10
/* The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET_MSK    0x03ff0000
/* The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_CLR_MSK    0xfc00ffff
/* The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_RESET      0x3e8
/* Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST field value from a register. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_GET(value) (((value) & 0x03ff0000) >> 16)
/* Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET(value) (((value) << 16) & 0x03ff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LPI_TMRS_CTL.
 */
struct ALT_EMAC_GMAC_LPI_TMRS_CTL_s
{
    uint32_t  twt : 16;  /* LPI TW Timer */
    uint32_t  lst : 10;  /* LPI LS Timer */
    uint32_t      :  6;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LPI_TMRS_CTL. */
typedef volatile struct ALT_EMAC_GMAC_LPI_TMRS_CTL_s  ALT_EMAC_GMAC_LPI_TMRS_CTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LPI_TMRS_CTL register from the beginning of the component. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST        0x34
/* The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register. */
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST))

/*
 * Register : Register 14 (Interrupt Register) - Interrupt_Status
 * 
 * The Interrupt Status register identifies the events in the MAC that can generate
 * interrupt. All interrupt events are generated only when the corresponding
 * optional feature is enabled.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                  
 * :--------|:-------|:------|:----------------------------------------------
 *  [0]     | R      | 0x0   | RGMII or SMII Interrupt Status               
 *  [1]     | R      | 0x0   | PCS Link Status Changed                      
 *  [2]     | R      | 0x0   | PCS Auto-Negotiation Complete                
 *  [3]     | ???    | 0x0   | *UNDEFINED*                                  
 *  [4]     | R      | 0x0   | MMC Interrupt Status                         
 *  [5]     | R      | 0x0   | MMC Receive Interrupt Status                 
 *  [6]     | R      | 0x0   | MMC Transmit Interrupt Status                
 *  [7]     | R      | 0x0   | MMC Receive Checksum Offload Interrupt Status
 *  [8]     | ???    | 0x0   | *UNDEFINED*                                  
 *  [9]     | R      | 0x0   | Timestamp Interrupt Status                   
 *  [10]    | R      | 0x0   | LPI Interrupt Status                         
 *  [31:11] | ???    | 0x0   | *UNDEFINED*                                  
 * 
 */
/*
 * Field : RGMII or SMII Interrupt Status - rgsmiiis
 * 
 * This bit is set because of any change in value of the Link Status of RGMII or
 * SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Status Register)). This
 * bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Status
 * Register.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description   
 * :----------------------------------------|:------|:---------------
 *  ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT | 0x0   | Link No Change
 *  ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT   | 0x1   | Link Change   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_RGSMIIIS
 * 
 * Link No Change
 */
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_RGSMIIIS
 * 
 * Link Change
 */
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS field value from a register. */
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : PCS Link Status Changed - pcslchgis
 * 
 * This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII
 * PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared
 * when you perform a read operation on the AN Status register.
 * 
 * This bit is valid only when you select the SGMII PHY interface during operation.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS field value from a register. */
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : PCS Auto-Negotiation Complete - pcsancis
 * 
 * This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or
 * SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is
 * cleared when you perform a read operation to the AN Status register.
 * 
 * This bit is valid only when you select the SGMII PHY interface during operation.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_STAT_PCSANCIS field value from a register. */
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : MMC Interrupt Status - mmcis
 * 
 * This bit is set high when any of the Bits [7:5] is set high and cleared only
 * when all of these bits are low.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                  
 * :-------------------------------------|:------|:------------------------------
 *  ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT | 0x0   | MMC Interrupt Status Disabled
 *  ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT   | 0x1   | MMC Interrupt Status Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCIS
 * 
 * MMC Interrupt Status Disabled
 */
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCIS
 * 
 * MMC Interrupt Status Enabled
 */
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCIS field value from a register. */
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_INT_STAT_MMCIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : MMC Receive Interrupt Status - mmcrxis
 * 
 * This bit is set high when an interrupt is generated in the MMC Receive Interrupt
 * Register. This bit is cleared when all the bits in this interrupt register are
 * cleared.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                          
 * :--------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD | 0x0   | MMC Receive Interrupt Status Disabled
 *  ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END  | 0x1   | MMC Receive Interrupt Status Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIS
 * 
 * MMC Receive Interrupt Status Disabled
 */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIS
 * 
 * MMC Receive Interrupt Status Enabled
 */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCRXIS field value from a register. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : MMC Transmit Interrupt Status - mmctxis
 * 
 * This bit is set high when an interrupt is generated in the MMC Transmit
 * Interrupt Register. This bit is cleared when all the bits in this interrupt
 * register are cleared.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                           
 * :---------------------------------------|:------|:---------------------------------------
 *  ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT | 0x0   | MMC Transmit Interrupt Status Disabled
 *  ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT   | 0x1   | MMC Transmit Interrupt Status Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCTXIS
 * 
 * MMC Transmit Interrupt Status Disabled
 */
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCTXIS
 * 
 * MMC Transmit Interrupt Status Enabled
 */
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_MSB        6
/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCTXIS field value from a register. */
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : MMC Receive Checksum Offload Interrupt Status - mmcrxipis
 * 
 * This bit is set high when an interrupt is generated in the MMC Receive Checksum
 * Offload Interrupt Register. This bit is cleared when all the bits in this
 * interrupt register are cleared.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                                  
 * :-----------------------------------------|:------|:----------------------------------------------
 *  ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT | 0x0   | MMC Receive Checksum Offload Interrupt Status
 * :                                         |       | Disabled                                     
 *  ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT   | 0x1   | MMC Receive Checksum Offload Interrupt Status
 * :                                         |       | Enabled                                      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS
 * 
 * MMC Receive Checksum Offload Interrupt Status Disabled
 */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS
 * 
 * MMC Receive Checksum Offload Interrupt Status Enabled
 */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS field value from a register. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Timestamp Interrupt Status - tsis
 * 
 * This bit is set when any of the following conditions is true:
 * 
 * * The system time value equals or exceeds the value specified in the Target Time
 *   High and Low registers.
 * 
 * * There is an overflow in the seconds register.
 * 
 * * The Auxiliary snapshot trigger is asserted.
 * 
 * This bit is cleared on reading Bit 0 of the Register 458 (Timestamp Status
 * Register).
 * 
 * When set, this bit indicates that the system time value is equal to or exceeds
 * the value specified in the Target Time registers. In this mode, this bit is
 * cleared after the completion of the read of this bit. In all other modes, this
 * bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                        
 * :------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT | 0x0   | Timestamp Interrupt Status Disabled
 *  ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT   | 0x1   | Timestamp Interrupt Status Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_TSIS
 * 
 * Timestamp Interrupt Status Disabled
 */
#define ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_TSIS
 * 
 * Timestamp Interrupt Status Enabled
 */
#define ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_TSIS_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_TSIS_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_TSIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_TSIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_TSIS_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_TSIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_TSIS_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_INT_STAT_TSIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_TSIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_STAT_TSIS field value from a register. */
#define ALT_EMAC_GMAC_INT_STAT_TSIS_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_INT_STAT_TSIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_STAT_TSIS_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : LPI Interrupt Status - lpiis
 * 
 * This bit is set for any LPI state entry or exit in the MAC Transmitter or
 * Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and
 * Status Register). In all other modes, this bit is reserved.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                  
 * :-------------------------------------|:------|:------------------------------
 *  ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT | 0x0   | LPI Interrupt Status Disabled
 *  ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT   | 0x1   | LPI Interrupt Status Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_LPIIS
 * 
 * LPI Interrupt Status Disabled
 */
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_LPIIS
 * 
 * LPI Interrupt Status Enabled
 */
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_STAT_LPIIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_INT_STAT_LPIIS register field value. */
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field. */
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_STAT_LPIIS field value from a register. */
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_INT_STAT_LPIIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET(value) (((value) << 10) & 0x00000400)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_INT_STAT.
 */
struct ALT_EMAC_GMAC_INT_STAT_s
{
    const uint32_t  rgsmiiis  :  1;  /* RGMII or SMII Interrupt Status */
    const uint32_t  pcslchgis :  1;  /* PCS Link Status Changed */
    const uint32_t  pcsancis  :  1;  /* PCS Auto-Negotiation Complete */
    uint32_t                  :  1;  /* *UNDEFINED* */
    const uint32_t  mmcis     :  1;  /* MMC Interrupt Status */
    const uint32_t  mmcrxis   :  1;  /* MMC Receive Interrupt Status */
    const uint32_t  mmctxis   :  1;  /* MMC Transmit Interrupt Status */
    const uint32_t  mmcrxipis :  1;  /* MMC Receive Checksum Offload Interrupt Status */
    uint32_t                  :  1;  /* *UNDEFINED* */
    const uint32_t  tsis      :  1;  /* Timestamp Interrupt Status */
    const uint32_t  lpiis     :  1;  /* LPI Interrupt Status */
    uint32_t                  : 21;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_INT_STAT. */
typedef volatile struct ALT_EMAC_GMAC_INT_STAT_s  ALT_EMAC_GMAC_INT_STAT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_INT_STAT register from the beginning of the component. */
#define ALT_EMAC_GMAC_INT_STAT_OFST        0x38
/* The address of the ALT_EMAC_GMAC_INT_STAT register. */
#define ALT_EMAC_GMAC_INT_STAT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_STAT_OFST))

/*
 * Register : Register 15 (Interrupt Mask Register) - Interrupt_Mask
 * 
 * The Interrupt Mask Register bits enable you to mask the interrupt signal because
 * of the corresponding event in the Interrupt Status Register. The interrupt
 * signal is sbd_intr_o.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                     
 * :--------|:-------|:------|:---------------------------------
 *  [0]     | RW     | 0x0   | RGMII or SMII Interrupt Mask    
 *  [1]     | R      | 0x0   | PCS Link Status Interrupt Mask  
 *  [2]     | R      | 0x0   | PCS AN Completion Interrupt Mask
 *  [8:3]   | ???    | 0x0   | *UNDEFINED*                     
 *  [9]     | RW     | 0x0   | Timestamp Interrupt Mask        
 *  [10]    | RW     | 0x0   | LPI Interrupt Mask              
 *  [31:11] | ???    | 0x0   | *UNDEFINED*                     
 * 
 */
/*
 * Field : RGMII or SMII Interrupt Mask - rgsmiiim
 * 
 * When set, this bit disables the assertion of the interrupt signal because of the
 * setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt
 * Status Register).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                         
 * :--------------------------------------|:------|:-------------------------------------
 *  ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD | 0x0   | RGMII or SMII Interrupt Mask Disable
 *  ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END  | 0x1   | RGMII or SMII Interrupt Mask Enable 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM
 * 
 * RGMII or SMII Interrupt Mask Disable
 */
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM
 * 
 * RGMII or SMII Interrupt Mask Enable
 */
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value. */
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value. */
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM field value from a register. */
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : PCS Link Status Interrupt Mask - pcslchgim
 * 
 * When set, this bit disables the assertion of the interrupt signal because of the
 * setting of the PCS Link-status changed bit in Register 14 (Interrupt Status
 * Register).
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value. */
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value. */
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM field value from a register. */
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : PCS AN Completion Interrupt Mask - pcsancim
 * 
 * When set, this bit disables the assertion of the interrupt signal because of the
 * setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status
 * Register).
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value. */
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value. */
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_MSK_PCSANCIM field value from a register. */
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timestamp Interrupt Mask - tsim
 * 
 * When set, this bit disables the assertion of the interrupt signal because of the
 * setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status
 * Register).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                      
 * :----------------------------------|:------|:----------------------------------
 *  ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD | 0x0   | Timestamp Interrupt Mask Disabled
 *  ALT_EMAC_GMAC_INT_MSK_TSIM_E_END  | 0x1   | Timestamp Interrupt Mask Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM
 * 
 * Timestamp Interrupt Mask Disabled
 */
#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM
 * 
 * Timestamp Interrupt Mask Enabled
 */
#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_TSIM_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_TSIM_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_TSIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_MSK_TSIM register field value. */
#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_TSIM register field value. */
#define ALT_EMAC_GMAC_INT_MSK_TSIM_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_INT_MSK_TSIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_TSIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_MSK_TSIM field value from a register. */
#define ALT_EMAC_GMAC_INT_MSK_TSIM_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_INT_MSK_TSIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : LPI Interrupt Mask - lpiim
 * 
 * When set, this bit disables the assertion of the interrupt signal because of the
 * setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status
 * Register).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD | 0x0   | LPI Interrupt Mask Disabled
 *  ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END  | 0x1   | LPI Interrupt Mask Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM
 * 
 * LPI Interrupt Mask Disabled
 */
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM
 * 
 * LPI Interrupt Mask Enabled
 */
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value. */
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value. */
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field. */
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_INT_MSK_LPIIM field value from a register. */
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_INT_MSK_LPIIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET(value) (((value) << 10) & 0x00000400)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_INT_MSK.
 */
struct ALT_EMAC_GMAC_INT_MSK_s
{
    uint32_t        rgsmiiim  :  1;  /* RGMII or SMII Interrupt Mask */
    const uint32_t  pcslchgim :  1;  /* PCS Link Status Interrupt Mask */
    const uint32_t  pcsancim  :  1;  /* PCS AN Completion Interrupt Mask */
    uint32_t                  :  6;  /* *UNDEFINED* */
    uint32_t        tsim      :  1;  /* Timestamp Interrupt Mask */
    uint32_t        lpiim     :  1;  /* LPI Interrupt Mask */
    uint32_t                  : 21;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_INT_MSK. */
typedef volatile struct ALT_EMAC_GMAC_INT_MSK_s  ALT_EMAC_GMAC_INT_MSK_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_INT_MSK register from the beginning of the component. */
#define ALT_EMAC_GMAC_INT_MSK_OFST        0x3c
/* The address of the ALT_EMAC_GMAC_INT_MSK register. */
#define ALT_EMAC_GMAC_INT_MSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_MSK_OFST))

/*
 * Register : Register 16 (MAC Address0 High Register) - MAC_Address0_High
 * 
 * The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC
 * address of the station. The first DA byte that is received on the (G)MII
 * interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low
 * register. For example, if 0x112233445566 is received (0x11 in lane 0 of the
 * first column) on the (G)MII as the destination address, then the MacAddress0
 * Register [47:0] is compared with 0x665544332211.
 * 
 * Because the MAC address registers are double-synchronized to the (G)MII clock
 * domains, then the synchronization is triggered only when Bits[31:24] (in little-
 * endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register
 * are written. For proper synchronization updates, the consecutive writes to this
 * Address Low Register should be performed after at least four clock cycles in the
 * destination clock domain.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | RW     | 0xffff | MAC Address0 [47:32]
 *  [30:16] | ???    | 0x0    | *UNDEFINED*         
 *  [31]    | R      | 0x1    | Address Enable      
 * 
 */
/*
 * Field : MAC Address0 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.
 * The MAC uses this field for filtering the received frames and inserting the MAC
 * address in the Transmit Flow Control (PAUSE) Frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Address Enable - ae
 * 
 * This bit is always set to 1.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_RESET      0x1
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR0_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR0_HIGH_s
{
    uint32_t        addrhi : 16;  /* MAC Address0 [47:32] */
    uint32_t               : 15;  /* *UNDEFINED* */
    const uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR0_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR0_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR0_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_OFST        0x40
/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR0_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR0_HIGH_OFST))

/*
 * Register : Register 17 (MAC Address0 Low Register) - MAC_Address0_Low
 * 
 * The MAC Address0 Low register holds the lower 32 bits of the first 6-byte MAC
 * address of the station.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description        
 * :-------|:-------|:-----------|:--------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address0 [31:0]
 * 
 */
/*
 * Field : MAC Address0 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the first 6-byte MAC address. This is
 * used by the MAC for filtering the received frames and inserting the MAC address
 * in the Transmit Flow Control (PAUSE) Frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR0_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR0_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address0 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR0_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR0_LOW_s  ALT_EMAC_GMAC_MAC_ADDR0_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_OFST        0x44
/* The address of the ALT_EMAC_GMAC_MAC_ADDR0_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR0_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR0_LOW_OFST))

/*
 * Register : Register 18 (MAC Address1 High Register) - MAC_Address1_High
 * 
 * The MAC Address1 High register holds the upper 16 bits of the 2nd 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address1 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | RW     | 0xffff | MAC Address1 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*         
 *  [24]    | RW     | 0x0    | Mask Byte Control   
 *  [25]    | RW     | 0x0    | Mask Byte Control   
 *  [26]    | RW     | 0x0    | Mask Byte Control   
 *  [27]    | RW     | 0x0    | Mask Byte Control   
 *  [28]    | RW     | 0x0    | Mask Byte Control   
 *  [29]    | RW     | 0x0    | Mask Byte Control   
 *  [30]    | RW     | 0x0    | Source Address      
 *  [31]    | RW     | 0x0    | Address Enable      
 * 
 */
/*
 * Field : MAC Address1 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 2nd 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address1 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address1 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address1 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address1 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address1 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address1 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address1[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address1[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 2nd MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                          
 * :---------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR1_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR1_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address1 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR1_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR1_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR1_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_OFST        0x48
/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR1_HIGH_OFST))

/*
 * Register : Register 19 (MAC Address1 Low Register) - MAC_Address1_Low
 * 
 * The MAC Address1 Low register holds the lower 32 bits of the 2nd 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description        
 * :-------|:-------|:-----------|:--------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address1 [31:0]
 * 
 */
/*
 * Field : MAC Address1 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 2nd 6-byte MAC address. The content
 * of this field is undefined until loaded by software after the initialization
 * process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR1_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR1_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address1 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR1_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR1_LOW_s  ALT_EMAC_GMAC_MAC_ADDR1_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_OFST        0x4c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR1_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR1_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR1_LOW_OFST))

/*
 * Register : Register 20 (MAC Address2 High Register) - MAC_Address2_High
 * 
 * The MAC Address2 High register holds the upper 16 bits of the 3rd 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address2 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | RW     | 0xffff | MAC Address2 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*         
 *  [24]    | RW     | 0x0    | Mask Byte Control   
 *  [25]    | RW     | 0x0    | Mask Byte Control   
 *  [26]    | RW     | 0x0    | Mask Byte Control   
 *  [27]    | RW     | 0x0    | Mask Byte Control   
 *  [28]    | RW     | 0x0    | Mask Byte Control   
 *  [29]    | RW     | 0x0    | Mask Byte Control   
 *  [30]    | RW     | 0x0    | Source Address      
 *  [31]    | RW     | 0x0    | Address Enable      
 * 
 */
/*
 * Field : MAC Address2 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 3rd 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address2 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address2 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address2 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address2 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address2 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address2 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address2[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address2[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 3rd MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                          
 * :---------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR2_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR2_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address2 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR2_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR2_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR2_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_OFST        0x50
/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR2_HIGH_OFST))

/*
 * Register : Register 21 (MAC Address2 Low Register) - MAC_Address2_Low
 * 
 * The MAC Address2 Low register holds the lower 32 bits of the 3rd 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description        
 * :-------|:-------|:-----------|:--------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address2 [31:0]
 * 
 */
/*
 * Field : MAC Address2 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 3rd 6-byte MAC address. The content
 * of this field is undefined until loaded by software after the initialization
 * process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR2_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR2_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address2 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR2_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR2_LOW_s  ALT_EMAC_GMAC_MAC_ADDR2_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_OFST        0x54
/* The address of the ALT_EMAC_GMAC_MAC_ADDR2_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR2_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR2_LOW_OFST))

/*
 * Register : Register 22 (MAC Address3 High Register) - MAC_Address3_High
 * 
 * The MAC Address3 High register holds the upper 16 bits of the 4th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address3 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | RW     | 0xffff | MAC Address3 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*         
 *  [24]    | RW     | 0x0    | Mask Byte Control   
 *  [25]    | RW     | 0x0    | Mask Byte Control   
 *  [26]    | RW     | 0x0    | Mask Byte Control   
 *  [27]    | RW     | 0x0    | Mask Byte Control   
 *  [28]    | RW     | 0x0    | Mask Byte Control   
 *  [29]    | RW     | 0x0    | Mask Byte Control   
 *  [30]    | RW     | 0x0    | Source Address      
 *  [31]    | RW     | 0x0    | Address Enable      
 * 
 */
/*
 * Field : MAC Address3 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 4th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address3 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address3 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address3 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address3 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address3 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address3 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address3[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address3[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 4th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                          
 * :---------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR3_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR3_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address3 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR3_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR3_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR3_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_OFST        0x58
/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR3_HIGH_OFST))

/*
 * Register : Register 23 (MAC Address3 Low Register) - MAC_Address3_Low
 * 
 * The MAC Address3 Low register holds the lower 32 bits of the 4th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description        
 * :-------|:-------|:-----------|:--------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address3 [31:0]
 * 
 */
/*
 * Field : MAC Address3 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 4th 6-byte MAC address. The content
 * of this field is undefined until loaded by software after the initialization
 * process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR3_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR3_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address3 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR3_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR3_LOW_s  ALT_EMAC_GMAC_MAC_ADDR3_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_OFST        0x5c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR3_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR3_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR3_LOW_OFST))

/*
 * Register : Register 24 (MAC Address4 High Register) - MAC_Address4_High
 * 
 * The MAC Address4 High register holds the upper 16 bits of the 5th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address4 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | RW     | 0xffff | MAC Address4 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*         
 *  [24]    | RW     | 0x0    | Mask Byte Control   
 *  [25]    | RW     | 0x0    | Mask Byte Control   
 *  [26]    | RW     | 0x0    | Mask Byte Control   
 *  [27]    | RW     | 0x0    | Mask Byte Control   
 *  [28]    | RW     | 0x0    | Mask Byte Control   
 *  [29]    | RW     | 0x0    | Mask Byte Control   
 *  [30]    | RW     | 0x0    | Source Address      
 *  [31]    | RW     | 0x0    | Address Enable      
 * 
 */
/*
 * Field : MAC Address4 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 5th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address4 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address4 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address4 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address4 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address4 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address4 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address4[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address4[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 5th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                          
 * :---------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR4_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR4_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address4 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR4_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR4_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR4_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_OFST        0x60
/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR4_HIGH_OFST))

/*
 * Register : Register 25 (MAC Address4 Low Register) - MAC_Address4_Low
 * 
 * The MAC Address4 Low register holds the lower 32 bits of the 5th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description        
 * :-------|:-------|:-----------|:--------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address4 [31:0]
 * 
 */
/*
 * Field : MAC Address4 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 5th 6-byte MAC address. The content
 * of this field is undefined until loaded by software after the initialization
 * process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR4_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR4_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address4 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR4_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR4_LOW_s  ALT_EMAC_GMAC_MAC_ADDR4_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_OFST        0x64
/* The address of the ALT_EMAC_GMAC_MAC_ADDR4_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR4_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR4_LOW_OFST))

/*
 * Register : Register 26 (MAC Address5 High Register) - MAC_Address5_High
 * 
 * The MAC Address5 High register holds the upper 16 bits of the 6th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address5 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | RW     | 0xffff | MAC Address5 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*         
 *  [24]    | RW     | 0x0    | Mask Byte Control   
 *  [25]    | RW     | 0x0    | Mask Byte Control   
 *  [26]    | RW     | 0x0    | Mask Byte Control   
 *  [27]    | RW     | 0x0    | Mask Byte Control   
 *  [28]    | RW     | 0x0    | Mask Byte Control   
 *  [29]    | RW     | 0x0    | Mask Byte Control   
 *  [30]    | RW     | 0x0    | Source Address      
 *  [31]    | RW     | 0x0    | Address Enable      
 * 
 */
/*
 * Field : MAC Address5 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 6th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address5 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address5 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address5 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address5 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address5 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address5 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address5[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address5[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 6th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                          
 * :---------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR5_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR5_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address5 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR5_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR5_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR5_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_OFST        0x68
/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR5_HIGH_OFST))

/*
 * Register : Register 27 (MAC Address5 Low Register) - MAC_Address5_Low
 * 
 * The MAC Address5 Low register holds the lower 32 bits of the 6th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description        
 * :-------|:-------|:-----------|:--------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address5 [31:0]
 * 
 */
/*
 * Field : MAC Address5 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 6th 6-byte MAC address. The content
 * of this field is undefined until loaded by software after the initialization
 * process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR5_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR5_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address5 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR5_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR5_LOW_s  ALT_EMAC_GMAC_MAC_ADDR5_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_OFST        0x6c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR5_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR5_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR5_LOW_OFST))

/*
 * Register : Register 28 (MAC Address6 High Register) - MAC_Address6_High
 * 
 * The MAC Address6 High register holds the upper 16 bits of the 7th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address6 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | RW     | 0xffff | MAC Address6 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*         
 *  [24]    | RW     | 0x0    | Mask Byte Control   
 *  [25]    | RW     | 0x0    | Mask Byte Control   
 *  [26]    | RW     | 0x0    | Mask Byte Control   
 *  [27]    | RW     | 0x0    | Mask Byte Control   
 *  [28]    | RW     | 0x0    | Mask Byte Control   
 *  [29]    | RW     | 0x0    | Mask Byte Control   
 *  [30]    | RW     | 0x0    | Source Address      
 *  [31]    | RW     | 0x0    | Address Enable      
 * 
 */
/*
 * Field : MAC Address6 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 7th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address6 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address6 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address6 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address6 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address6 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address6 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address6[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address6[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 7th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                          
 * :---------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR6_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR6_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address6 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR6_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR6_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR6_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_OFST        0x70
/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR6_HIGH_OFST))

/*
 * Register : Register 29 (MAC Address6 Low Register) - MAC_Address6_Low
 * 
 * The MAC Address6 Low register holds the lower 32 bits of the 7th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description        
 * :-------|:-------|:-----------|:--------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address6 [31:0]
 * 
 */
/*
 * Field : MAC Address6 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 7th 6-byte MAC address. The content
 * of this field is undefined until loaded by software after the initialization
 * process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR6_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR6_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address6 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR6_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR6_LOW_s  ALT_EMAC_GMAC_MAC_ADDR6_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_OFST        0x74
/* The address of the ALT_EMAC_GMAC_MAC_ADDR6_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR6_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR6_LOW_OFST))

/*
 * Register : Register 30 (MAC Address7 High Register) - MAC_Address7_High
 * 
 * The MAC Address7 High register holds the upper 16 bits of the 8th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address7 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | RW     | 0xffff | MAC Address7 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*         
 *  [24]    | RW     | 0x0    | Mask Byte Control   
 *  [25]    | RW     | 0x0    | Mask Byte Control   
 *  [26]    | RW     | 0x0    | Mask Byte Control   
 *  [27]    | RW     | 0x0    | Mask Byte Control   
 *  [28]    | RW     | 0x0    | Mask Byte Control   
 *  [29]    | RW     | 0x0    | Mask Byte Control   
 *  [30]    | RW     | 0x0    | Source Address      
 *  [31]    | RW     | 0x0    | Address Enable      
 * 
 */
/*
 * Field : MAC Address7 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 8th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address7 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address7 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address7 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address7 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address7 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address7 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address7[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address7[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 8th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                          
 * :---------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR7_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR7_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address7 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR7_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR7_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR7_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_OFST        0x78
/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR7_HIGH_OFST))

/*
 * Register : Register 31 (MAC Address7 Low Register) - MAC_Address7_Low
 * 
 * The MAC Address7 Low register holds the lower 32 bits of the 8th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description        
 * :-------|:-------|:-----------|:--------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address7 [31:0]
 * 
 */
/*
 * Field : MAC Address7 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 8th 6-byte MAC address. The content
 * of this field is undefined until loaded by software after the initialization
 * process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR7_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR7_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address7 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR7_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR7_LOW_s  ALT_EMAC_GMAC_MAC_ADDR7_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_OFST        0x7c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR7_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR7_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR7_LOW_OFST))

/*
 * Register : Register 32 (MAC Address8 High Register) - MAC_Address8_High
 * 
 * The MAC Address8 High register holds the upper 16 bits of the 9th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address8 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | RW     | 0xffff | MAC Address8 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*         
 *  [24]    | RW     | 0x0    | Mask Byte Control   
 *  [25]    | RW     | 0x0    | Mask Byte Control   
 *  [26]    | RW     | 0x0    | Mask Byte Control   
 *  [27]    | RW     | 0x0    | Mask Byte Control   
 *  [28]    | RW     | 0x0    | Mask Byte Control   
 *  [29]    | RW     | 0x0    | Mask Byte Control   
 *  [30]    | RW     | 0x0    | Source Address      
 *  [31]    | RW     | 0x0    | Address Enable      
 * 
 */
/*
 * Field : MAC Address8 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 9th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address8 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address8 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address8 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address8 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address8 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address8 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address8[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address8[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 9th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                          
 * :---------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR8_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR8_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address8 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR8_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR8_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR8_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_OFST        0x80
/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR8_HIGH_OFST))

/*
 * Register : Register 33 (MAC Address8 Low Register) - MAC_Address8_Low
 * 
 * The MAC Address8 Low register holds the lower 32 bits of the 9th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description        
 * :-------|:-------|:-----------|:--------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address8 [31:0]
 * 
 */
/*
 * Field : MAC Address8 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 9th 6-byte MAC address. The content
 * of this field is undefined until loaded by software after the initialization
 * process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR8_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR8_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address8 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR8_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR8_LOW_s  ALT_EMAC_GMAC_MAC_ADDR8_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_OFST        0x84
/* The address of the ALT_EMAC_GMAC_MAC_ADDR8_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR8_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR8_LOW_OFST))

/*
 * Register : Register 34 (MAC Address9 High Register) - MAC_Address9_High
 * 
 * The MAC Address9 High register holds the upper 16 bits of the 10th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address9 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description         
 * :--------|:-------|:-------|:---------------------
 *  [15:0]  | RW     | 0xffff | MAC Address9 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*         
 *  [24]    | RW     | 0x0    | Mask Byte Control   
 *  [25]    | RW     | 0x0    | Mask Byte Control   
 *  [26]    | RW     | 0x0    | Mask Byte Control   
 *  [27]    | RW     | 0x0    | Mask Byte Control   
 *  [28]    | RW     | 0x0    | Mask Byte Control   
 *  [29]    | RW     | 0x0    | Mask Byte Control   
 *  [30]    | RW     | 0x0    | Source Address      
 *  [31]    | RW     | 0x0    | Address Enable      
 * 
 */
/*
 * Field : MAC Address9 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 10th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address9 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address9 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address9 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address9 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address9 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address9 high and low registers. Each
 * bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description                        
 * :---------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_UNMSKED    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_E_MSKED      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address9[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address9[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 10th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                          
 * :---------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR9_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR9_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address9 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR9_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR9_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR9_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_OFST        0x88
/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR9_HIGH_OFST))

/*
 * Register : Register 35 (MAC Address9 Low Register) - MAC_Address9_Low
 * 
 * The MAC Address9 Low register holds the lower 32 bits of the 10th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description        
 * :-------|:-------|:-----------|:--------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address9 [31:0]
 * 
 */
/*
 * Field : MAC Address9 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 10th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR9_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR9_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address9 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR9_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR9_LOW_s  ALT_EMAC_GMAC_MAC_ADDR9_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_OFST        0x8c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR9_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR9_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR9_LOW_OFST))

/*
 * Register : Register 36 (MAC Address10 High Register) - MAC_Address10_High
 * 
 * The MAC Address10 High register holds the upper 16 bits of the 11th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address10 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address10 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address10 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 11th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address10 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address10 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address10 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address10 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address10 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address10 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address10[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address10[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 11th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR10_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR10_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address10 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR10_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR10_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR10_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_OFST        0x90
/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR10_HIGH_OFST))

/*
 * Register : Register 37 (MAC Address10 Low Register) - MAC_Address10_Low
 * 
 * The MAC Address10 Low register holds the lower 32 bits of the 11th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address10 [31:0]
 * 
 */
/*
 * Field : MAC Address10 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 11th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR10_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR10_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address10 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR10_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR10_LOW_s  ALT_EMAC_GMAC_MAC_ADDR10_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_OFST        0x94
/* The address of the ALT_EMAC_GMAC_MAC_ADDR10_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR10_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR10_LOW_OFST))

/*
 * Register : Register 38 (MAC Address11 High Register) - MAC_Address11_High
 * 
 * The MAC Address11 High register holds the upper 16 bits of the 12th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address11 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address11 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address11 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 12th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address11 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address11 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address11 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address11 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address11 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address11 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address11[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address11[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 12th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR11_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR11_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address11 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR11_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR11_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR11_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_OFST        0x98
/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR11_HIGH_OFST))

/*
 * Register : Register 39 (MAC Address11 Low Register) - MAC_Address11_Low
 * 
 * The MAC Address11 Low register holds the lower 32 bits of the 12th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address11 [31:0]
 * 
 */
/*
 * Field : MAC Address11 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 12th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR11_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR11_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address11 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR11_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR11_LOW_s  ALT_EMAC_GMAC_MAC_ADDR11_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_OFST        0x9c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR11_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR11_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR11_LOW_OFST))

/*
 * Register : Register 40 (MAC Address12 High Register) - MAC_Address12_High
 * 
 * The MAC Address12 High register holds the upper 16 bits of the 13th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address12 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address12 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address12 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 13th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address12 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address12 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address12 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address12 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address12 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address12 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address12[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address12[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 13th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR12_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR12_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address12 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR12_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR12_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR12_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_OFST        0xa0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR12_HIGH_OFST))

/*
 * Register : Register 41 (MAC Address12 Low Register) - MAC_Address12_Low
 * 
 * The MAC Address12 Low register holds the lower 32 bits of the 13th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address12 [31:0]
 * 
 */
/*
 * Field : MAC Address12 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 13th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR12_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR12_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address12 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR12_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR12_LOW_s  ALT_EMAC_GMAC_MAC_ADDR12_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_OFST        0xa4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR12_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR12_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR12_LOW_OFST))

/*
 * Register : Register 42 (MAC Address13 High Register) - MAC_Address13_High
 * 
 * The MAC Address13 High register holds the upper 16 bits of the 14th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address13 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address13 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address13 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 14th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address13 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address13 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address13 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address13 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address13 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address13 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address13[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address13[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 14th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR13_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR13_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address13 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR13_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR13_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR13_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_OFST        0xa8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR13_HIGH_OFST))

/*
 * Register : Register 43 (MAC Address13 Low Register) - MAC_Address13_Low
 * 
 * The MAC Address13 Low register holds the lower 32 bits of the 14th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address13 [31:0]
 * 
 */
/*
 * Field : MAC Address13 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 14th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR13_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR13_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address13 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR13_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR13_LOW_s  ALT_EMAC_GMAC_MAC_ADDR13_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_OFST        0xac
/* The address of the ALT_EMAC_GMAC_MAC_ADDR13_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR13_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR13_LOW_OFST))

/*
 * Register : Register 44 (MAC Address14 High Register) - MAC_Address14_High
 * 
 * The MAC Address14 High register holds the upper 16 bits of the 15th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address14 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address14 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address14 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 15th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address14 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address14 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address14 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address14 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address14 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address14 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address14[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address14[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 15th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR14_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR14_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address14 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR14_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR14_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR14_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_OFST        0xb0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR14_HIGH_OFST))

/*
 * Register : Register 45 (MAC Address14 Low Register) - MAC_Address14_Low
 * 
 * The MAC Address14 Low register holds the lower 32 bits of the 15th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address14 [31:0]
 * 
 */
/*
 * Field : MAC Address14 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 15th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR14_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR14_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address14 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR14_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR14_LOW_s  ALT_EMAC_GMAC_MAC_ADDR14_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_OFST        0xb4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR14_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR14_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR14_LOW_OFST))

/*
 * Register : Register 46 (MAC Address15 High Register) - MAC_Address15_High
 * 
 * The MAC Address15 High register holds the upper 16 bits of the 16th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address15 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address15 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address15 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 16th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address15 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address15 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address15 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address15 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address15 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address15 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address15[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address15[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 16th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR15_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR15_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address15 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR15_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR15_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR15_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_OFST        0xb8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR15_HIGH_OFST))

/*
 * Register : Register 47 (MAC Address15 Low Register) - MAC_Address15_Low
 * 
 * The MAC Address15 Low register holds the lower 32 bits of the 16th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address15 [31:0]
 * 
 */
/*
 * Field : MAC Address15 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 16th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR15_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR15_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address15 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR15_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR15_LOW_s  ALT_EMAC_GMAC_MAC_ADDR15_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_OFST        0xbc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR15_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR15_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR15_LOW_OFST))

/*
 * Register : Register 54 (SGMII/RGMII/SMII Status Register) - SGMII_RGMII_SMII_Control_Status
 * 
 * The SGMII/RGMII/SMII Status register indicates the status signals received by
 * the RGMII interface (selected at reset) from the PHY.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [0]    | R      | 0x0   | Link Mode  
 *  [2:1]  | R      | 0x0   | Link Speed 
 *  [3]    | R      | 0x0   | Link Status
 *  [31:4] | ???    | 0x0   | *UNDEFINED*
 * 
 */
/*
 * Field : Link Mode - lnkmod
 * 
 * This bit indicates the current mode of operation of the link
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description
 * :--------------------------------------------|:------|:------------
 *  ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP | 0x0   | Half Duplex
 *  ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP | 0x1   | Full Duplex
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD
 * 
 * Half Duplex
 */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD
 * 
 * Full Duplex
 */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP 0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD field value from a register. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Link Speed - lnkspeed
 * 
 * This bit indicates the current speed of the link. Bit 2 is reserved when the MAC
 * is configured for the SMII PHY interface.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description      
 * :------------------------------------------------------|:------|:------------------
 *  ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ | 0x0   | Link Speed 2.5MHz
 *  ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ      | 0x1   | Link Speed 25MHz 
 *  ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ     | 0x2   | Link Speed 125MHz
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED
 * 
 * Link Speed 2.5MHz
 */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED
 * 
 * Link Speed 25MHz
 */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ        0x1
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED
 * 
 * Link Speed 125MHz
 */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ       0x2

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET_MSK    0x00000006
/* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_CLR_MSK    0xfffffff9
/* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED field value from a register. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_GET(value) (((value) & 0x00000006) >> 1)
/* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET(value) (((value) << 1) & 0x00000006)

/*
 * Field : Link Status - lnksts
 * 
 * This bit indicates whether the link is up (1'b1) or down (1'b0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                         | Value | Description
 * :---------------------------------------------|:------|:------------
 *  ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN | 0x0   | Linkdown   
 *  ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP   | 0x1   | Linkup     
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS
 * 
 * Linkdown
 */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS
 * 
 * Linkup
 */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS field value from a register. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET(value) (((value) << 3) & 0x00000008)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MII_CTL_STAT.
 */
struct ALT_EMAC_GMAC_MII_CTL_STAT_s
{
    const uint32_t  lnkmod   :  1;  /* Link Mode */
    const uint32_t  lnkspeed :  2;  /* Link Speed */
    const uint32_t  lnksts   :  1;  /* Link Status */
    uint32_t                 : 28;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MII_CTL_STAT. */
typedef volatile struct ALT_EMAC_GMAC_MII_CTL_STAT_s  ALT_EMAC_GMAC_MII_CTL_STAT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MII_CTL_STAT register from the beginning of the component. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_OFST        0xd8
/* The address of the ALT_EMAC_GMAC_MII_CTL_STAT register. */
#define ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MII_CTL_STAT_OFST))

/*
 * Register : Register 64 (MMC Control Register) - MMC_Control
 * 
 * The MMC Control register establishes the operating mode of the management
 * counters.
 * 
 * Note:
 * 
 * The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset).
 * Therefore, when the Software tries to set both bits in the same write cycle, all
 * counters are cleared and the bit 4 is not set.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                                     
 * :-------|:-------|:------|:-------------------------------------------------
 *  [0]    | RW     | 0x0   | Counters Reset                                  
 *  [1]    | RW     | 0x0   | Counters Stop Rollover                          
 *  [2]    | RW     | 0x0   | Reset on Read                                   
 *  [3]    | RW     | 0x0   | MMC Counter Freeze                              
 *  [4]    | RW     | 0x0   | Counters Preset                                 
 *  [5]    | RW     | 0x0   | Full-Half Preset                                
 *  [7:6]  | ???    | 0x0   | *UNDEFINED*                                     
 *  [8]    | RW     | 0x0   | Update MMC Counters for Dropped Broadcast Frames
 *  [31:9] | ???    | 0x0   | *UNDEFINED*                                     
 * 
 */
/*
 * Field : Counters Reset - cntrst
 * 
 * When this bit is set, all counters are reset. This bit is cleared automatically
 * after one clock cycle.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                     
 * :------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_DISD | 0x0   | Auto cleared after 1 clock cycle
 *  ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_END  | 0x1   | All Counters Reset              
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTRST
 * 
 * Auto cleared after 1 clock cycle
 */
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTRST
 * 
 * All Counters Reset
 */
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTRST field value from a register. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Counters Stop Rollover - cntstopro
 * 
 * When this bit is set, after reaching maximum value, the counter does not roll
 * over to zero.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description               
 * :---------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_DISD | 0x0   | Counter Roll Over         
 *  ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_END  | 0x1   | Counter does not Roll Over
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO
 * 
 * Counter Roll Over
 */
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO
 * 
 * Counter does not Roll Over
 */
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO field value from a register. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Reset on Read - rstonrd
 * 
 * When this bit is set, the MMC counters are reset to zero after Read (self-
 * clearing after reset). The counters are cleared when the least significant byte
 * lane (bits[7:0]) is read.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description        
 * :-------------------------------------|:------|:--------------------
 *  ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_DISD | 0x0   | No reset after read
 *  ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_END  | 0x1   | Reset after read   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_RSTONRD
 * 
 * No reset after read
 */
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_RSTONRD
 * 
 * Reset after read
 */
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field. */
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_CTL_RSTONRD field value from a register. */
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : MMC Counter Freeze - cntfreez
 * 
 * When this bit is set, it freezes all MMC counters to their current value. Until
 * this bit is reset to 0, no MMC counter is updated because of any transmitted or
 * received frame. If any MMC counter is read with the Reset on Read bit set, then
 * that counter is also cleared in this mode.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                         
 * :--------------------------------------|:------|:-------------------------------------
 *  ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_DISD | 0x0   | Update MMC Counters                 
 *  ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_END  | 0x1   | Freeze MMC counters to current value
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ
 * 
 * Update MMC Counters
 */
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ
 * 
 * Freeze MMC counters to current value
 */
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ field value from a register. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Counters Preset - cntprst
 * 
 * When this bit is set, all counters are initialized or preset to almost full or
 * almost half according to bit 5. This bit is cleared automatically after 1 clock
 * cycle. This bit, along with bit 5, is useful for debugging and testing the
 * assertion of interrupts because of MMC counter becoming half-full or full.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                           
 * :-------------------------------------|:------|:---------------------------------------
 *  ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_DISD | 0x0   | Counters not preset                   
 *  ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_END  | 0x1   | Counters preset to full or almost full
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRST
 * 
 * Counters not preset
 */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRST
 * 
 * Counters preset to full or almost full
 */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTPRST field value from a register. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Full-Half Preset - cntprstlvl
 * 
 * When low and bit 4 is set, all MMC counters get preset to almost-half value. All
 * octet counters get preset to 0x7FFF_F800 (half - 2KBytes) and all frame-counters
 * gets preset to 0x7FFF_FFF0 (half - 16).
 * 
 * When this bit is high and bit 4 is set, all MMC counters get preset to almost-
 * full value. All octet counters get preset to 0xFFFF_F800 (full - 2KBytes) and
 * all frame-counters gets preset to 0xFFFF_FFF0 (full - 16).
 * 
 * For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the
 * respective octet and frame counters. Similarly, the almost-full preset values
 * for the 16-bit counters are 0xF800 and 0xFFF0.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                       
 * :----------------------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTHALF | 0x0   | Preset All Counters to almost-half
 *  ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTFULL | 0x1   | Present All Counters almost-full  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL
 * 
 * Preset All Counters to almost-half
 */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTHALF   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL
 * 
 * Present All Counters almost-full
 */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTFULL   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL field value from a register. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Update MMC Counters for Dropped Broadcast Frames - ucdbc
 * 
 * When set, this bit enables MAC to update all the related MMC Counters for
 * Broadcast frames dropped due to setting of DBF bit (Disable Broadcast Frames) of
 * MAC Filter Register at offset 0x0004.
 * 
 * When reset, MMC Counters are not updated for dropped Broadcast frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value. */
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field. */
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_CTL_UCDBC field value from a register. */
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET(value) (((value) << 8) & 0x00000100)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MMC_CTL.
 */
struct ALT_EMAC_GMAC_MMC_CTL_s
{
    uint32_t  cntrst     :  1;  /* Counters Reset */
    uint32_t  cntstopro  :  1;  /* Counters Stop Rollover */
    uint32_t  rstonrd    :  1;  /* Reset on Read */
    uint32_t  cntfreez   :  1;  /* MMC Counter Freeze */
    uint32_t  cntprst    :  1;  /* Counters Preset */
    uint32_t  cntprstlvl :  1;  /* Full-Half Preset */
    uint32_t             :  2;  /* *UNDEFINED* */
    uint32_t  ucdbc      :  1;  /* Update MMC Counters for Dropped Broadcast Frames */
    uint32_t             : 23;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MMC_CTL. */
typedef volatile struct ALT_EMAC_GMAC_MMC_CTL_s  ALT_EMAC_GMAC_MMC_CTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MMC_CTL register from the beginning of the component. */
#define ALT_EMAC_GMAC_MMC_CTL_OFST        0x100
/* The address of the ALT_EMAC_GMAC_MMC_CTL register. */
#define ALT_EMAC_GMAC_MMC_CTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_CTL_OFST))

/*
 * Register : Register 65 (MMC Receive Interrupt Register) - MMC_Receive_Interrupt
 * 
 * The MMC Receive Interrupt register maintains the interrupts that are generated
 * when the following happens:
 * 
 * * Receive statistic counters reach half of their maximum values (0x8000_0000 for
 *   32-bit counter and 0x8000 for 16-bit counter).
 * 
 * * Receive statistic counters cross their maximum values (0xFFFF_FFFF for 32-bit
 *   counter and 0xFFFF for 16-bit counter).
 * 
 * When the Counter Stop Rollover is set, then interrupts are set but the counter
 * remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide
 * register. An interrupt bit is cleared when the respective MMC counter that
 * caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the
 * respective counter must be read in order to clear the interrupt bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                                              
 * :--------|:-------|:------|:--------------------------------------------------------------------------
 *  [0]     | R      | 0x0   | MMC Receive Good Bad Frame Counter Interrupt Status                      
 *  [1]     | R      | 0x0   | MMC Receive Good Bad Octet Counter Interrupt Status                      
 *  [2]     | R      | 0x0   | MMC Receive Good Octet Counter Interrupt Status.                         
 *  [3]     | R      | 0x0   | MMC Receive Broadcast Good Frame Counter Interrupt Status.               
 *  [4]     | R      | 0x0   | MMC Receive Multicast Good Frame Counter Interrupt Status                
 *  [5]     | R      | 0x0   | MMC Receive CRC Error Frame Counter Interrupt Status                     
 *  [6]     | R      | 0x0   | MMC Receive Alignment Error Frame Counter Interrupt Status               
 *  [7]     | R      | 0x0   | MMC Receive Runt Frame Counter Interrupt Status                          
 *  [8]     | R      | 0x0   | MMC Receive Jabber Error Frame Counter Interrupt Status                  
 *  [9]     | R      | 0x0   | MMC Receive Undersize Good Frame Counter Interrupt Status                
 *  [10]    | R      | 0x0   | MMC Receive Oversize Good Frame Counter Interrupt Status                 
 *  [11]    | R      | 0x0   | MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status             
 *  [12]    | R      | 0x0   | MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status      
 *  [13]    | R      | 0x0   | MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status     
 *  [14]    | R      | 0x0   | MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status     
 *  [15]    | R      | 0x0   | MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status    
 *  [16]    | R      | 0x0   | MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status
 *  [17]    | R      | 0x0   | MMC Receive Unicast Good Frame Counter Interrupt Status                  
 *  [18]    | R      | 0x0   | MMC Receive Length Error Frame Counter Interrupt Status                  
 *  [19]    | R      | 0x0   | MMC Receive Out Of Range Error Frame Counter Interrupt Status            
 *  [20]    | R      | 0x0   | MMC Receive Pause Frame Counter Interrupt Status                         
 *  [21]    | R      | 0x0   | MMC Receive FIFO Overflow Frame Counter Interrupt Status                 
 *  [22]    | R      | 0x0   | MMC Receive VLAN Good Bad Frame Counter Interrupt Status                 
 *  [23]    | R      | 0x0   | MMC Receive Watchdog Error Frame Counter Interrupt Status                
 *  [24]    | R      | 0x0   | MMC Receive Error Frame Counter Interrupt Status                         
 *  [25]    | R      | 0x0   | MMC Receive Control Frame Counter Interrupt Status                       
 *  [31:26] | ???    | 0x0   | *UNDEFINED*                                                              
 * 
 */
/*
 * Field : MMC Receive Good Bad Frame Counter Interrupt Status - rxgbfrmis
 * 
 * This bit is set when the rxframecount_bg counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                       
 * :----------------------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF | 0x0   | Preset All Counters to almost-half
 *  ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL | 0x1   | Present All Counters almost-full  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS
 * 
 * Preset All Counters to almost-half
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS
 * 
 * Present All Counters almost-full
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : MMC Receive Good Bad Octet Counter Interrupt Status - rxgboctis
 * 
 * This bit is set when the rxoctetcount_bg counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT | 0x0   | Rxoctetcount_bg < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT   | 0x1   | Rxoctetcount_bg >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS
 * 
 * Rxoctetcount_bg < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS
 * 
 * Rxoctetcount_bg >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : MMC Receive Good Octet Counter Interrupt Status. - rxgoctis
 * 
 * This bit is set when the rxoctetcount_g counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description               
 * :----------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT | 0x0   | Rxoctetcount_g < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT   | 0x1   | Rxoctetcount_g >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS
 * 
 * Rxoctetcount_g < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS
 * 
 * Rxoctetcount_g >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : MMC Receive Broadcast Good Frame Counter Interrupt Status. - rxbcgfis
 * 
 * This bit is set when the rxbroadcastframes_g counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : MMC Receive Multicast Good Frame Counter Interrupt Status - rxmcgfis
 * 
 * This bit is set when the rxmulticastframes_g counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                    
 * :----------------------------------------|:------|:--------------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT | 0x0   | rxbroadcastframes_g < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT   | 0x1   | rxbroadcastframes_g >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS
 * 
 * rxbroadcastframes_g < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS
 * 
 * rxbroadcastframes_g >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : MMC Receive CRC Error Frame Counter Interrupt Status - rxcrcerfis
 * 
 * This bit is set when the rxcrcerror counter reaches half of the maximum value or
 * the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description           
 * :------------------------------------------|:------|:-----------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT | 0x0   | rxcrcerror < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT   | 0x1   | rxcrcerror >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS
 * 
 * rxcrcerror < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS
 * 
 * rxcrcerror >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : MMC Receive Alignment Error Frame Counter Interrupt Status - rxalgnerfis
 * 
 * This bit is set when the rxalignmenterror counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                 
 * :-------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT | 0x0   | rxalignmenterror < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT   | 0x1   | rxalignmenterror >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS
 * 
 * rxalignmenterror < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS
 * 
 * rxalignmenterror >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_MSB        6
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : MMC Receive Runt Frame Counter Interrupt Status - rxruntfis
 * 
 * This bit is set when the rxrunterror counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description            
 * :-----------------------------------------|:------|:------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT | 0x0   | rxrunterror < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT   | 0x1   | rxrunterror >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS
 * 
 * rxrunterror < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS
 * 
 * rxrunterror >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : MMC Receive Jabber Error Frame Counter Interrupt Status - rxjaberfis
 * 
 * This bit is set when the rxjabbererror counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description              
 * :------------------------------------------|:------|:--------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT | 0x0   | rxjabbererror < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT   | 0x1   | rxjabbererror >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS
 * 
 * rxjabbererror < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS
 * 
 * rxjabbererror >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : MMC Receive Undersize Good Frame Counter Interrupt Status - rxusizegfis
 * 
 * This bit is set when the rxundersize_g counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description              
 * :-------------------------------------------|:------|:--------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT | 0x0   | rxundersize_g < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT   | 0x1   | rxundersize_g >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS
 * 
 * rxundersize_g < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS
 * 
 * rxundersize_g >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : MMC Receive Oversize Good Frame Counter Interrupt Status - rxosizegfis
 * 
 * This bit is set when the rxoversize_g counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description              
 * :-------------------------------------------|:------|:--------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT | 0x0   | rxoversize_g  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT   | 0x1   | rxoversize_g  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS
 * 
 * rxoversize_g  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS
 * 
 * rxoversize_g  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status - rx64octgbfis
 * 
 * This bit is set when the rx64octets_gb counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description               
 * :--------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT | 0x0   | rx64octets_gb   < half max
 *  ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT   | 0x1   | rx64octets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS
 * 
 * rx64octets_gb   < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS
 * 
 * rx64octets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_MSB        11
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET_MSK    0x00000800
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status - rx65t127octgbfis
 * 
 * This is set when the rx65to127octets_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description                    
 * :------------------------------------------------|:------|:--------------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT | 0x0   | rx65to127octets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT   | 0x1   | rx65to127octets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS
 * 
 * rx65to127octets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS
 * 
 * rx65to127octets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_MSB        12
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET_MSK    0x00001000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_CLR_MSK    0xffffefff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status - rx128t255octgbfis
 * 
 * This bit is set when the rx128to255octets_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description                     
 * :-------------------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT | 0x0   | rx128to255octets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT   | 0x1   | rx128to255octets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS
 * 
 * rx128to255octets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS
 * 
 * rx128to255octets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_MSB        13
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status - rx256t511octgbfis
 * 
 * This bit is set when the rx256to511octets_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description                     
 * :-------------------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT | 0x0   | rx256to511octets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT   | 0x1   | rx256to511octets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS
 * 
 * rx256to511octets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS
 * 
 * rx256to511octets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_MSB        14
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET_MSK    0x00004000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_CLR_MSK    0xffffbfff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - rx512t1023octgbfis
 * 
 * This bit is set when the rx512to1023octets_gb counter reaches half of the
 * maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description                      
 * :--------------------------------------------------|:------|:----------------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT | 0x0   | rx512to1023octets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT   | 0x1   | rx512to1023octets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS
 * 
 * rx512to1023octets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS
 * 
 * rx512to1023octets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET_MSK    0x00008000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_CLR_MSK    0xffff7fff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - rx1024tmaxoctgbfis
 * 
 * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the
 * maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description                      
 * :--------------------------------------------------|:------|:----------------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT | 0x0   | rx1024tomaxoctets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT   | 0x1   | rx1024tomaxoctets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS
 * 
 * rx1024tomaxoctets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS
 * 
 * rx1024tomaxoctets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : MMC Receive Unicast Good Frame Counter Interrupt Status - rxucgfis
 * 
 * This bit is set when the rxunicastframes_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                      
 * :----------------------------------------|:------|:----------------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT | 0x0   | rx1024tomaxoctets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT   | 0x1   | rx1024tomaxoctets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS
 * 
 * rx1024tomaxoctets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS
 * 
 * rx1024tomaxoctets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_MSB        17
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET_MSK    0x00020000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : MMC Receive Length Error Frame Counter Interrupt Status - rxlenerfis
 * 
 * This bit is set when the rxlengtherror counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description               
 * :------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT | 0x0   | rxlengtherror  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT   | 0x1   | rxlengtherror  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS
 * 
 * rxlengtherror  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS
 * 
 * rxlengtherror  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : MMC Receive Out Of Range Error Frame Counter Interrupt Status - rxorangefis
 * 
 * This bit is set when the rxoutofrangetype counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                  
 * :-------------------------------------------|:------|:------------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT | 0x0   | rxoutofrangetype  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT   | 0x1   | rxoutofrangetype  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS
 * 
 * rxoutofrangetype  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS
 * 
 * rxoutofrangetype  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : MMC Receive Pause Frame Counter Interrupt Status - rxpausfis
 * 
 * This bit is set when the rxpauseframe counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description              
 * :-----------------------------------------|:------|:--------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT | 0x0   | rxpauseframe  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT   | 0x1   | rxpauseframe  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS
 * 
 * rxpauseframe  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS
 * 
 * rxpauseframe  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : MMC Receive FIFO Overflow Frame Counter Interrupt Status - rxfovfis
 * 
 * This bit is set when the rxfifooverflow counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                
 * :----------------------------------------|:------|:----------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT | 0x0   | rxfifooverflow  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT   | 0x1   | rxfifooverflow  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS
 * 
 * rxfifooverflow  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS
 * 
 * rxfifooverflow  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : MMC Receive VLAN Good Bad Frame Counter Interrupt Status - rxvlangbfis
 * 
 * This bit is set when the rxvlanframes_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                 
 * :-------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT | 0x0   | rxvlanframes_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT   | 0x1   | rxvlanframes_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS
 * 
 * rxvlanframes_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS
 * 
 * rxvlanframes_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_MSB        22
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET_MSK    0x00400000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_CLR_MSK    0xffbfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : MMC Receive Watchdog Error Frame Counter Interrupt Status - rxwdogfis
 * 
 * This bit is set when the rxwatchdogerror counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT | 0x0   | rxwatchdogerror  < half max 
 *  ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT   | 0x1   | rxwatchdogerror  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS
 * 
 * rxwatchdogerror  < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS
 * 
 * rxwatchdogerror  >= half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_MSB        23
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET_MSK    0x00800000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_CLR_MSK    0xff7fffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : MMC Receive Error Frame Counter Interrupt Status - rxrcverrfis
 * 
 * This bit is set when the rxrcverror counter reaches half of the maximum value or
 * the maximum value.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : MMC Receive Control Frame Counter Interrupt Status - rxctrlfis
 * 
 * This bit is set when the rxctrlframes_g counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET(value) (((value) << 25) & 0x02000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MMC_RX_INT.
 */
struct ALT_EMAC_GMAC_MMC_RX_INT_s
{
    const uint32_t  rxgbfrmis          :  1;  /* MMC Receive Good Bad Frame Counter Interrupt Status */
    const uint32_t  rxgboctis          :  1;  /* MMC Receive Good Bad Octet Counter Interrupt Status */
    const uint32_t  rxgoctis           :  1;  /* MMC Receive Good Octet Counter Interrupt Status. */
    const uint32_t  rxbcgfis           :  1;  /* MMC Receive Broadcast Good Frame Counter Interrupt Status. */
    const uint32_t  rxmcgfis           :  1;  /* MMC Receive Multicast Good Frame Counter Interrupt Status */
    const uint32_t  rxcrcerfis         :  1;  /* MMC Receive CRC Error Frame Counter Interrupt Status */
    const uint32_t  rxalgnerfis        :  1;  /* MMC Receive Alignment Error Frame Counter Interrupt Status */
    const uint32_t  rxruntfis          :  1;  /* MMC Receive Runt Frame Counter Interrupt Status */
    const uint32_t  rxjaberfis         :  1;  /* MMC Receive Jabber Error Frame Counter Interrupt Status */
    const uint32_t  rxusizegfis        :  1;  /* MMC Receive Undersize Good Frame Counter Interrupt Status */
    const uint32_t  rxosizegfis        :  1;  /* MMC Receive Oversize Good Frame Counter Interrupt Status */
    const uint32_t  rx64octgbfis       :  1;  /* MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  rx65t127octgbfis   :  1;  /* MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  rx128t255octgbfis  :  1;  /* MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  rx256t511octgbfis  :  1;  /* MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  rx512t1023octgbfis :  1;  /* MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  rx1024tmaxoctgbfis :  1;  /* MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  rxucgfis           :  1;  /* MMC Receive Unicast Good Frame Counter Interrupt Status */
    const uint32_t  rxlenerfis         :  1;  /* MMC Receive Length Error Frame Counter Interrupt Status */
    const uint32_t  rxorangefis        :  1;  /* MMC Receive Out Of Range Error Frame Counter Interrupt Status */
    const uint32_t  rxpausfis          :  1;  /* MMC Receive Pause Frame Counter Interrupt Status */
    const uint32_t  rxfovfis           :  1;  /* MMC Receive FIFO Overflow Frame Counter Interrupt Status */
    const uint32_t  rxvlangbfis        :  1;  /* MMC Receive VLAN Good Bad Frame Counter Interrupt Status */
    const uint32_t  rxwdogfis          :  1;  /* MMC Receive Watchdog Error Frame Counter Interrupt Status */
    const uint32_t  rxrcverrfis        :  1;  /* MMC Receive Error Frame Counter Interrupt Status */
    const uint32_t  rxctrlfis          :  1;  /* MMC Receive Control Frame Counter Interrupt Status */
    uint32_t                           :  6;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MMC_RX_INT. */
typedef volatile struct ALT_EMAC_GMAC_MMC_RX_INT_s  ALT_EMAC_GMAC_MMC_RX_INT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MMC_RX_INT register from the beginning of the component. */
#define ALT_EMAC_GMAC_MMC_RX_INT_OFST        0x104
/* The address of the ALT_EMAC_GMAC_MMC_RX_INT register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_OFST))

/*
 * Register : Register 66 (MMC Transmit Interrupt Register) - MMC_Transmit_Interrupt
 * 
 * The MMC Transmit Interrupt register maintains the interrupts generated when
 * transmit statistic counters reach half of their maximum values (0x8000_0000 for
 * 32-bit counter and 0x8000 for 16-bit counter), and the maximum values
 * (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter
 * Stop Rollover is set, then interrupts are set but the counter remains at all-
 * ones. The MMC Transmit Interrupt register is a 32-bit wide register. An
 * interrupt bit is cleared when the respective MMC counter that caused the
 * interrupt is read. The least significant byte lane (Bits[7:0]) of the respective
 * counter must be read in order to clear the interrupt bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                                               
 * :--------|:-------|:------|:---------------------------------------------------------------------------
 *  [0]     | R      | 0x0   | MMC Transmit Good Bad Octet Counter Interrupt Status                      
 *  [1]     | R      | 0x0   | MMC Transmit Good Bad Frame Counter Interrupt Status                      
 *  [2]     | R      | 0x0   | MMC Transmit Broadcast Good Frame Counter Interrupt Status                
 *  [3]     | R      | 0x0   | MMC Transmit Multicast Good Frame Counter Interrupt Status                
 *  [4]     | R      | 0x0   | MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status.            
 *  [5]     | R      | 0x0   | MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status      
 *  [6]     | R      | 0x0   | MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status     
 *  [7]     | R      | 0x0   | MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status     
 *  [8]     | R      | 0x0   | MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status    
 *  [9]     | R      | 0x0   | MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status
 *  [10]    | R      | 0x0   | MMC Transmit Unicast Good Bad Frame Counter Interrupt Status              
 *  [11]    | R      | 0x0   | MMC Transmit Multicast Good Bad Frame Counter Interrupt Status            
 *  [12]    | R      | 0x0   | MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status            
 *  [13]    | R      | 0x0   | MMC Transmit Underflow Error Frame Counter Interrupt Status               
 *  [14]    | R      | 0x0   | MMC Transmit Single Collision Good Frame Counter Interrupt Status         
 *  [15]    | R      | 0x0   | MMC Transmit Multiple Collision Good Frame Counter Interrupt Status       
 *  [16]    | R      | 0x0   | MMC Transmit Deferred Frame Counter Interrupt Status                      
 *  [17]    | R      | 0x0   | MMC Transmit Late Collision Frame Counter Interrupt Status                
 *  [18]    | R      | 0x0   | MMC Transmit Excessive Collision Frame Counter Interrupt Status           
 *  [19]    | R      | 0x0   | MMC Transmit Carrier Error Frame Counter Interrupt Status                 
 *  [20]    | R      | 0x0   | MMC Transmit Good Octet Counter Interrupt Status                          
 *  [21]    | R      | 0x0   | MMC Transmit Good Frame Counter Interrupt Status                          
 *  [22]    | R      | 0x0   | MMC Transmit Excessive Deferral Frame Counter Interrupt Status            
 *  [23]    | R      | 0x0   | MMC Transmit Pause Frame Counter Interrupt Status                         
 *  [24]    | R      | 0x0   | MMC Transmit VLAN Good Frame Counter Interrupt Status                     
 *  [25]    | R      | 0x0   | MMC Transmit Oversize Good Frame Counter Interrupt Status                 
 *  [31:26] | ???    | 0x0   | *UNDEFINED*                                                               
 * 
 */
/*
 * Field : MMC Transmit Good Bad Octet Counter Interrupt Status - txgboctis
 * 
 * This bit is set when the txoctetcount_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT | 0x0   | txoctetcount_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT   | 0x1   | txoctetcount_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS
 * 
 * txoctetcount_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS
 * 
 * txoctetcount_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : MMC Transmit Good Bad Frame Counter Interrupt Status - txgbfrmis
 * 
 * This bit is set when the txframecount_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT | 0x0   | txframecount_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT   | 0x1   | txframecount_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS
 * 
 * txframecount_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS
 * 
 * txframecount_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : MMC Transmit Broadcast Good Frame Counter Interrupt Status - txbcgfis
 * 
 * This bit is set when the txbroadcastframes_g counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                     
 * :----------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT | 0x0   | txbroadcastframes_g  < half max 
 *  ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT   | 0x1   | txbroadcastframes_g  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS
 * 
 * txbroadcastframes_g  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS
 * 
 * txbroadcastframes_g  >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : MMC Transmit Multicast Good Frame Counter Interrupt Status - txmcgfis
 * 
 * This bit is set when the txmulticastframes_g counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                     
 * :----------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT | 0x0   | txmulticastframes_g  < half max 
 *  ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT   | 0x1   | txmulticastframes_g  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS
 * 
 * txmulticastframes_g  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS
 * 
 * txmulticastframes_g  >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. - tx64octgbfis
 * 
 * This bit is set when the tx64octets_gb counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description               
 * :-------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD | 0x0   | tx64octets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END  | 0x1   | tx64octets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS
 * 
 * tx64octets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS
 * 
 * tx64octets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status - tx65t127octgbfis
 * 
 * This bit is set when the tx65to127octets_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description                    
 * :------------------------------------------------|:------|:--------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT | 0x0   | tx65to127octets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT   | 0x1   | tx65to127octets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS
 * 
 * tx65to127octets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS
 * 
 * tx65to127octets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status - tx128t255octgbfis
 * 
 * This bit is set when the tx128to255octets_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description                     
 * :-------------------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT | 0x0   | tx128to255octets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT   | 0x1   | tx128to255octets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS
 * 
 * tx128to255octets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS
 * 
 * tx128to255octets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_MSB        6
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status - tx256t511octgbfis
 * 
 * This bit is set when the tx256to511octets_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description                     
 * :-------------------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT | 0x0   | tx256to511octets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT   | 0x1   | tx256to511octets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS
 * 
 * tx256to511octets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS
 * 
 * tx256to511octets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - tx512t1023octgbfis
 * 
 * This bit is set when the tx512to1023octets_gb counter reaches half of the
 * maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description                      
 * :--------------------------------------------------|:------|:----------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT | 0x0   | tx512to1023octets_gb  < half max 
 *  ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT   | 0x1   | tx512to1023octets_gb  >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS
 * 
 * tx512to1023octets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS
 * 
 * tx512to1023octets_gb  >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - tx1024tmaxoctgbfis
 * 
 * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the
 * maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description                       
 * :--------------------------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT | 0x0   | tx1024tomaxoctets_gb  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT   | 0x1   | tx1024tomaxoctets_gb   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS
 * 
 * tx1024tomaxoctets_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS
 * 
 * tx1024tomaxoctets_gb   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : MMC Transmit Unicast Good Bad Frame Counter Interrupt Status - txucgbfis
 * 
 * This bit is set when the txunicastframes_gb counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                     
 * :-----------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT | 0x0   | txunicastframes_bb  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT   | 0x1   | txunicastframes_bb   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS
 * 
 * txunicastframes_bb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS
 * 
 * txunicastframes_bb   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : MMC Transmit Multicast Good Bad Frame Counter Interrupt Status - txmcgbfis
 * 
 * This bit is set when the txmulticastframes_gb counter reaches half of the
 * maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                       
 * :-----------------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT | 0x0   | txmulticastframes_gb  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT   | 0x1   | txmulticastframes_gb   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS
 * 
 * txmulticastframes_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS
 * 
 * txmulticastframes_gb   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_MSB        11
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET_MSK    0x00000800
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status - txbcgbfis
 * 
 * This bit is set when the txbroadcastframes_gb counter reaches half of the
 * maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                       
 * :----------------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD | 0x0   | txbroadcastframes_gb  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END  | 0x1   | txbroadcastframes_gb   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS
 * 
 * txbroadcastframes_gb  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS
 * 
 * txbroadcastframes_gb   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_MSB        12
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET_MSK    0x00001000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_CLR_MSK    0xffffefff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : MMC Transmit Underflow Error Frame Counter Interrupt Status - txuflowerfis
 * 
 * This bit is set when the txunderflowerror counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                           
 * :-------------------------------------------|:------|:---------------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD | 0x0   | txunderflowerror counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END  | 0x1   | txunderflowerror counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS
 * 
 * txunderflowerror counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS
 * 
 * txunderflowerror counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_MSB        13
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : MMC Transmit Single Collision Good Frame Counter Interrupt Status - txscolgfis
 * 
 * This bit is set when the txsinglecol_g counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                        
 * :-----------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD | 0x0   | txsinglecol_g counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END  | 0x1   | txsinglecol_g counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS
 * 
 * txsinglecol_g counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS
 * 
 * txsinglecol_g counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_MSB        14
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET_MSK    0x00004000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_CLR_MSK    0xffffbfff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : MMC Transmit Multiple Collision Good Frame Counter Interrupt Status - txmcolgfis
 * 
 * This bit is set when the txmulticol_g counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                       
 * :-----------------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD | 0x0   | txmulticol_g counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END  | 0x1   | txmulticol_g counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS
 * 
 * txmulticol_g counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS
 * 
 * txmulticol_g counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET_MSK    0x00008000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_CLR_MSK    0xffff7fff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : MMC Transmit Deferred Frame Counter Interrupt Status - txdeffis
 * 
 * This bit is set when the txdeferred counter reaches half of the maximum value or
 * the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                     
 * :---------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD | 0x0   | txdeferred counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END  | 0x1   | txdeferred counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS
 * 
 * txdeferred counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS
 * 
 * txdeferred counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : MMC Transmit Late Collision Frame Counter Interrupt Status - txlatcolfis
 * 
 * This bit is set when the txlatecol counter reaches half of the maximum value or
 * the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                    
 * :------------------------------------------|:------|:--------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD | 0x0   | txlatecol counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END  | 0x1   | txlatecol counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS
 * 
 * txlatecol counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS
 * 
 * txlatecol counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_MSB        17
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET_MSK    0x00020000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : MMC Transmit Excessive Collision Frame Counter Interrupt Status - txexcolfis
 * 
 * This bit is set when the txexcesscol counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                     
 * :-----------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD | 0x0   | txexesscol counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END  | 0x1   | txexesscol counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS
 * 
 * txexesscol counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS
 * 
 * txexesscol counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : MMC Transmit Carrier Error Frame Counter Interrupt Status - txcarerfis
 * 
 * This bit is set when the txcarriererror counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                         
 * :-----------------------------------------|:------|:-------------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD | 0x0   | txcarriererror counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END  | 0x1   | txcarriererror counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS
 * 
 * txcarriererror counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS
 * 
 * txcarriererror counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : MMC Transmit Good Octet Counter Interrupt Status - txgoctis
 * 
 * This bit is set when the txoctetcount_g counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                         
 * :---------------------------------------|:------|:-------------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD | 0x0   | txoctetcount_g counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END  | 0x1   | txoctetcount_g counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS
 * 
 * txoctetcount_g counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS
 * 
 * txoctetcount_g counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : MMC Transmit Good Frame Counter Interrupt Status - txgfrmis
 * 
 * This bit is set when the txframecount_g counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                         
 * :---------------------------------------|:------|:-------------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD | 0x0   | txframecount_g counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END  | 0x1   | txframecount_g counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS
 * 
 * txframecount_g counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS
 * 
 * txframecount_g counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : MMC Transmit Excessive Deferral Frame Counter Interrupt Status - txexdeffis
 * 
 * This bit is set when the txexcessdef counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                       
 * :-----------------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD | 0x0   | txoexcessdef counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END  | 0x1   | txoexcessdef counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS
 * 
 * txoexcessdef counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS
 * 
 * txoexcessdef counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_MSB        22
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET_MSK    0x00400000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_CLR_MSK    0xffbfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : MMC Transmit Pause Frame Counter Interrupt Status - txpausfis
 * 
 * This bit is set when the txpauseframeserror counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                             
 * :----------------------------------------|:------|:-----------------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD | 0x0   | txpauseframeserror counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END  | 0x1   | txpauseframeserror counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS
 * 
 * txpauseframeserror counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS
 * 
 * txpauseframeserror counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_MSB        23
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET_MSK    0x00800000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_CLR_MSK    0xff7fffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : MMC Transmit VLAN Good Frame Counter Interrupt Status - txvlangfis
 * 
 * This bit is set when the txvlanframes_g counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                         
 * :-----------------------------------------|:------|:-------------------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD | 0x0   | txvlanframes_g counter  < half max  
 *  ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END  | 0x1   | txvlanframes_g counter   >= half max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS
 * 
 * txvlanframes_g counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS
 * 
 * txvlanframes_g counter   >= half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : MMC Transmit Oversize Good Frame Counter Interrupt Status - txosizegfis
 * 
 * This bit is set when the txoversize_g counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET(value) (((value) << 25) & 0x02000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MMC_TX_INT.
 */
struct ALT_EMAC_GMAC_MMC_TX_INT_s
{
    const uint32_t  txgboctis          :  1;  /* MMC Transmit Good Bad Octet Counter Interrupt Status */
    const uint32_t  txgbfrmis          :  1;  /* MMC Transmit Good Bad Frame Counter Interrupt Status */
    const uint32_t  txbcgfis           :  1;  /* MMC Transmit Broadcast Good Frame Counter Interrupt Status */
    const uint32_t  txmcgfis           :  1;  /* MMC Transmit Multicast Good Frame Counter Interrupt Status */
    const uint32_t  tx64octgbfis       :  1;  /* MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. */
    const uint32_t  tx65t127octgbfis   :  1;  /* MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  tx128t255octgbfis  :  1;  /* MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  tx256t511octgbfis  :  1;  /* MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  tx512t1023octgbfis :  1;  /* MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  tx1024tmaxoctgbfis :  1;  /* MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status */
    const uint32_t  txucgbfis          :  1;  /* MMC Transmit Unicast Good Bad Frame Counter Interrupt Status */
    const uint32_t  txmcgbfis          :  1;  /* MMC Transmit Multicast Good Bad Frame Counter Interrupt Status */
    const uint32_t  txbcgbfis          :  1;  /* MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status */
    const uint32_t  txuflowerfis       :  1;  /* MMC Transmit Underflow Error Frame Counter Interrupt Status */
    const uint32_t  txscolgfis         :  1;  /* MMC Transmit Single Collision Good Frame Counter Interrupt Status */
    const uint32_t  txmcolgfis         :  1;  /* MMC Transmit Multiple Collision Good Frame Counter Interrupt Status */
    const uint32_t  txdeffis           :  1;  /* MMC Transmit Deferred Frame Counter Interrupt Status */
    const uint32_t  txlatcolfis        :  1;  /* MMC Transmit Late Collision Frame Counter Interrupt Status */
    const uint32_t  txexcolfis         :  1;  /* MMC Transmit Excessive Collision Frame Counter Interrupt Status */
    const uint32_t  txcarerfis         :  1;  /* MMC Transmit Carrier Error Frame Counter Interrupt Status */
    const uint32_t  txgoctis           :  1;  /* MMC Transmit Good Octet Counter Interrupt Status */
    const uint32_t  txgfrmis           :  1;  /* MMC Transmit Good Frame Counter Interrupt Status */
    const uint32_t  txexdeffis         :  1;  /* MMC Transmit Excessive Deferral Frame Counter Interrupt Status */
    const uint32_t  txpausfis          :  1;  /* MMC Transmit Pause Frame Counter Interrupt Status */
    const uint32_t  txvlangfis         :  1;  /* MMC Transmit VLAN Good Frame Counter Interrupt Status */
    const uint32_t  txosizegfis        :  1;  /* MMC Transmit Oversize Good Frame Counter Interrupt Status */
    uint32_t                           :  6;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MMC_TX_INT. */
typedef volatile struct ALT_EMAC_GMAC_MMC_TX_INT_s  ALT_EMAC_GMAC_MMC_TX_INT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MMC_TX_INT register from the beginning of the component. */
#define ALT_EMAC_GMAC_MMC_TX_INT_OFST        0x108
/* The address of the ALT_EMAC_GMAC_MMC_TX_INT register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_OFST))

/*
 * Register : Register 67 (MMC Receive Interrupt Mask Register) - MMC_Receive_Interrupt_Mask
 * 
 * The MMC Receive Interrupt Mask register maintains the masks for the interrupts
 * generated when the receive statistic counters reach half of their maximum value,
 * or maximum value. This register is 32-bits wide.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                                            
 * :--------|:-------|:------|:------------------------------------------------------------------------
 *  [0]     | RW     | 0x0   | MMC Receive Good Bad Frame Counter Interrupt Mask                      
 *  [1]     | RW     | 0x0   | MMC Receive Good Bad Octet Counter Interrupt Mask                      
 *  [2]     | RW     | 0x0   | MMC Receive Good Octet Counter Interrupt Mask                          
 *  [3]     | RW     | 0x0   | MMC Receive Broadcast Good Frame Counter Interrupt Mask                
 *  [4]     | RW     | 0x0   | MMC Receive Multicast Good Frame Counter Interrupt Mask                
 *  [5]     | RW     | 0x0   | MMC Receive CRC Error Frame Counter Interrupt Mask                     
 *  [6]     | RW     | 0x0   | MMC Receive Alignment Error Frame Counter Interrupt Mask               
 *  [7]     | RW     | 0x0   | MMC Receive Runt Frame Counter Interrupt Mask                          
 *  [8]     | RW     | 0x0   | MMC Receive Jabber Error Frame Counter Interrupt Mask                  
 *  [9]     | RW     | 0x0   | MMC Receive Undersize Good Frame Counter Interrupt Mask                
 *  [10]    | RW     | 0x0   | MMC Receive Oversize Good Frame Counter Interrupt Mask                 
 *  [11]    | RW     | 0x0   | MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask             
 *  [12]    | RW     | 0x0   | MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask      
 *  [13]    | RW     | 0x0   | MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask     
 *  [14]    | RW     | 0x0   | MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask     
 *  [15]    | RW     | 0x0   | MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask    
 *  [16]    | RW     | 0x0   | MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
 *  [17]    | RW     | 0x0   | MMC Receive Unicast Good Frame Counter Interrupt Mask                  
 *  [18]    | RW     | 0x0   | MMC Receive Length Error Frame Counter Interrupt Mask                  
 *  [19]    | RW     | 0x0   | MMC Receive Out Of Range Error Frame Counter Interrupt  Mask           
 *  [20]    | RW     | 0x0   | MMC Receive Pause Frame Counter Interrupt Mask                         
 *  [21]    | RW     | 0x0   | MMC Receive FIFO Overflow Frame Counter Interrupt Mask                 
 *  [22]    | RW     | 0x0   | MMC Receive VLAN Good Bad Frame Counter Interrupt Mask                 
 *  [23]    | RW     | 0x0   | MMC Receive Watchdog Error Frame Counter Interrupt Mask                
 *  [24]    | RW     | 0x0   | MMC Receive Error Frame Counter Interrupt Mask                         
 *  [25]    | RW     | 0x0   | MMC Receive Control Frame Counter Interrupt Mask                       
 *  [31:26] | ???    | 0x0   | *UNDEFINED*                                                            
 * 
 */
/*
 * Field : MMC Receive Good Bad Frame Counter Interrupt Mask - rxgbfrmim
 * 
 * Setting this bit masks the interrupt when the rxframecount_gb counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : MMC Receive Good Bad Octet Counter Interrupt Mask - rxgboctim
 * 
 * Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : MMC Receive Good Octet Counter Interrupt Mask - rxgoctim
 * 
 * Setting this bit masks the interrupt when the rxoctetcount_g counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : MMC Receive Broadcast Good Frame Counter Interrupt Mask - rxbcgfim
 * 
 * Setting this bit masks the interrupt when the rxbroadcastframes_g counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : MMC Receive Multicast Good Frame Counter Interrupt Mask - rxmcgfim
 * 
 * Setting this bit masks the interrupt when the rxmulticastframes_g counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : MMC Receive CRC Error Frame Counter Interrupt Mask - rxcrcerfim
 * 
 * Setting this bit masks the interrupt when the rxcrcerror counter reaches half of
 * the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description               
 * :--------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : MMC Receive Alignment Error Frame Counter Interrupt Mask - rxalgnerfim
 * 
 * Setting this bit masks the interrupt when the rxalignmenterror counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description               
 * :---------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_MSB        6
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : MMC Receive Runt Frame Counter Interrupt Mask - rxruntfim
 * 
 * Setting this bit masks the interrupt when the rxrunterror counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : MMC Receive Jabber Error Frame Counter Interrupt Mask - rxjaberfim
 * 
 * Setting this bit masks the interrupt when the rxjabbererror counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description               
 * :--------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : MMC Receive Undersize Good Frame Counter Interrupt Mask - rxusizegfim
 * 
 * Setting this bit masks the interrupt when the rxundersize_g counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description               
 * :---------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : MMC Receive Oversize Good Frame Counter Interrupt Mask - rxosizegfim
 * 
 * Setting this bit masks the interrupt when the rxoversize_g counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description               
 * :---------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask - rx64octgbfim
 * 
 * Setting this bit masks the interrupt when the rx64octets_gb counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                | Value | Description               
 * :----------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_MSB        11
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET_MSK    0x00000800
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - rx65t127octgbfim
 * 
 * Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                    | Value | Description               
 * :--------------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_MSB        12
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET_MSK    0x00001000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_CLR_MSK    0xffffefff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - rx128t255octgbfim
 * 
 * Setting this bit masks the interrupt when the rx128to255octets_gb counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                     | Value | Description               
 * :---------------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_MSB        13
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - rx256t511octgbfim
 * 
 * Setting this bit masks the interrupt when the rx256to511octets_gb counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                     | Value | Description               
 * :---------------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_MSB        14
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET_MSK    0x00004000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_CLR_MSK    0xffffbfff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - rx512t1023octgbfim
 * 
 * Setting this bit masks the interrupt when the rx512to1023octets_gb counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                      | Value | Description               
 * :----------------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET_MSK    0x00008000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_CLR_MSK    0xffff7fff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - rx1024tmaxoctgbfim
 * 
 * Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                      | Value | Description               
 * :----------------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : MMC Receive Unicast Good Frame Counter Interrupt Mask - rxucgfim
 * 
 * Setting this bit masks the interrupt when the rxunicastframes_g counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_MSB        17
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET_MSK    0x00020000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_CLR_MSK    0xfffdffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : MMC Receive Length Error Frame Counter Interrupt Mask - rxlenerfim
 * 
 * Setting this bit masks the interrupt when the rxlengtherror counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description               
 * :--------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : MMC Receive Out Of Range Error Frame Counter Interrupt  Mask - rxorangefim
 * 
 * Setting this bit masks the interrupt when the rxoutofrangetype counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description               
 * :---------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : MMC Receive Pause Frame Counter Interrupt Mask - rxpausfim
 * 
 * Setting this bit masks the interrupt when the rxpauseframes counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : MMC Receive FIFO Overflow Frame Counter Interrupt Mask - rxfovfim
 * 
 * Setting this bit masks the interrupt when the rxfifooverflow counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : MMC Receive VLAN Good Bad Frame Counter Interrupt Mask - rxvlangbfim
 * 
 * Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description               
 * :---------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_MSB        22
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET_MSK    0x00400000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_CLR_MSK    0xffbfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : MMC Receive Watchdog Error Frame Counter Interrupt Mask - rxwdogfim
 * 
 * Setting this bit masks the interrupt when the rxwatchdog counter reaches half of
 * the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_MSB        23
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET_MSK    0x00800000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_CLR_MSK    0xff7fffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : MMC Receive Error Frame Counter Interrupt Mask - rxrcverrfim
 * 
 * Setting this bit masks the interrupt when the rxrcverror error counter reaches
 * half the maximum value, and also when it reaches the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description               
 * :---------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : MMC Receive Control Frame Counter Interrupt Mask - rxctrlfim
 * 
 * Setting this bit masks the interrupt when the rxctrlframes counter reaches half
 * the maximum value, and also when it reaches the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET(value) (((value) << 25) & 0x02000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MMC_RX_INT_MSK.
 */
struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s
{
    uint32_t  rxgbfrmim          :  1;  /* MMC Receive Good Bad Frame Counter Interrupt Mask */
    uint32_t  rxgboctim          :  1;  /* MMC Receive Good Bad Octet Counter Interrupt Mask */
    uint32_t  rxgoctim           :  1;  /* MMC Receive Good Octet Counter Interrupt Mask */
    uint32_t  rxbcgfim           :  1;  /* MMC Receive Broadcast Good Frame Counter Interrupt Mask */
    uint32_t  rxmcgfim           :  1;  /* MMC Receive Multicast Good Frame Counter Interrupt Mask */
    uint32_t  rxcrcerfim         :  1;  /* MMC Receive CRC Error Frame Counter Interrupt Mask */
    uint32_t  rxalgnerfim        :  1;  /* MMC Receive Alignment Error Frame Counter Interrupt Mask */
    uint32_t  rxruntfim          :  1;  /* MMC Receive Runt Frame Counter Interrupt Mask */
    uint32_t  rxjaberfim         :  1;  /* MMC Receive Jabber Error Frame Counter Interrupt Mask */
    uint32_t  rxusizegfim        :  1;  /* MMC Receive Undersize Good Frame Counter Interrupt Mask */
    uint32_t  rxosizegfim        :  1;  /* MMC Receive Oversize Good Frame Counter Interrupt Mask */
    uint32_t  rx64octgbfim       :  1;  /* MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  rx65t127octgbfim   :  1;  /* MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  rx128t255octgbfim  :  1;  /* MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  rx256t511octgbfim  :  1;  /* MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  rx512t1023octgbfim :  1;  /* MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  rx1024tmaxoctgbfim :  1;  /* MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  rxucgfim           :  1;  /* MMC Receive Unicast Good Frame Counter Interrupt Mask */
    uint32_t  rxlenerfim         :  1;  /* MMC Receive Length Error Frame Counter Interrupt Mask */
    uint32_t  rxorangefim        :  1;  /* MMC Receive Out Of Range Error Frame Counter Interrupt  Mask */
    uint32_t  rxpausfim          :  1;  /* MMC Receive Pause Frame Counter Interrupt Mask */
    uint32_t  rxfovfim           :  1;  /* MMC Receive FIFO Overflow Frame Counter Interrupt Mask */
    uint32_t  rxvlangbfim        :  1;  /* MMC Receive VLAN Good Bad Frame Counter Interrupt Mask */
    uint32_t  rxwdogfim          :  1;  /* MMC Receive Watchdog Error Frame Counter Interrupt Mask */
    uint32_t  rxrcverrfim        :  1;  /* MMC Receive Error Frame Counter Interrupt Mask */
    uint32_t  rxctrlfim          :  1;  /* MMC Receive Control Frame Counter Interrupt Mask */
    uint32_t                     :  6;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MMC_RX_INT_MSK. */
typedef volatile struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s  ALT_EMAC_GMAC_MMC_RX_INT_MSK_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register from the beginning of the component. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST        0x10c
/* The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register. */
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST))

/*
 * Register : Register 68 (MMC Transmit Interrupt Mask Register) - MMC_Transmit_Interrupt_Mask
 * 
 * The MMC Transmit Interrupt Mask register maintains the masks for the interrupts
 * generated when the transmit statistic counters reach half of their maximum value
 * or maximum value. This register is 32-bits wide.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                                             
 * :--------|:-------|:------|:-------------------------------------------------------------------------
 *  [0]     | RW     | 0x0   | MMC Transmit Good Bad Octet Counter Interrupt Mask                      
 *  [1]     | RW     | 0x0   | MMC Transmit Good Bad Frame Counter Interrupt Mask                      
 *  [2]     | RW     | 0x0   | MMC Transmit Broadcast Good Frame Counter Interrupt Mask                
 *  [3]     | RW     | 0x0   | MMC Transmit Multicast Good Frame Counter Interrupt Mask                
 *  [4]     | RW     | 0x0   | MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask             
 *  [5]     | RW     | 0x0   | MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask      
 *  [6]     | RW     | 0x0   | MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask     
 *  [7]     | RW     | 0x0   | MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask     
 *  [8]     | RW     | 0x0   | MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask    
 *  [9]     | RW     | 0x0   | MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
 *  [10]    | RW     | 0x0   | MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask              
 *  [11]    | RW     | 0x0   | MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask            
 *  [12]    | RW     | 0x0   | MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask            
 *  [13]    | RW     | 0x0   | MMC Transmit Underflow Error Frame Counter Interrupt Mask               
 *  [14]    | RW     | 0x0   | MMC Transmit Single Collision Good Frame Counter Interrupt Mask         
 *  [15]    | RW     | 0x0   | MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask       
 *  [16]    | RW     | 0x0   | MMC Transmit Deferred Frame Counter Interrupt Mask                      
 *  [17]    | RW     | 0x0   | MMC Transmit Late Collision Frame Counter Interrupt Mask                
 *  [18]    | RW     | 0x0   | MMC Transmit Excessive Collision Frame Counter Interrupt Mask           
 *  [19]    | RW     | 0x0   | MMC Transmit Carrier Error Frame Counter Interrupt Mask                 
 *  [20]    | RW     | 0x0   | MMC Transmit Good Octet Counter Interrupt Mask                          
 *  [21]    | RW     | 0x0   | MMC Transmit Good Frame Counter Interrupt Mask                          
 *  [22]    | RW     | 0x0   | MMC Transmit Excessive Deferral Frame Counter Interrupt Mask            
 *  [23]    | RW     | 0x0   | MMC Transmit Pause Frame Counter Interrupt Mask                         
 *  [24]    | RW     | 0x0   | MMC Transmit VLAN Good Frame Counter Interrupt Mask                     
 *  [25]    | RW     | 0x0   | MMC Transmit Oversize Good Frame Counter Interrupt Mask                 
 *  [31:26] | ???    | 0x0   | *UNDEFINED*                                                             
 * 
 */
/*
 * Field : MMC Transmit Good Bad Octet Counter Interrupt Mask - txgboctim
 * 
 * Setting this bit masks the interrupt when the txoctetcount_gb counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : MMC Transmit Good Bad Frame Counter Interrupt Mask - txgbfrmim
 * 
 * Setting this bit masks the interrupt when the txframecount_gb counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : MMC Transmit Broadcast Good Frame Counter Interrupt Mask - txbcgfim
 * 
 * Setting this bit masks the interrupt when the txbroadcastframes_g counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : MMC Transmit Multicast Good Frame Counter Interrupt Mask - txmcgfim
 * 
 * Setting this bit masks the interrupt when the txmulticastframes_g counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask - tx64octgbfim
 * 
 * Setting this bit masks the interrupt when the tx64octets_gb counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                | Value | Description               
 * :----------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - tx65t127octgbfim
 * 
 * Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                    | Value | Description               
 * :--------------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - tx128t255octgbfim
 * 
 * Setting this bit masks the interrupt when the tx128to255octets_gb counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                     | Value | Description               
 * :---------------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_MSB        6
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - tx256t511octgbfim
 * 
 * Setting this bit masks the interrupt when the tx256to511octets_gb counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                     | Value | Description               
 * :---------------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - tx512t1023octgbfim
 * 
 * Setting this bit masks the interrupt when the tx512to1023octets_gb counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                      | Value | Description               
 * :----------------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - tx1024tmaxoctgbfim
 * 
 * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                      | Value | Description               
 * :----------------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask - txucgbfim
 * 
 * Setting this bit masks the interrupt when the txunicastframes_gb counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask - txmcgbfim
 * 
 * Setting this bit masks the interrupt when the txmulticastframes_gb counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_MSB        11
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET_MSK    0x00000800
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask - txbcgbfim
 * 
 * Setting this bit masks the interrupt when the txbroadcastframes_gb counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_MSB        12
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET_MSK    0x00001000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_CLR_MSK    0xffffefff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : MMC Transmit Underflow Error Frame Counter Interrupt Mask - txuflowerfim
 * 
 * Setting this bit masks the interrupt when the txunderflowerror counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                | Value | Description               
 * :----------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_MSB        13
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : MMC Transmit Single Collision Good Frame Counter Interrupt Mask - txscolgfim
 * 
 * Setting this bit masks the interrupt when the txsinglecol_g counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description               
 * :--------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_MSB        14
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET_MSK    0x00004000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_CLR_MSK    0xffffbfff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask - txmcolgfim
 * 
 * Setting this bit masks the interrupt when the txmulticol_g counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description               
 * :--------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET_MSK    0x00008000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_CLR_MSK    0xffff7fff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : MMC Transmit Deferred Frame Counter Interrupt Mask - txdeffim
 * 
 * Setting this bit masks the interrupt when the txdeferred counter reaches half of
 * the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : MMC Transmit Late Collision Frame Counter Interrupt Mask - txlatcolfim
 * 
 * Setting this bit masks the interrupt when the txlatecol counter reaches half of
 * the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description               
 * :---------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_MSB        17
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET_MSK    0x00020000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_CLR_MSK    0xfffdffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : MMC Transmit Excessive Collision Frame Counter Interrupt Mask - txexcolfim
 * 
 * Setting this bit masks the interrupt when the txexcesscol counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description               
 * :--------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : MMC Transmit Carrier Error Frame Counter Interrupt Mask - txcarerfim
 * 
 * Setting this bit masks the interrupt when the txcarriererror counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description               
 * :--------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : MMC Transmit Good Octet Counter Interrupt Mask - txgoctim
 * 
 * Setting this bit masks the interrupt when the txoctetcount_g counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : MMC Transmit Good Frame Counter Interrupt Mask - txgfrmim
 * 
 * Setting this bit masks the interrupt when the txframecount_g counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description               
 * :------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : MMC Transmit Excessive Deferral Frame Counter Interrupt Mask - txexdeffim
 * 
 * Setting this bit masks the interrupt when the txexcessdef counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description               
 * :--------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_MSB        22
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET_MSK    0x00400000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_CLR_MSK    0xffbfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : MMC Transmit Pause Frame Counter Interrupt Mask - txpausfim
 * 
 * Setting this bit masks the interrupt when the txpauseframes counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description               
 * :-------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_MSB        23
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET_MSK    0x00800000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_CLR_MSK    0xff7fffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : MMC Transmit VLAN Good Frame Counter Interrupt Mask - txvlangfim
 * 
 * Setting this bit masks the interrupt when the txvlanframes_g counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description               
 * :--------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : MMC Transmit Oversize Good Frame Counter Interrupt Mask - txosizegfim
 * 
 * Setting this bit masks the interrupt when the txoversize_g counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description               
 * :---------------------------------------------------|:------|:---------------------------
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR | 0x0   | counter < half max        
 *  ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR   | 0x1   | counter >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM
 * 
 * counter < half max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM
 * 
 * counter >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET(value) (((value) << 25) & 0x02000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MMC_TX_INT_MSK.
 */
struct ALT_EMAC_GMAC_MMC_TX_INT_MSK_s
{
    uint32_t  txgboctim          :  1;  /* MMC Transmit Good Bad Octet Counter Interrupt Mask */
    uint32_t  txgbfrmim          :  1;  /* MMC Transmit Good Bad Frame Counter Interrupt Mask */
    uint32_t  txbcgfim           :  1;  /* MMC Transmit Broadcast Good Frame Counter Interrupt Mask */
    uint32_t  txmcgfim           :  1;  /* MMC Transmit Multicast Good Frame Counter Interrupt Mask */
    uint32_t  tx64octgbfim       :  1;  /* MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  tx65t127octgbfim   :  1;  /* MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  tx128t255octgbfim  :  1;  /* MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  tx256t511octgbfim  :  1;  /* MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  tx512t1023octgbfim :  1;  /* MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  tx1024tmaxoctgbfim :  1;  /* MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask */
    uint32_t  txucgbfim          :  1;  /* MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask */
    uint32_t  txmcgbfim          :  1;  /* MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask */
    uint32_t  txbcgbfim          :  1;  /* MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask */
    uint32_t  txuflowerfim       :  1;  /* MMC Transmit Underflow Error Frame Counter Interrupt Mask */
    uint32_t  txscolgfim         :  1;  /* MMC Transmit Single Collision Good Frame Counter Interrupt Mask */
    uint32_t  txmcolgfim         :  1;  /* MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask */
    uint32_t  txdeffim           :  1;  /* MMC Transmit Deferred Frame Counter Interrupt Mask */
    uint32_t  txlatcolfim        :  1;  /* MMC Transmit Late Collision Frame Counter Interrupt Mask */
    uint32_t  txexcolfim         :  1;  /* MMC Transmit Excessive Collision Frame Counter Interrupt Mask */
    uint32_t  txcarerfim         :  1;  /* MMC Transmit Carrier Error Frame Counter Interrupt Mask */
    uint32_t  txgoctim           :  1;  /* MMC Transmit Good Octet Counter Interrupt Mask */
    uint32_t  txgfrmim           :  1;  /* MMC Transmit Good Frame Counter Interrupt Mask */
    uint32_t  txexdeffim         :  1;  /* MMC Transmit Excessive Deferral Frame Counter Interrupt Mask */
    uint32_t  txpausfim          :  1;  /* MMC Transmit Pause Frame Counter Interrupt Mask */
    uint32_t  txvlangfim         :  1;  /* MMC Transmit VLAN Good Frame Counter Interrupt Mask */
    uint32_t  txosizegfim        :  1;  /* MMC Transmit Oversize Good Frame Counter Interrupt Mask */
    uint32_t                     :  6;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MMC_TX_INT_MSK. */
typedef volatile struct ALT_EMAC_GMAC_MMC_TX_INT_MSK_s  ALT_EMAC_GMAC_MMC_TX_INT_MSK_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register from the beginning of the component. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST        0x110
/* The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register. */
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST))

/*
 * Register : Register 69 (txoctetcount_gb Register) - txoctetcount_gb
 * 
 * Number of bytes transmitted, exclusive of preamble and retried bytes, in good
 * and bad frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description    
 * :-------|:-------|:------|:----------------
 *  [31:0] | R      | 0x0   | txoctetcount_gb
 * 
 */
/*
 * Field : txoctetcount_gb - cnt
 * 
 * Number of bytes transmitted, exclusive of preamble and retried bytes, in good
 * and bad frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXOCTETCOUNT_GB.
 */
struct ALT_EMAC_GMAC_TXOCTETCOUNT_GB_s
{
    const uint32_t  cnt : 32;  /* txoctetcount_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXOCTETCOUNT_GB. */
typedef volatile struct ALT_EMAC_GMAC_TXOCTETCOUNT_GB_s  ALT_EMAC_GMAC_TXOCTETCOUNT_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_OFST        0x114
/* The address of the ALT_EMAC_GMAC_TXOCTETCOUNT_GB register. */
#define ALT_EMAC_GMAC_TXOCTETCOUNT_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOCTETCOUNT_GB_OFST))

/*
 * Register : Register 70 (txframecount_gb Register) - txframecount_gb
 * 
 * Number of good and bad frames transmitted, exclusive of retried frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description    
 * :-------|:-------|:------|:----------------
 *  [31:0] | R      | 0x0   | txframecount_gb
 * 
 */
/*
 * Field : txframecount_gb - cnt
 * 
 * Number of good and bad frames transmitted, exclusive of retried frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_GB.
 */
struct ALT_EMAC_GMAC_TXFRMCOUNT_GB_s
{
    const uint32_t  cnt : 32;  /* txframecount_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_GB. */
typedef volatile struct ALT_EMAC_GMAC_TXFRMCOUNT_GB_s  ALT_EMAC_GMAC_TXFRMCOUNT_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_OFST        0x118
/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_GB register. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXFRMCOUNT_GB_OFST))

/*
 * Register : Register 71 (txbroadcastframes_g Register) - txbroadcastframes_g
 * 
 * Number of good broadcast frames transmitted
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | txbroadcastframes_g
 * 
 */
/*
 * Field : txbroadcastframes_g - cnt
 * 
 * Number of good broadcast frames transmitted
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_G.
 */
struct ALT_EMAC_GMAC_TXBCASTFRMS_G_s
{
    const uint32_t  cnt : 32;  /* txbroadcastframes_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_G. */
typedef volatile struct ALT_EMAC_GMAC_TXBCASTFRMS_G_s  ALT_EMAC_GMAC_TXBCASTFRMS_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXBCASTFRMS_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_G_OFST        0x11c
/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_G register. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXBCASTFRMS_G_OFST))

/*
 * Register : Register 72 (txmulticastframes_g Register) - txmulticastframes_g
 * 
 * Number of good multicast frames transmitted
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | txmulticastframes_g
 * 
 */
/*
 * Field : txmulticastframes_g - cnt
 * 
 * Number of good multicast frames transmitted
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_G.
 */
struct ALT_EMAC_GMAC_TXMCASTFRMS_G_s
{
    const uint32_t  cnt : 32;  /* txmulticastframes_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_G. */
typedef volatile struct ALT_EMAC_GMAC_TXMCASTFRMS_G_s  ALT_EMAC_GMAC_TXMCASTFRMS_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXMCASTFRMS_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_G_OFST        0x120
/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_G register. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMCASTFRMS_G_OFST))

/*
 * Register : Register 73 (tx64octets_gb Register) - tx64octets_gb
 * 
 * Number of good and bad frames transmitted with length 64 bytes, exclusive of
 * preamble and retried frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description  
 * :-------|:-------|:------|:--------------
 *  [31:0] | R      | 0x0   | tx64octets_gb
 * 
 */
/*
 * Field : tx64octets_gb - cnt
 * 
 * Number of good and bad frames transmitted with length 64 bytes, exclusive of
 * preamble and retried frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TX64OCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TX64OCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TX64OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TX64OCTETS_GB.
 */
struct ALT_EMAC_GMAC_TX64OCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* tx64octets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TX64OCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_TX64OCTETS_GB_s  ALT_EMAC_GMAC_TX64OCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TX64OCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TX64OCTETS_GB_OFST        0x124
/* The address of the ALT_EMAC_GMAC_TX64OCTETS_GB register. */
#define ALT_EMAC_GMAC_TX64OCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX64OCTETS_GB_OFST))

/*
 * Register : Register 74 (tx65to127octets_gb Register) - tx65to127octets_gb
 * 
 * Number of good and bad frames transmitted with length between 65 and 127
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description       
 * :-------|:-------|:------|:-------------------
 *  [31:0] | R      | 0x0   | tx65to127octets_gb
 * 
 */
/*
 * Field : tx65to127octets_gb - cnt
 * 
 * Number of good and bad frames transmitted with length between 65 and 127
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TX65TO127OCTETS_GB.
 */
struct ALT_EMAC_GMAC_TX65TO127OCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* tx65to127octets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TX65TO127OCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_TX65TO127OCTETS_GB_s  ALT_EMAC_GMAC_TX65TO127OCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_OFST        0x128
/* The address of the ALT_EMAC_GMAC_TX65TO127OCTETS_GB register. */
#define ALT_EMAC_GMAC_TX65TO127OCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX65TO127OCTETS_GB_OFST))

/*
 * Register : Register 75 (tx128to255octets_gb Register) - tx128to255octets_gb
 * 
 * Number of good and bad frames transmitted with length between 128 and 255
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | tx128to255octets_gb
 * 
 */
/*
 * Field : tx128to255octets_gb - cnt
 * 
 * Number of good and bad frames transmitted with length between 128 and 255
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TX128TO255OCTETS_GB.
 */
struct ALT_EMAC_GMAC_TX128TO255OCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* tx128to255octets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TX128TO255OCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_TX128TO255OCTETS_GB_s  ALT_EMAC_GMAC_TX128TO255OCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_OFST        0x12c
/* The address of the ALT_EMAC_GMAC_TX128TO255OCTETS_GB register. */
#define ALT_EMAC_GMAC_TX128TO255OCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX128TO255OCTETS_GB_OFST))

/*
 * Register : Register 76 (tx256to511octets_gb Register) - tx256to511octets_gb
 * 
 * Number of good and bad frames transmitted with length between 256 and 511
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | tx256to511octets_gb
 * 
 */
/*
 * Field : tx256to511octets_gb - cnt
 * 
 * Number of good and bad frames transmitted with length between 256 and 511
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TX256TO511OCTETS_GB.
 */
struct ALT_EMAC_GMAC_TX256TO511OCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* tx256to511octets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TX256TO511OCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_TX256TO511OCTETS_GB_s  ALT_EMAC_GMAC_TX256TO511OCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_OFST        0x130
/* The address of the ALT_EMAC_GMAC_TX256TO511OCTETS_GB register. */
#define ALT_EMAC_GMAC_TX256TO511OCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX256TO511OCTETS_GB_OFST))

/*
 * Register : Register 77 (tx512to1023octets_gb Register) - tx512to1023octets_gb
 * 
 * Number of good and bad frames transmitted with length between 512 and 1,023
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description         
 * :-------|:-------|:------|:---------------------
 *  [31:0] | R      | 0x0   | tx512to1023octets_gb
 * 
 */
/*
 * Field : tx512to1023octets_gb - cnt
 * 
 * Number of good and bad frames transmitted with length between 512 and 1,023
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TX512TO1023OCTETS_GB.
 */
struct ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* tx512to1023octets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TX512TO1023OCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_s  ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_OFST        0x134
/* The address of the ALT_EMAC_GMAC_TX512TO1023OCTETS_GB register. */
#define ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_OFST))

/*
 * Register : Register 78 (tx1024tomaxoctets_gb Register) - tx1024tomaxoctets_gb
 * 
 * Number of good and bad frames transmitted with length between 1,024 and maxsize
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description         
 * :-------|:-------|:------|:---------------------
 *  [31:0] | R      | 0x0   | tx1024tomaxoctets_gb
 * 
 */
/*
 * Field : tx1024tomaxoctets_gb - cnt
 * 
 * Number of good and bad frames transmitted with length between 1,024 and maxsize
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB.
 */
struct ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* tx1024tomaxoctets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_s  ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_OFST        0x138
/* The address of the ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB register. */
#define ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_OFST))

/*
 * Register : Register 79 (txunicastframes_gb Register) - txunicastframes_gb
 * 
 * Number of good and bad unicast frames transmitted
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description       
 * :-------|:-------|:------|:-------------------
 *  [31:0] | R      | 0x0   | txunicastframes_gb
 * 
 */
/*
 * Field : txunicastframes_gb - cnt
 * 
 * Number of good and bad unicast frames transmitted
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXUNICASTFRMS_GB.
 */
struct ALT_EMAC_GMAC_TXUNICASTFRMS_GB_s
{
    const uint32_t  cnt : 32;  /* txunicastframes_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXUNICASTFRMS_GB. */
typedef volatile struct ALT_EMAC_GMAC_TXUNICASTFRMS_GB_s  ALT_EMAC_GMAC_TXUNICASTFRMS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_OFST        0x13c
/* The address of the ALT_EMAC_GMAC_TXUNICASTFRMS_GB register. */
#define ALT_EMAC_GMAC_TXUNICASTFRMS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXUNICASTFRMS_GB_OFST))

/*
 * Register : Register 80 (txmulticastframes_gb Register) - txmulticastframes_gb
 * 
 * Number of good and bad multicast frames transmitted
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description         
 * :-------|:-------|:------|:---------------------
 *  [31:0] | R      | 0x0   | txmulticastframes_gb
 * 
 */
/*
 * Field : txmulticastframes_gb - cnt
 * 
 * Number of good and bad multicast frames transmitted
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_GB.
 */
struct ALT_EMAC_GMAC_TXMCASTFRMS_GB_s
{
    const uint32_t  cnt : 32;  /* txmulticastframes_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXMCASTFRMS_GB. */
typedef volatile struct ALT_EMAC_GMAC_TXMCASTFRMS_GB_s  ALT_EMAC_GMAC_TXMCASTFRMS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_OFST        0x140
/* The address of the ALT_EMAC_GMAC_TXMCASTFRMS_GB register. */
#define ALT_EMAC_GMAC_TXMCASTFRMS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMCASTFRMS_GB_OFST))

/*
 * Register : Register 81 (txbroadcastframes_gb Register) - txbroadcastframes_gb
 * 
 * Number of good and bad broadcast frames transmitted
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description         
 * :-------|:-------|:------|:---------------------
 *  [31:0] | R      | 0x0   | txbroadcastframes_gb
 * 
 */
/*
 * Field : txbroadcastframes_gb - cnt
 * 
 * Number of good and bad broadcast frames transmitted
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_GB.
 */
struct ALT_EMAC_GMAC_TXBCASTFRMS_GB_s
{
    const uint32_t  cnt : 32;  /* txbroadcastframes_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXBCASTFRMS_GB. */
typedef volatile struct ALT_EMAC_GMAC_TXBCASTFRMS_GB_s  ALT_EMAC_GMAC_TXBCASTFRMS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_OFST        0x144
/* The address of the ALT_EMAC_GMAC_TXBCASTFRMS_GB register. */
#define ALT_EMAC_GMAC_TXBCASTFRMS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXBCASTFRMS_GB_OFST))

/*
 * Register : Register 82 (txunderflowerror Register) - txunderflowerror
 * 
 * Number of frames aborted due to frame underflow error
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | R      | 0x0   | txunderflowerror
 * 
 */
/*
 * Field : txunderflowerror - cnt
 * 
 * Number of frames aborted due to frame underflow error
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value. */
#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value. */
#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field. */
#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXUNDERFLOWERROR.
 */
struct ALT_EMAC_GMAC_TXUNDERFLOWERROR_s
{
    const uint32_t  cnt : 32;  /* txunderflowerror */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXUNDERFLOWERROR. */
typedef volatile struct ALT_EMAC_GMAC_TXUNDERFLOWERROR_s  ALT_EMAC_GMAC_TXUNDERFLOWERROR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_OFST        0x148
/* The address of the ALT_EMAC_GMAC_TXUNDERFLOWERROR register. */
#define ALT_EMAC_GMAC_TXUNDERFLOWERROR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXUNDERFLOWERROR_OFST))

/*
 * Register : Register 83 (txsinglecol_g Register) - txsinglecol_g
 * 
 * Number of successfully transmitted frames after a single collision in Half-
 * duplex mode
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description  
 * :-------|:-------|:------|:--------------
 *  [31:0] | R      | 0x0   | txsinglecol_g
 * 
 */
/*
 * Field : txsinglecol_g - cnt
 * 
 * Number of successfully transmitted frames after a single collision in Half-
 * duplex mode
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field. */
#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXSINGLECOL_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXSINGLECOL_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXSINGLECOL_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXSINGLECOL_G.
 */
struct ALT_EMAC_GMAC_TXSINGLECOL_G_s
{
    const uint32_t  cnt : 32;  /* txsinglecol_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXSINGLECOL_G. */
typedef volatile struct ALT_EMAC_GMAC_TXSINGLECOL_G_s  ALT_EMAC_GMAC_TXSINGLECOL_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXSINGLECOL_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXSINGLECOL_G_OFST        0x14c
/* The address of the ALT_EMAC_GMAC_TXSINGLECOL_G register. */
#define ALT_EMAC_GMAC_TXSINGLECOL_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXSINGLECOL_G_OFST))

/*
 * Register : Register 84 (txmulticol_g Register) - txmulticol_g
 * 
 * Number of successfully transmitted frames after more than a single collision in
 * Half-duplex mode
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description 
 * :-------|:-------|:------|:-------------
 *  [31:0] | R      | 0x0   | txmulticol_g
 * 
 */
/*
 * Field : txmulticol_g - cnt
 * 
 * Number of successfully transmitted frames after more than a single collision in
 * Half-duplex mode
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field. */
#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXMULTICOL_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXMULTICOL_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXMULTICOL_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXMULTICOL_G.
 */
struct ALT_EMAC_GMAC_TXMULTICOL_G_s
{
    const uint32_t  cnt : 32;  /* txmulticol_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXMULTICOL_G. */
typedef volatile struct ALT_EMAC_GMAC_TXMULTICOL_G_s  ALT_EMAC_GMAC_TXMULTICOL_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXMULTICOL_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXMULTICOL_G_OFST        0x150
/* The address of the ALT_EMAC_GMAC_TXMULTICOL_G register. */
#define ALT_EMAC_GMAC_TXMULTICOL_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXMULTICOL_G_OFST))

/*
 * Register : Register 85 (txdeferred Register) - txdeferred
 * 
 * Number of successfully transmitted frames after a deferral in Halfduplex mode
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | R      | 0x0   | txdeferred 
 * 
 */
/*
 * Field : txdeferred - cnt
 * 
 * Number of successfully transmitted frames after a deferral in Halfduplex mode
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
#define ALT_EMAC_GMAC_TXDEFERRED_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
#define ALT_EMAC_GMAC_TXDEFERRED_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
#define ALT_EMAC_GMAC_TXDEFERRED_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXDEFERRED_CNT register field value. */
#define ALT_EMAC_GMAC_TXDEFERRED_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXDEFERRED_CNT register field value. */
#define ALT_EMAC_GMAC_TXDEFERRED_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXDEFERRED_CNT register field. */
#define ALT_EMAC_GMAC_TXDEFERRED_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXDEFERRED_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXDEFERRED_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXDEFERRED_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXDEFERRED_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXDEFERRED.
 */
struct ALT_EMAC_GMAC_TXDEFERRED_s
{
    const uint32_t  cnt : 32;  /* txdeferred */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXDEFERRED. */
typedef volatile struct ALT_EMAC_GMAC_TXDEFERRED_s  ALT_EMAC_GMAC_TXDEFERRED_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXDEFERRED register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXDEFERRED_OFST        0x154
/* The address of the ALT_EMAC_GMAC_TXDEFERRED register. */
#define ALT_EMAC_GMAC_TXDEFERRED_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXDEFERRED_OFST))

/*
 * Register : Register 86 (txlatecol Register) - txlatecol
 * 
 * Number of frames aborted due to late collision error
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | R      | 0x0   | txlatecol  
 * 
 */
/*
 * Field : txlatecol - cnt
 * 
 * Number of frames aborted due to late collision error
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
#define ALT_EMAC_GMAC_TXLATECOL_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
#define ALT_EMAC_GMAC_TXLATECOL_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
#define ALT_EMAC_GMAC_TXLATECOL_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXLATECOL_CNT register field value. */
#define ALT_EMAC_GMAC_TXLATECOL_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXLATECOL_CNT register field value. */
#define ALT_EMAC_GMAC_TXLATECOL_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXLATECOL_CNT register field. */
#define ALT_EMAC_GMAC_TXLATECOL_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXLATECOL_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXLATECOL_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXLATECOL_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXLATECOL_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXLATECOL.
 */
struct ALT_EMAC_GMAC_TXLATECOL_s
{
    const uint32_t  cnt : 32;  /* txlatecol */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXLATECOL. */
typedef volatile struct ALT_EMAC_GMAC_TXLATECOL_s  ALT_EMAC_GMAC_TXLATECOL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXLATECOL register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXLATECOL_OFST        0x158
/* The address of the ALT_EMAC_GMAC_TXLATECOL register. */
#define ALT_EMAC_GMAC_TXLATECOL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXLATECOL_OFST))

/*
 * Register : Register 87 (txexesscol Register) - txexesscol
 * 
 * Number of frames aborted due to excessive (16) collision errors
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | R      | 0x0   | txexesscol 
 * 
 */
/*
 * Field : txexesscol - cnt
 * 
 * Number of frames aborted due to excessive (16) collision errors
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value. */
#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value. */
#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXEXESSCOL_CNT register field. */
#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXEXESSCOL_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXEXESSCOL_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXEXESSCOL_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXEXESSCOL.
 */
struct ALT_EMAC_GMAC_TXEXESSCOL_s
{
    const uint32_t  cnt : 32;  /* txexesscol */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXEXESSCOL. */
typedef volatile struct ALT_EMAC_GMAC_TXEXESSCOL_s  ALT_EMAC_GMAC_TXEXESSCOL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXEXESSCOL register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXEXESSCOL_OFST        0x15c
/* The address of the ALT_EMAC_GMAC_TXEXESSCOL register. */
#define ALT_EMAC_GMAC_TXEXESSCOL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXEXESSCOL_OFST))

/*
 * Register : Register 88 (txcarriererror Register) - txcarriererr
 * 
 * Number of frames aborted due to carrier sense error (no carrier or loss of
 * carrier)
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | txcarriererror
 * 
 */
/*
 * Field : txcarriererror - cnt
 * 
 * Number of frames aborted due to carrier sense error (no carrier or loss of
 * carrier)
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value. */
#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value. */
#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXCARRIERERR_CNT register field. */
#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXCARRIERERR_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXCARRIERERR_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXCARRIERERR_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXCARRIERERR.
 */
struct ALT_EMAC_GMAC_TXCARRIERERR_s
{
    const uint32_t  cnt : 32;  /* txcarriererror */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXCARRIERERR. */
typedef volatile struct ALT_EMAC_GMAC_TXCARRIERERR_s  ALT_EMAC_GMAC_TXCARRIERERR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXCARRIERERR register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXCARRIERERR_OFST        0x160
/* The address of the ALT_EMAC_GMAC_TXCARRIERERR register. */
#define ALT_EMAC_GMAC_TXCARRIERERR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXCARRIERERR_OFST))

/*
 * Register : Register 89 (txoctetcount_g Register) - txoctetcnt
 * 
 * Number of bytes transmitted, exclusive of preamble, in good frames only
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | txoctetcount_g
 * 
 */
/*
 * Field : txoctetcount_g - txoctetcount_g
 * 
 * Number of bytes transmitted, exclusive of preamble, in good frames only
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value. */
#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value. */
#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field. */
#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G field value from a register. */
#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXOCTETCNT_TXOCTETCOUNT_G_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXOCTETCNT.
 */
struct ALT_EMAC_GMAC_TXOCTETCNT_s
{
    const uint32_t  txoctetcount_g : 32;  /* txoctetcount_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXOCTETCNT. */
typedef volatile struct ALT_EMAC_GMAC_TXOCTETCNT_s  ALT_EMAC_GMAC_TXOCTETCNT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXOCTETCNT register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXOCTETCNT_OFST        0x164
/* The address of the ALT_EMAC_GMAC_TXOCTETCNT register. */
#define ALT_EMAC_GMAC_TXOCTETCNT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOCTETCNT_OFST))

/*
 * Register : Register 90 (txframecount_g Register) - txframecount_g
 * 
 * Number of good frames transmitted
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | txframecount_g
 * 
 */
/*
 * Field : txframecount_g - cnt
 * 
 * Number of good frames transmitted
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_G.
 */
struct ALT_EMAC_GMAC_TXFRMCOUNT_G_s
{
    const uint32_t  cnt : 32;  /* txframecount_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXFRMCOUNT_G. */
typedef volatile struct ALT_EMAC_GMAC_TXFRMCOUNT_G_s  ALT_EMAC_GMAC_TXFRMCOUNT_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXFRMCOUNT_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_G_OFST        0x168
/* The address of the ALT_EMAC_GMAC_TXFRMCOUNT_G register. */
#define ALT_EMAC_GMAC_TXFRMCOUNT_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXFRMCOUNT_G_OFST))

/*
 * Register : Register 91 (txexcessdef Register) - txexcessdef
 * 
 * Number of frames aborted due to excessive deferral error (deferred for more than
 * two max-sized frame times)
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | R      | 0x0   | txexcessdef
 * 
 */
/*
 * Field : txexcessdef - cnt
 * 
 * Number of frames aborted due to excessive deferral error (deferred for more than
 * two max-sized frame times)
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value. */
#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value. */
#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field. */
#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXEXCESSDEF_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXEXCESSDEF_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXEXCESSDEF_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXEXCESSDEF.
 */
struct ALT_EMAC_GMAC_TXEXCESSDEF_s
{
    const uint32_t  cnt : 32;  /* txexcessdef */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXEXCESSDEF. */
typedef volatile struct ALT_EMAC_GMAC_TXEXCESSDEF_s  ALT_EMAC_GMAC_TXEXCESSDEF_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXEXCESSDEF register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXEXCESSDEF_OFST        0x16c
/* The address of the ALT_EMAC_GMAC_TXEXCESSDEF register. */
#define ALT_EMAC_GMAC_TXEXCESSDEF_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXEXCESSDEF_OFST))

/*
 * Register : Register 92 (txpauseframes Register) - txpauseframes
 * 
 * Number of good PAUSE frames transmitted
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description  
 * :-------|:-------|:------|:--------------
 *  [31:0] | R      | 0x0   | txpauseframes
 * 
 */
/*
 * Field : txpauseframes - cnt
 * 
 * Number of good PAUSE frames transmitted
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value. */
#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value. */
#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field. */
#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXPAUSEFRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXPAUSEFRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXPAUSEFRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXPAUSEFRMS.
 */
struct ALT_EMAC_GMAC_TXPAUSEFRMS_s
{
    const uint32_t  cnt : 32;  /* txpauseframes */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXPAUSEFRMS. */
typedef volatile struct ALT_EMAC_GMAC_TXPAUSEFRMS_s  ALT_EMAC_GMAC_TXPAUSEFRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXPAUSEFRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXPAUSEFRMS_OFST        0x170
/* The address of the ALT_EMAC_GMAC_TXPAUSEFRMS register. */
#define ALT_EMAC_GMAC_TXPAUSEFRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXPAUSEFRMS_OFST))

/*
 * Register : Register 93 (txvlanframes_g Register) - txvlanframes_g
 * 
 * Number of good VLAN frames transmitted, exclusive of retried frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | txvlanframes_g
 * 
 */
/*
 * Field : txvlanframes_g - cnt
 * 
 * Number of good VLAN frames transmitted, exclusive of retried frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXVLANFRMS_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXVLANFRMS_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXVLANFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXVLANFRMS_G.
 */
struct ALT_EMAC_GMAC_TXVLANFRMS_G_s
{
    const uint32_t  cnt : 32;  /* txvlanframes_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXVLANFRMS_G. */
typedef volatile struct ALT_EMAC_GMAC_TXVLANFRMS_G_s  ALT_EMAC_GMAC_TXVLANFRMS_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXVLANFRMS_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXVLANFRMS_G_OFST        0x174
/* The address of the ALT_EMAC_GMAC_TXVLANFRMS_G register. */
#define ALT_EMAC_GMAC_TXVLANFRMS_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXVLANFRMS_G_OFST))

/*
 * Register : Register 94 (txoversize_g Register) - txoversize_g
 * 
 * Number of good and bad frames received
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description 
 * :-------|:-------|:------|:-------------
 *  [31:0] | R      | 0x0   | txoversize_g
 * 
 */
/*
 * Field : txoversize_g - cnt
 * 
 * Number of good and bad frames received
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value. */
#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TXOVERSIZE_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TXOVERSIZE_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TXOVERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TXOVERSIZE_G.
 */
struct ALT_EMAC_GMAC_TXOVERSIZE_G_s
{
    const uint32_t  cnt : 32;  /* txoversize_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TXOVERSIZE_G. */
typedef volatile struct ALT_EMAC_GMAC_TXOVERSIZE_G_s  ALT_EMAC_GMAC_TXOVERSIZE_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TXOVERSIZE_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_TXOVERSIZE_G_OFST        0x178
/* The address of the ALT_EMAC_GMAC_TXOVERSIZE_G register. */
#define ALT_EMAC_GMAC_TXOVERSIZE_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TXOVERSIZE_G_OFST))

/*
 * Register : Register 95 (rxframecount_gb Register) - rxframecount_gb
 * 
 * Number of good and bad frames received
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                    
 * :-------|:-------|:------|:--------------------------------
 *  [31:0] | R      | 0x0   | ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT
 * 
 */
/*
 * Field : cnt
 * 
 * Number of good and bad frames received
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXFRMCOUNT_GB.
 */
struct ALT_EMAC_GMAC_RXFRMCOUNT_GB_s
{
    const uint32_t  cnt : 32;  /* ALT_EMAC_GMAC_RXFRMCOUNT_GB_CNT */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXFRMCOUNT_GB. */
typedef volatile struct ALT_EMAC_GMAC_RXFRMCOUNT_GB_s  ALT_EMAC_GMAC_RXFRMCOUNT_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_OFST        0x180
/* The address of the ALT_EMAC_GMAC_RXFRMCOUNT_GB register. */
#define ALT_EMAC_GMAC_RXFRMCOUNT_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXFRMCOUNT_GB_OFST))

/*
 * Register : Register 97 (rxoctetcount_gb Register) - rxoctetcount_gb
 * 
 * Number of bytes received, exclusive of preamble, in good and bad frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description    
 * :-------|:-------|:------|:----------------
 *  [31:0] | R      | 0x0   | rxoctetcount_gb
 * 
 */
/*
 * Field : rxoctetcount_gb - cnt
 * 
 * Number of bytes received, exclusive of preamble, in good and bad frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_GB.
 */
struct ALT_EMAC_GMAC_RXOCTETCOUNT_GB_s
{
    const uint32_t  cnt : 32;  /* rxoctetcount_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_GB. */
typedef volatile struct ALT_EMAC_GMAC_RXOCTETCOUNT_GB_s  ALT_EMAC_GMAC_RXOCTETCOUNT_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_OFST        0x184
/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_GB register. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOCTETCOUNT_GB_OFST))

/*
 * Register : Register 98 (rxoctetcount_g Register) - rxoctetcount_g
 * 
 * Number of bytes received, exclusive of preamble, only in good frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | rxoctetcount_g
 * 
 */
/*
 * Field : rxoctetcount_g - cnt
 * 
 * Number of bytes received, exclusive of preamble, only in good frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_G.
 */
struct ALT_EMAC_GMAC_RXOCTETCOUNT_G_s
{
    const uint32_t  cnt : 32;  /* rxoctetcount_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXOCTETCOUNT_G. */
typedef volatile struct ALT_EMAC_GMAC_RXOCTETCOUNT_G_s  ALT_EMAC_GMAC_RXOCTETCOUNT_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_OFST        0x188
/* The address of the ALT_EMAC_GMAC_RXOCTETCOUNT_G register. */
#define ALT_EMAC_GMAC_RXOCTETCOUNT_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOCTETCOUNT_G_OFST))

/*
 * Register : Register 99 (rxbroadcastframes_g Register) - rxbroadcastframes_g
 * 
 * Number of good broadcast frames received
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | rxbroadcastframes_g
 * 
 */
/*
 * Field : rxbroadcastframes_g - cnt
 * 
 * Number of good broadcast frames received
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXBCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXBCASTFRMS_G.
 */
struct ALT_EMAC_GMAC_RXBCASTFRMS_G_s
{
    const uint32_t  cnt : 32;  /* rxbroadcastframes_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXBCASTFRMS_G. */
typedef volatile struct ALT_EMAC_GMAC_RXBCASTFRMS_G_s  ALT_EMAC_GMAC_RXBCASTFRMS_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXBCASTFRMS_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXBCASTFRMS_G_OFST        0x18c
/* The address of the ALT_EMAC_GMAC_RXBCASTFRMS_G register. */
#define ALT_EMAC_GMAC_RXBCASTFRMS_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXBCASTFRMS_G_OFST))

/*
 * Register : Register 100 (rxmulticastframes_g Register) - rxmulticastframes_g
 * 
 * Number of good multicast frames received
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | rxmulticastframes_g
 * 
 */
/*
 * Field : rxmulticastframes_g - cnt
 * 
 * Number of good multicast frames received
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXMCASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXMCASTFRMS_G.
 */
struct ALT_EMAC_GMAC_RXMCASTFRMS_G_s
{
    const uint32_t  cnt : 32;  /* rxmulticastframes_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXMCASTFRMS_G. */
typedef volatile struct ALT_EMAC_GMAC_RXMCASTFRMS_G_s  ALT_EMAC_GMAC_RXMCASTFRMS_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXMCASTFRMS_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXMCASTFRMS_G_OFST        0x190
/* The address of the ALT_EMAC_GMAC_RXMCASTFRMS_G register. */
#define ALT_EMAC_GMAC_RXMCASTFRMS_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXMCASTFRMS_G_OFST))

/*
 * Register : Register 101 (rxcrcerror Register) - rxcrcerror
 * 
 * Number of frames received with CRC error
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | R      | 0x0   | rxcrcerror 
 * 
 */
/*
 * Field : rxcrcerror - cnt
 * 
 * Number of frames received with CRC error
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXCRCERROR_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXCRCERROR_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXCRCERROR_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXCRCERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXCRCERROR_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXCRCERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXCRCERROR_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXCRCERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXCRCERROR_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXCRCERROR_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXCRCERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXCRCERROR_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXCRCERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXCRCERROR.
 */
struct ALT_EMAC_GMAC_RXCRCERROR_s
{
    const uint32_t  cnt : 32;  /* rxcrcerror */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXCRCERROR. */
typedef volatile struct ALT_EMAC_GMAC_RXCRCERROR_s  ALT_EMAC_GMAC_RXCRCERROR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXCRCERROR register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXCRCERROR_OFST        0x194
/* The address of the ALT_EMAC_GMAC_RXCRCERROR register. */
#define ALT_EMAC_GMAC_RXCRCERROR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXCRCERROR_OFST))

/*
 * Register : Register 102 (rxalignmenterror Register) - rxalignmenterror
 * 
 * Number of frames received with alignment (dribble) error. Valid only in 10/100
 * mode
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | R      | 0x0   | rxalignmenterror
 * 
 */
/*
 * Field : rxalignmenterror - cnt
 * 
 * Number of frames received with alignment (dribble) error. Valid only in 10/100
 * mode
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXALIGNMENTERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXALIGNMENTERROR.
 */
struct ALT_EMAC_GMAC_RXALIGNMENTERROR_s
{
    const uint32_t  cnt : 32;  /* rxalignmenterror */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXALIGNMENTERROR. */
typedef volatile struct ALT_EMAC_GMAC_RXALIGNMENTERROR_s  ALT_EMAC_GMAC_RXALIGNMENTERROR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXALIGNMENTERROR register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXALIGNMENTERROR_OFST        0x198
/* The address of the ALT_EMAC_GMAC_RXALIGNMENTERROR register. */
#define ALT_EMAC_GMAC_RXALIGNMENTERROR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXALIGNMENTERROR_OFST))

/*
 * Register : Register 103 (rxrunterror Register) - rxrunterror
 * 
 * Number of frames received with runt (<64 bytes and CRC error) error
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | R      | 0x0   | rxrunterror
 * 
 */
/*
 * Field : rxrunterror - cnt
 * 
 * Number of frames received with runt (<64 bytes and CRC error) error
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXRUNTERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXRUNTERROR_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXRUNTERROR_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXRUNTERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXRUNTERROR.
 */
struct ALT_EMAC_GMAC_RXRUNTERROR_s
{
    const uint32_t  cnt : 32;  /* rxrunterror */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXRUNTERROR. */
typedef volatile struct ALT_EMAC_GMAC_RXRUNTERROR_s  ALT_EMAC_GMAC_RXRUNTERROR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXRUNTERROR register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXRUNTERROR_OFST        0x19c
/* The address of the ALT_EMAC_GMAC_RXRUNTERROR register. */
#define ALT_EMAC_GMAC_RXRUNTERROR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXRUNTERROR_OFST))

/*
 * Register : Register 104 (rxjabbererror Register) - rxjabbererror
 * 
 * Number of giant frames received with length (including CRC) greater than 1,518
 * bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is
 * enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged)
 * are considered as giant frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description  
 * :-------|:-------|:------|:--------------
 *  [31:0] | R      | 0x0   | rxjabbererror
 * 
 */
/*
 * Field : rxjabbererror - cnt
 * 
 * Number of giant frames received with length (including CRC) greater than 1,518
 * bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is
 * enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged)
 * are considered as giant frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXJABBERERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXJABBERERROR_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXJABBERERROR_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXJABBERERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXJABBERERROR.
 */
struct ALT_EMAC_GMAC_RXJABBERERROR_s
{
    const uint32_t  cnt : 32;  /* rxjabbererror */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXJABBERERROR. */
typedef volatile struct ALT_EMAC_GMAC_RXJABBERERROR_s  ALT_EMAC_GMAC_RXJABBERERROR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXJABBERERROR register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXJABBERERROR_OFST        0x1a0
/* The address of the ALT_EMAC_GMAC_RXJABBERERROR register. */
#define ALT_EMAC_GMAC_RXJABBERERROR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXJABBERERROR_OFST))

/*
 * Register : Register 105 (rxundersize_g Register) - rxundersize_g
 * 
 * Number of frames received with length less than 64 bytes, without any errors
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description  
 * :-------|:-------|:------|:--------------
 *  [31:0] | R      | 0x0   | rxundersize_g
 * 
 */
/*
 * Field : rxundersize_g - cnt
 * 
 * Number of frames received with length less than 64 bytes, without any errors
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXUNDERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXUNDERSIZE_G.
 */
struct ALT_EMAC_GMAC_RXUNDERSIZE_G_s
{
    const uint32_t  cnt : 32;  /* rxundersize_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXUNDERSIZE_G. */
typedef volatile struct ALT_EMAC_GMAC_RXUNDERSIZE_G_s  ALT_EMAC_GMAC_RXUNDERSIZE_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXUNDERSIZE_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXUNDERSIZE_G_OFST        0x1a4
/* The address of the ALT_EMAC_GMAC_RXUNDERSIZE_G register. */
#define ALT_EMAC_GMAC_RXUNDERSIZE_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUNDERSIZE_G_OFST))

/*
 * Register : Register 106 (rxoversize_g Register) - rxoversize_g
 * 
 * Number of frames received with length greater than the maxsize (1,518 or 1,522
 * for VLAN tagged frames), without errors
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description 
 * :-------|:-------|:------|:-------------
 *  [31:0] | R      | 0x0   | rxoversize_g
 * 
 */
/*
 * Field : rxoversize_g - cnt
 * 
 * Number of frames received with length greater than the maxsize (1,518 or 1,522
 * for VLAN tagged frames), without errors
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field. */
#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXOVERSIZE_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXOVERSIZE_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXOVERSIZE_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXOVERSIZE_G.
 */
struct ALT_EMAC_GMAC_RXOVERSIZE_G_s
{
    const uint32_t  cnt : 32;  /* rxoversize_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXOVERSIZE_G. */
typedef volatile struct ALT_EMAC_GMAC_RXOVERSIZE_G_s  ALT_EMAC_GMAC_RXOVERSIZE_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXOVERSIZE_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXOVERSIZE_G_OFST        0x1a8
/* The address of the ALT_EMAC_GMAC_RXOVERSIZE_G register. */
#define ALT_EMAC_GMAC_RXOVERSIZE_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOVERSIZE_G_OFST))

/*
 * Register : Register 107 (rx64octets_gb Register) - rx64octets_gb
 * 
 * Number of good and bad frames received with length 64 bytes, exclusive of
 * preamble
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description  
 * :-------|:-------|:------|:--------------
 *  [31:0] | R      | 0x0   | rx64octets_gb
 * 
 */
/*
 * Field : rx64octets_gb - cnt
 * 
 * Number of good and bad frames received with length 64 bytes, exclusive of
 * preamble
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RX64OCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RX64OCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RX64OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RX64OCTETS_GB.
 */
struct ALT_EMAC_GMAC_RX64OCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* rx64octets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RX64OCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_RX64OCTETS_GB_s  ALT_EMAC_GMAC_RX64OCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RX64OCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_RX64OCTETS_GB_OFST        0x1ac
/* The address of the ALT_EMAC_GMAC_RX64OCTETS_GB register. */
#define ALT_EMAC_GMAC_RX64OCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX64OCTETS_GB_OFST))

/*
 * Register : Register 108 (rx65to127octets_gb Register) - rx65to127octets_gb
 * 
 * Number of good and bad frames received with length between 65 and 127
 * (inclusive) bytes, exclusive of preamble
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description       
 * :-------|:-------|:------|:-------------------
 *  [31:0] | R      | 0x0   | rx65to127octets_gb
 * 
 */
/*
 * Field : rx65to127octets_gb - cnt
 * 
 * Number of good and bad frames received with length between 65 and 127
 * (inclusive) bytes, exclusive of preamble
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RX65TO127OCTETS_GB.
 */
struct ALT_EMAC_GMAC_RX65TO127OCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* rx65to127octets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RX65TO127OCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_RX65TO127OCTETS_GB_s  ALT_EMAC_GMAC_RX65TO127OCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_OFST        0x1b0
/* The address of the ALT_EMAC_GMAC_RX65TO127OCTETS_GB register. */
#define ALT_EMAC_GMAC_RX65TO127OCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX65TO127OCTETS_GB_OFST))

/*
 * Register : Register 109 (rx128to255octets_gb Register) - rx128to255octets_gb
 * 
 * Number of good and bad frames received with length between 128 and 255
 * (inclusive) bytes, exclusive of preamble
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | rx128to255octets_gb
 * 
 */
/*
 * Field : rx128to255octets_gb - cnt
 * 
 * Number of good and bad frames received with length between 128 and 255
 * (inclusive) bytes, exclusive of preamble
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RX128TO255OCTETS_GB.
 */
struct ALT_EMAC_GMAC_RX128TO255OCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* rx128to255octets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RX128TO255OCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_RX128TO255OCTETS_GB_s  ALT_EMAC_GMAC_RX128TO255OCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_OFST        0x1b4
/* The address of the ALT_EMAC_GMAC_RX128TO255OCTETS_GB register. */
#define ALT_EMAC_GMAC_RX128TO255OCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX128TO255OCTETS_GB_OFST))

/*
 * Register : Register 110 (rx256to511octets_gb Register) - rx256to511octets_gb
 * 
 * Number of good and bad frames received with length between 256 and 511
 * (inclusive) bytes, exclusive of preamble
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | rx256to511octets_gb
 * 
 */
/*
 * Field : rx256to511octets_gb - cnt
 * 
 * Number of good and bad frames received with length between 256 and 511
 * (inclusive) bytes, exclusive of preamble
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RX256TO511OCTETS_GB.
 */
struct ALT_EMAC_GMAC_RX256TO511OCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* rx256to511octets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RX256TO511OCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_RX256TO511OCTETS_GB_s  ALT_EMAC_GMAC_RX256TO511OCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_OFST        0x1b8
/* The address of the ALT_EMAC_GMAC_RX256TO511OCTETS_GB register. */
#define ALT_EMAC_GMAC_RX256TO511OCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX256TO511OCTETS_GB_OFST))

/*
 * Register : Register 111 (rx512to1023octets_gb Register) - rx512to1023octets_gb
 * 
 * Number of good and bad frames received with length between 512 and 1,023
 * (inclusive) bytes, exclusive of preamble
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description         
 * :-------|:-------|:------|:---------------------
 *  [31:0] | R      | 0x0   | rx512to1023octets_gb
 * 
 */
/*
 * Field : rx512to1023octets_gb - cnt
 * 
 * Number of good and bad frames received with length between 512 and 1,023
 * (inclusive) bytes, exclusive of preamble
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RX512TO1023OCTETS_GB.
 */
struct ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* rx512to1023octets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RX512TO1023OCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_s  ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_OFST        0x1bc
/* The address of the ALT_EMAC_GMAC_RX512TO1023OCTETS_GB register. */
#define ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_OFST))

/*
 * Register : Register 112 (rx1024tomaxoctets_gb Register) - rx1024tomaxoctets_gb
 * 
 * Number of good and bad frames received with length between 1,024 and maxsize
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description         
 * :-------|:-------|:------|:---------------------
 *  [31:0] | R      | 0x0   | rx1024tomaxoctets_gb
 * 
 */
/*
 * Field : rx1024tomaxoctets_gb - cnt
 * 
 * Number of good and bad frames received with length between 1,024 and maxsize
 * (inclusive) bytes, exclusive of preamble and retried frames
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB.
 */
struct ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_s
{
    const uint32_t  cnt : 32;  /* rx1024tomaxoctets_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB. */
typedef volatile struct ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_s  ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_OFST        0x1c0
/* The address of the ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB register. */
#define ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_OFST))

/*
 * Register : Register 113 (rxunicastframes_g Register) - rxunicastframes_g
 * 
 * Number of good unicast frames received
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description      
 * :-------|:-------|:------|:------------------
 *  [31:0] | R      | 0x0   | rxunicastframes_g
 * 
 */
/*
 * Field : rxunicastframes_g - cnt
 * 
 * Number of good unicast frames received
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXUNICASTFRMS_G.
 */
struct ALT_EMAC_GMAC_RXUNICASTFRMS_G_s
{
    const uint32_t  cnt : 32;  /* rxunicastframes_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXUNICASTFRMS_G. */
typedef volatile struct ALT_EMAC_GMAC_RXUNICASTFRMS_G_s  ALT_EMAC_GMAC_RXUNICASTFRMS_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_OFST        0x1c4
/* The address of the ALT_EMAC_GMAC_RXUNICASTFRMS_G register. */
#define ALT_EMAC_GMAC_RXUNICASTFRMS_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUNICASTFRMS_G_OFST))

/*
 * Register : Register 114 (rxlengtherror Register) - rxlengtherror
 * 
 * Number of frames received with length error (length type field not equal to
 * frame size), for all frames with valid length field
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description  
 * :-------|:-------|:------|:--------------
 *  [31:0] | R      | 0x0   | rxlengtherror
 * 
 */
/*
 * Field : rxlengtherror - cnt
 * 
 * Number of frames received with length error (length type field not equal to
 * frame size), for all frames with valid length field
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXLENERROR_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXLENERROR_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXLENERROR_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXLENERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXLENERROR_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXLENERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXLENERROR_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXLENERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXLENERROR_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXLENERROR_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXLENERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXLENERROR_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXLENERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXLENERROR.
 */
struct ALT_EMAC_GMAC_RXLENERROR_s
{
    const uint32_t  cnt : 32;  /* rxlengtherror */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXLENERROR. */
typedef volatile struct ALT_EMAC_GMAC_RXLENERROR_s  ALT_EMAC_GMAC_RXLENERROR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXLENERROR register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXLENERROR_OFST        0x1c8
/* The address of the ALT_EMAC_GMAC_RXLENERROR register. */
#define ALT_EMAC_GMAC_RXLENERROR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXLENERROR_OFST))

/*
 * Register : Register 115 (rxoutofrangetype Register) - rxoutofrangetype
 * 
 * Number of frames received with length field not equal to the valid frame size
 * (greater than 1,500 but less than 1,536)
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | R      | 0x0   | rxoutofrangetype
 * 
 */
/*
 * Field : rxoutofrangetype - cnt
 * 
 * Number of frames received with length field not equal to the valid frame size
 * (greater than 1,500 but less than 1,536)
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value. */
#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value. */
#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field. */
#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXOUTOFRANGETYPE.
 */
struct ALT_EMAC_GMAC_RXOUTOFRANGETYPE_s
{
    const uint32_t  cnt : 32;  /* rxoutofrangetype */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXOUTOFRANGETYPE. */
typedef volatile struct ALT_EMAC_GMAC_RXOUTOFRANGETYPE_s  ALT_EMAC_GMAC_RXOUTOFRANGETYPE_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_OFST        0x1cc
/* The address of the ALT_EMAC_GMAC_RXOUTOFRANGETYPE register. */
#define ALT_EMAC_GMAC_RXOUTOFRANGETYPE_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXOUTOFRANGETYPE_OFST))

/*
 * Register : Register 116 (rxpauseframes Register) - rxpauseframes
 * 
 * Number of good and valid PAUSE frames received
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description  
 * :-------|:-------|:------|:--------------
 *  [31:0] | R      | 0x0   | rxpauseframes
 * 
 */
/*
 * Field : rxpauseframes - cnt
 * 
 * Number of good and valid PAUSE frames received
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXPAUSEFRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXPAUSEFRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXPAUSEFRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXPAUSEFRMS.
 */
struct ALT_EMAC_GMAC_RXPAUSEFRMS_s
{
    const uint32_t  cnt : 32;  /* rxpauseframes */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXPAUSEFRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXPAUSEFRMS_s  ALT_EMAC_GMAC_RXPAUSEFRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXPAUSEFRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXPAUSEFRMS_OFST        0x1d0
/* The address of the ALT_EMAC_GMAC_RXPAUSEFRMS register. */
#define ALT_EMAC_GMAC_RXPAUSEFRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXPAUSEFRMS_OFST))

/*
 * Register : Register 117 (rxfifooverflow Register) - rxfifooverflow
 * 
 * Number of missed received frames due to FIFO overflow
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | rxfifooverflow
 * 
 */
/*
 * Field : rxfifooverflow - cnt
 * 
 * Number of missed received frames due to FIFO overflow
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value. */
#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value. */
#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXFIFOOVF_CNT register field. */
#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXFIFOOVF_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXFIFOOVF_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXFIFOOVF_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXFIFOOVF.
 */
struct ALT_EMAC_GMAC_RXFIFOOVF_s
{
    const uint32_t  cnt : 32;  /* rxfifooverflow */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXFIFOOVF. */
typedef volatile struct ALT_EMAC_GMAC_RXFIFOOVF_s  ALT_EMAC_GMAC_RXFIFOOVF_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXFIFOOVF register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXFIFOOVF_OFST        0x1d4
/* The address of the ALT_EMAC_GMAC_RXFIFOOVF register. */
#define ALT_EMAC_GMAC_RXFIFOOVF_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXFIFOOVF_OFST))

/*
 * Register : Register 118 (rxvlanframes_gb Register) - rxvlanframes_gb
 * 
 * Number of good and bad VLAN frames received
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description    
 * :-------|:-------|:------|:----------------
 *  [31:0] | R      | 0x0   | rxvlanframes_gb
 * 
 */
/*
 * Field : rxvlanframes_gb - cnt
 * 
 * Number of good and bad VLAN frames received
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value. */
#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field. */
#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXVLANFRMS_GB_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXVLANFRMS_GB.
 */
struct ALT_EMAC_GMAC_RXVLANFRMS_GB_s
{
    const uint32_t  cnt : 32;  /* rxvlanframes_gb */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXVLANFRMS_GB. */
typedef volatile struct ALT_EMAC_GMAC_RXVLANFRMS_GB_s  ALT_EMAC_GMAC_RXVLANFRMS_GB_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXVLANFRMS_GB register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXVLANFRMS_GB_OFST        0x1d8
/* The address of the ALT_EMAC_GMAC_RXVLANFRMS_GB register. */
#define ALT_EMAC_GMAC_RXVLANFRMS_GB_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXVLANFRMS_GB_OFST))

/*
 * Register : Register 119 (rxwatchdogerror Register) - rxwatchdogerror
 * 
 * Number of frames received with error due to watchdog timeout error (frames with
 * a data load larger than 2,048 bytes)
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description    
 * :-------|:-------|:------|:----------------
 *  [31:0] | R      | 0x0   | rxwatchdogerror
 * 
 */
/*
 * Field : rxwatchdogerror - cnt
 * 
 * Number of frames received with error due to watchdog timeout error (frames with
 * a data load larger than 2,048 bytes)
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXWDERROR_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXWDERROR_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXWDERROR_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXWDERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXWDERROR_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXWDERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXWDERROR_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXWDERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXWDERROR_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXWDERROR_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXWDERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXWDERROR_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXWDERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXWDERROR.
 */
struct ALT_EMAC_GMAC_RXWDERROR_s
{
    const uint32_t  cnt : 32;  /* rxwatchdogerror */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXWDERROR. */
typedef volatile struct ALT_EMAC_GMAC_RXWDERROR_s  ALT_EMAC_GMAC_RXWDERROR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXWDERROR register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXWDERROR_OFST        0x1dc
/* The address of the ALT_EMAC_GMAC_RXWDERROR register. */
#define ALT_EMAC_GMAC_RXWDERROR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXWDERROR_OFST))

/*
 * Register : Register 120 (rxrcverror Register) - rxrcverror
 * 
 * Number of frames received with Receive error or Frame Extension error on the
 * GMII or MII interface.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description
 * :-------|:-------|:------|:------------
 *  [31:0] | R      | 0x0   | rxrcverror 
 * 
 */
/*
 * Field : rxrcverror - cnt
 * 
 * Number of frames received with Receive error or Frame Extension error on the
 * GMII or MII interface.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXRCVERROR_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXRCVERROR_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXRCVERROR_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXRCVERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXRCVERROR_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXRCVERROR_CNT register field value. */
#define ALT_EMAC_GMAC_RXRCVERROR_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXRCVERROR_CNT register field. */
#define ALT_EMAC_GMAC_RXRCVERROR_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXRCVERROR_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXRCVERROR_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXRCVERROR_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXRCVERROR_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXRCVERROR.
 */
struct ALT_EMAC_GMAC_RXRCVERROR_s
{
    const uint32_t  cnt : 32;  /* rxrcverror */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXRCVERROR. */
typedef volatile struct ALT_EMAC_GMAC_RXRCVERROR_s  ALT_EMAC_GMAC_RXRCVERROR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXRCVERROR register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXRCVERROR_OFST        0x1e0
/* The address of the ALT_EMAC_GMAC_RXRCVERROR register. */
#define ALT_EMAC_GMAC_RXRCVERROR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXRCVERROR_OFST))

/*
 * Register : Register 121 (rxctrlframes_g Register) - rxctrlframes_g
 * 
 * Number of received good control frames.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | rxctrlframes_g
 * 
 */
/*
 * Field : rxctrlframes_g - cnt
 * 
 * Number of received good control frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value. */
#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field. */
#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXCTLFRMS_G_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXCTLFRMS_G_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXCTLFRMS_G_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXCTLFRMS_G.
 */
struct ALT_EMAC_GMAC_RXCTLFRMS_G_s
{
    const uint32_t  cnt : 32;  /* rxctrlframes_g */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXCTLFRMS_G. */
typedef volatile struct ALT_EMAC_GMAC_RXCTLFRMS_G_s  ALT_EMAC_GMAC_RXCTLFRMS_G_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXCTLFRMS_G register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXCTLFRMS_G_OFST        0x1e4
/* The address of the ALT_EMAC_GMAC_RXCTLFRMS_G register. */
#define ALT_EMAC_GMAC_RXCTLFRMS_G_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXCTLFRMS_G_OFST))

/*
 * Register : Register 128 (MMC Receive Checksum Offload Interrupt Mask Register) - MMC_IPC_Receive_Interrupt_Mask
 * 
 * This register maintains the mask for the interrupt generated from the receive
 * IPC statistic
 * 
 * counters.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                                        
 * :--------|:-------|:------|:--------------------------------------------------------------------
 *  [0]     | RW     | 0x0   | MMC Receive IPV4 Good Frame Counter Interrupt Mask                 
 *  [1]     | RW     | 0x0   | MMC Receive IPV4 Header Error Frame Counter Interrupt Mask         
 *  [2]     | RW     | 0x0   | MMC Receive IPV4 No Payload Frame Counter Interrupt Mask           
 *  [3]     | RW     | 0x0   | MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask           
 *  [4]     | RW     | 0x0   | MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask
 *  [5]     | RW     | 0x0   | MMC Receive IPV6 Good Frame Counter Interrupt Mask                 
 *  [6]     | RW     | 0x0   | MMC Receive IPV6 Header Error Frame Counter Interrupt Mask         
 *  [7]     | RW     | 0x0   | MMC Receive IPV6 No Payload Frame Counter Interrupt Mask           
 *  [8]     | RW     | 0x0   | MMC Receive UDP Good Frame Counter Interrupt Mask                  
 *  [9]     | RW     | 0x0   | MMC Receive UDP Error Frame Counter Interrupt Mask                 
 *  [10]    | RW     | 0x0   | MMC Receive TCP Good Frame Counter Interrupt Mask                  
 *  [11]    | RW     | 0x0   | MMC Receive TCP Error Frame Counter Interrupt Mask                 
 *  [12]    | RW     | 0x0   | MMC Receive ICMP Good Frame Counter Interrupt Mask                 
 *  [13]    | RW     | 0x0   | MMC Receive ICMP Error Frame Counter Interrupt Mask                
 *  [15:14] | ???    | 0x0   | *UNDEFINED*                                                        
 *  [16]    | RW     | 0x0   | MMC Receive IPV4 Good Octet Counter Interrupt Mask                 
 *  [17]    | RW     | 0x0   | MMC Receive IPV4 Header Error Octet Counter Interrupt Mask         
 *  [18]    | RW     | 0x0   | MMC Receive IPV4 No Payload Octet Counter Interrupt Mask           
 *  [19]    | RW     | 0x0   | MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask           
 *  [20]    | RW     | 0x0   | MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask
 *  [21]    | RW     | 0x0   | MMC Receive IPV6 Good Octet Counter Interrupt Mask                 
 *  [22]    | RW     | 0x0   | MMC Receive IPV6 Header Error Octet Counter Interrupt Mask         
 *  [23]    | RW     | 0x0   | MMC Receive IPV6 No Payload Octet Counter Interrupt Mask           
 *  [24]    | RW     | 0x0   | MMC Receive UDP Good Octet Counter Interrupt Mask                  
 *  [25]    | RW     | 0x0   | MMC Receive UDP Error Octet Counter Interrupt Mask                 
 *  [26]    | RW     | 0x0   | MMC Receive TCP Good Octet Counter Interrupt Mask                  
 *  [27]    | RW     | 0x0   | MMC Receive TCP Error Octet Counter Interrupt Mask                 
 *  [28]    | RW     | 0x0   | MMC Receive ICMP Good Octet Counter Interrupt Mask                 
 *  [29]    | RW     | 0x0   | MMC Receive ICMP Error Octet Counter Interrupt Mask                
 *  [31:30] | ???    | 0x0   | *UNDEFINED*                                                        
 * 
 */
/*
 * Field : MMC Receive IPV4 Good Frame Counter Interrupt Mask - rxipv4gfim
 * 
 * Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description                 
 * :------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - rxipv4herfim
 * 
 * Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                    | Value | Description                 
 * :--------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - rxipv4nopayfim
 * 
 * Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                      | Value | Description                 
 * :----------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - rxipv4fragfim
 * 
 * Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                     | Value | Description                 
 * :---------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - rxipv4udsblfim
 * 
 * Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                      | Value | Description                 
 * :----------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : MMC Receive IPV6 Good Frame Counter Interrupt Mask - rxipv6gfim
 * 
 * Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description                 
 * :------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - rxipv6herfim
 * 
 * Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                    | Value | Description                 
 * :--------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_MSB        6
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - rxipv6nopayfim
 * 
 * Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                      | Value | Description                 
 * :----------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : MMC Receive UDP Good Frame Counter Interrupt Mask - rxudpgfim
 * 
 * Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                 | Value | Description                 
 * :-----------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : MMC Receive UDP Error Frame Counter Interrupt Mask - rxudperfim
 * 
 * Setting this bit masks the interrupt when the rxudp_err_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description                 
 * :------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : MMC Receive TCP Good Frame Counter Interrupt Mask - rxtcpgfim
 * 
 * Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half
 * of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                 | Value | Description                 
 * :-----------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : MMC Receive TCP Error Frame Counter Interrupt Mask - rxtcperfim
 * 
 * Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description                 
 * :------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_MSB        11
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET_MSK    0x00000800
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : MMC Receive ICMP Good Frame Counter Interrupt Mask - rxicmpgfim
 * 
 * Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description                 
 * :------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_MSB        12
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET_MSK    0x00001000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_CLR_MSK    0xffffefff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : MMC Receive ICMP Error Frame Counter Interrupt Mask - rxicmperfim
 * 
 * Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                   | Value | Description                 
 * :-------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_MSB        13
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : MMC Receive IPV4 Good Octet Counter Interrupt Mask - rxipv4goim
 * 
 * Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description                 
 * :------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - rxipv4heroim
 * 
 * Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                    | Value | Description                 
 * :--------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_MSB        17
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET_MSK    0x00020000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_CLR_MSK    0xfffdffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - rxipv4nopayoim
 * 
 * Setting this bit masks the interrupt when the rxipv4_nopay_octets counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                      | Value | Description                 
 * :----------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - rxipv4fragoim
 * 
 * Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                     | Value | Description                 
 * :---------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - rxipv4udsbloim
 * 
 * Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                      | Value | Description                 
 * :----------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : MMC Receive IPV6 Good Octet Counter Interrupt Mask - rxipv6goim
 * 
 * Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description                 
 * :------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - rxipv6heroim
 * 
 * Setting this bit masks interrupt when the rxipv6_hdrerr_octets counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                    | Value | Description                 
 * :--------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_MSB        22
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET_MSK    0x00400000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_CLR_MSK    0xffbfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - rxipv6nopayoim
 * 
 * Setting this bit masks the interrupt when the rxipv6_nopay_octets counter
 * reaches half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                      | Value | Description                 
 * :----------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_MSB        23
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET_MSK    0x00800000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_CLR_MSK    0xff7fffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : MMC Receive UDP Good Octet Counter Interrupt Mask - rxudpgoim
 * 
 * Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                 | Value | Description                 
 * :-----------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : MMC Receive UDP Error Octet Counter Interrupt Mask - rxudperoim
 * 
 * Setting this bit masks the interrupt when the rxudp_err_octets counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description                 
 * :------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : MMC Receive TCP Good Octet Counter Interrupt Mask - rxtcpgoim
 * 
 * Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                 | Value | Description                 
 * :-----------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : MMC Receive TCP Error Octet Counter Interrupt Mask - rxtcperoim
 * 
 * Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description                 
 * :------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : MMC Receive ICMP Good Octet Counter Interrupt Mask - rxicmpgoim
 * 
 * Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                  | Value | Description                 
 * :------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : MMC Receive ICMP Error Octet Counter Interrupt Mask - rxicmperoim
 * 
 * Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches
 * half of the maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                   | Value | Description                 
 * :-------------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR   | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET(value) (((value) << 29) & 0x20000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK.
 */
struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s
{
    uint32_t  rxipv4gfim     :  1;  /* MMC Receive IPV4 Good Frame Counter Interrupt Mask */
    uint32_t  rxipv4herfim   :  1;  /* MMC Receive IPV4 Header Error Frame Counter Interrupt Mask */
    uint32_t  rxipv4nopayfim :  1;  /* MMC Receive IPV4 No Payload Frame Counter Interrupt Mask */
    uint32_t  rxipv4fragfim  :  1;  /* MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask */
    uint32_t  rxipv4udsblfim :  1;  /* MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask */
    uint32_t  rxipv6gfim     :  1;  /* MMC Receive IPV6 Good Frame Counter Interrupt Mask */
    uint32_t  rxipv6herfim   :  1;  /* MMC Receive IPV6 Header Error Frame Counter Interrupt Mask */
    uint32_t  rxipv6nopayfim :  1;  /* MMC Receive IPV6 No Payload Frame Counter Interrupt Mask */
    uint32_t  rxudpgfim      :  1;  /* MMC Receive UDP Good Frame Counter Interrupt Mask */
    uint32_t  rxudperfim     :  1;  /* MMC Receive UDP Error Frame Counter Interrupt Mask */
    uint32_t  rxtcpgfim      :  1;  /* MMC Receive TCP Good Frame Counter Interrupt Mask */
    uint32_t  rxtcperfim     :  1;  /* MMC Receive TCP Error Frame Counter Interrupt Mask */
    uint32_t  rxicmpgfim     :  1;  /* MMC Receive ICMP Good Frame Counter Interrupt Mask */
    uint32_t  rxicmperfim    :  1;  /* MMC Receive ICMP Error Frame Counter Interrupt Mask */
    uint32_t                 :  2;  /* *UNDEFINED* */
    uint32_t  rxipv4goim     :  1;  /* MMC Receive IPV4 Good Octet Counter Interrupt Mask */
    uint32_t  rxipv4heroim   :  1;  /* MMC Receive IPV4 Header Error Octet Counter Interrupt Mask */
    uint32_t  rxipv4nopayoim :  1;  /* MMC Receive IPV4 No Payload Octet Counter Interrupt Mask */
    uint32_t  rxipv4fragoim  :  1;  /* MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask */
    uint32_t  rxipv4udsbloim :  1;  /* MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask */
    uint32_t  rxipv6goim     :  1;  /* MMC Receive IPV6 Good Octet Counter Interrupt Mask */
    uint32_t  rxipv6heroim   :  1;  /* MMC Receive IPV6 Header Error Octet Counter Interrupt Mask */
    uint32_t  rxipv6nopayoim :  1;  /* MMC Receive IPV6 No Payload Octet Counter Interrupt Mask */
    uint32_t  rxudpgoim      :  1;  /* MMC Receive UDP Good Octet Counter Interrupt Mask */
    uint32_t  rxudperoim     :  1;  /* MMC Receive UDP Error Octet Counter Interrupt Mask */
    uint32_t  rxtcpgoim      :  1;  /* MMC Receive TCP Good Octet Counter Interrupt Mask */
    uint32_t  rxtcperoim     :  1;  /* MMC Receive TCP Error Octet Counter Interrupt Mask */
    uint32_t  rxicmpgoim     :  1;  /* MMC Receive ICMP Good Octet Counter Interrupt Mask */
    uint32_t  rxicmperoim    :  1;  /* MMC Receive ICMP Error Octet Counter Interrupt Mask */
    uint32_t                 :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK. */
typedef volatile struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register from the beginning of the component. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST        0x200
/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST))

/*
 * Register : Register 130 (MMC Receive Checksum Offload Interrupt Register) - MMC_IPC_Receive_Interrupt
 * 
 * This register maintains the interrupts generated when receive IPC statistic
 * counters reach half their maximum values (0x8000_0000 for 32-bit counter and
 * 0x8000 for 16-bit counter), and when they cross their maximum values
 * (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter
 * Stop Rollover is set, then interrupts are set but the counter remains at all-
 * ones. The MMC Receive Checksum Offload Interrupt register is 32-bits wide. When
 * the MMC IPC counter that caused the interrupt is read, its corresponding
 * interrupt bit is cleared. The counter's least-significant byte lane (bits[7:0])
 * must be read to clear the interrupt bit.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                                          
 * :--------|:-------|:------|:----------------------------------------------------------------------
 *  [0]     | R      | 0x0   | MMC Receive IPV4 Good Frame Counter Interrupt Status                 
 *  [1]     | R      | 0x0   | MMC Receive IPV4 Header Error Frame Counter Interrupt Status         
 *  [2]     | R      | 0x0   | MMC Receive IPV4 No Payload Frame Counter Interrupt Status           
 *  [3]     | R      | 0x0   | MMC Receive IPV4 Fragmented Frame Counter Interrupt Status           
 *  [4]     | R      | 0x0   | MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status
 *  [5]     | R      | 0x0   | MMC Receive IPV6 Good Frame Counter Interrupt Status                 
 *  [6]     | R      | 0x0   | MMC Receive IPV6 Header Error Frame Counter Interrupt Status         
 *  [7]     | R      | 0x0   | MMC Receive IPV6 No Payload Frame Counter Interrupt Status           
 *  [8]     | R      | 0x0   | MMC Receive UDP Good Frame Counter Interrupt Status                  
 *  [9]     | R      | 0x0   | MMC Receive UDP Error Frame Counter Interrupt Status                 
 *  [10]    | R      | 0x0   | MMC Receive TCP Good Frame Counter Interrupt Status                  
 *  [11]    | R      | 0x0   | MMC Receive TCP Error Frame Counter Interrupt Status                 
 *  [12]    | R      | 0x0   | MMC Receive ICMP Good Frame Counter Interrupt Status                 
 *  [13]    | R      | 0x0   | MMC Receive ICMP Error Frame Counter Interrupt Status                
 *  [15:14] | ???    | 0x0   | *UNDEFINED*                                                          
 *  [16]    | R      | 0x0   | MMC Receive IPV4 Good Octet Counter Interrupt Status                 
 *  [17]    | R      | 0x0   | MMC Receive IPV4 Header Error Octet Counter Interrupt Status         
 *  [18]    | R      | 0x0   | MMC Receive IPV4 No Payload Octet Counter Interrupt Status           
 *  [19]    | R      | 0x0   | MMC Receive IPV4 Fragmented Octet Counter Interrupt Status           
 *  [20]    | R      | 0x0   | MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status
 *  [21]    | R      | 0x0   | MMC Receive IPV6 Good Octet Counter Interrupt Status                 
 *  [22]    | R      | 0x0   | MMC Receive IPV6 Header Error Octet Counter Interrupt Status         
 *  [23]    | R      | 0x0   | MMC Receive IPV6 No Payload Octet Counter Interrupt Status           
 *  [24]    | R      | 0x0   | MMC Receive UDP Good Octet Counter Interrupt Status                  
 *  [25]    | R      | 0x0   | MMC Receive UDP Error Octet Counter Interrupt Status                 
 *  [26]    | R      | 0x0   | MMC Receive TCP Good Octet Counter Interrupt Status                  
 *  [27]    | R      | 0x0   | MMC Receive TCP Error Octet Counter Interrupt Status                 
 *  [28]    | R      | 0x0   | MMC Receive ICMP Good Octet Counter Interrupt Status                 
 *  [29]    | R      | 0x0   | MMC Receive ICMP Error Octet Counter Interrupt Status                
 *  [31:30] | ???    | 0x0   | *UNDEFINED*                                                          
 * 
 */
/*
 * Field : MMC Receive IPV4 Good Frame Counter Interrupt Status - rxipv4gfis
 * 
 * This bit is set when the rxipv4_gd_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                 
 * :-----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : MMC Receive IPV4 Header Error Frame Counter Interrupt Status - rxipv4herfis
 * 
 * This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description                 
 * :-------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_NOINT     0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_INTERR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : MMC Receive IPV4 No Payload Frame Counter Interrupt Status - rxipv4nopayfis
 * 
 * This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description                 
 * :---------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - rxipv4fragfis
 * 
 * This bit is set when the rxipv4_frag_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description                 
 * :--------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_NOINT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_INTERR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - rxipv4udsblfis
 * 
 * This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description                 
 * :---------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : MMC Receive IPV6 Good Frame Counter Interrupt Status - rxipv6gfis
 * 
 * This bit is set when the rxipv6_gd_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                 
 * :-----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : MMC Receive IPV6 Header Error Frame Counter Interrupt Status - rxipv6herfis
 * 
 * This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description                 
 * :-------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_NOINT     0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_INTERR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_MSB        6
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : MMC Receive IPV6 No Payload Frame Counter Interrupt Status - rxipv6nopayfis
 * 
 * This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description                 
 * :---------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : MMC Receive UDP Good Frame Counter Interrupt Status - rxudpgfis
 * 
 * This bit is set when the rxudp_gd_frms counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                 
 * :----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_NOINT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_INTERR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : MMC Receive UDP Error Frame Counter Interrupt Status - rxudperfis
 * 
 * This bit is set when the rxudp_err_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                 
 * :-----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : MMC Receive TCP Good Frame Counter Interrupt Status - rxtcpgfis
 * 
 * This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                 
 * :----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_NOINT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_INTERR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : MMC Receive TCP Error Frame Counter Interrupt Status - rxtcperfis
 * 
 * This bit is set when the rxtcp_err_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                 
 * :-----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_MSB        11
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET_MSK    0x00000800
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : MMC Receive ICMP Good Frame Counter Interrupt Status - rxicmpgfis
 * 
 * This bit is set when the rxicmp_gd_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                 
 * :-----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_MSB        12
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET_MSK    0x00001000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_CLR_MSK    0xffffefff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : MMC Receive ICMP Error Frame Counter Interrupt Status - rxicmperfis
 * 
 * This bit is set when the rxicmp_err_frms counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description                 
 * :------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_NOINT  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_INTERR 0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_MSB        13
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : MMC Receive IPV4 Good Octet Counter Interrupt Status - rxipv4gois
 * 
 * This bit is set when the rxipv4_gd_octets counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                 
 * :-----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : MMC Receive IPV4 Header Error Octet Counter Interrupt Status - rxipv4herois
 * 
 * This bit is set when the rxipv4_hdrerr_octets counter reaches half of the
 * maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description                 
 * :-------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_NOINT     0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_INTERR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_MSB        17
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET_MSK    0x00020000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_CLR_MSK    0xfffdffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : MMC Receive IPV4 No Payload Octet Counter Interrupt Status - rxipv4nopayois
 * 
 * This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description                 
 * :---------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - rxipv4fragois
 * 
 * This bit is set when the rxipv4_frag_octets counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description                 
 * :--------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_NOINT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_INTERR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - rxipv4udsblois
 * 
 * This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description                 
 * :---------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : MMC Receive IPV6 Good Octet Counter Interrupt Status - rxipv6gois
 * 
 * This bit is set when the rxipv6_gd_octets counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                 
 * :-----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : MMC Receive IPV6 Header Error Octet Counter Interrupt Status - rxipv6herois
 * 
 * This bit is set when the rxipv6_hdrerr_octets counter reaches half of the
 * maximum value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                             | Value | Description                 
 * :-------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_NOINT     0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_INTERR    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_MSB        22
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET_MSK    0x00400000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_CLR_MSK    0xffbfffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_GET(value) (((value) & 0x00400000) >> 22)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET(value) (((value) << 22) & 0x00400000)

/*
 * Field : MMC Receive IPV6 No Payload Octet Counter Interrupt Status - rxipv6nopayois
 * 
 * This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description                 
 * :---------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_MSB        23
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET_MSK    0x00800000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_CLR_MSK    0xff7fffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : MMC Receive UDP Good Octet Counter Interrupt Status - rxudpgois
 * 
 * This bit is set when the rxudp_gd_octets counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                 
 * :----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_NOINT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_INTERR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : MMC Receive UDP Error Octet Counter Interrupt Status - rxudperois
 * 
 * This bit is set when the rxudp_err_octets counter reaches half the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                 
 * :-----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : MMC Receive TCP Good Octet Counter Interrupt Status - rxtcpgois
 * 
 * This bit is set when the rxtcp_gd_octets counter reaches half the maximum value
 * or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                 
 * :----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_NOINT    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_INTERR   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : MMC Receive TCP Error Octet Counter Interrupt Status - rxtcperois
 * 
 * This bit is set when the rxtcp_err_octets counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                 
 * :-----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : MMC Receive ICMP Good Octet Counter Interrupt Status - rxicmpgois
 * 
 * This bit is set when the rxicmp_gd_octets counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                 
 * :-----------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_NOINT   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_INTERR  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : MMC Receive ICMP Error Octet Counter Interrupt Status - rxicmperois
 * 
 * This bit is set when the rxicmp_err_octets counter reaches half of the maximum
 * value or the maximum value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description                 
 * :------------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_NOINT  | 0x0   | counter  < half max         
 *  ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_INTERR | 0x1   | counter   >= half max or max
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS
 * 
 * counter  < half max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_NOINT  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS
 * 
 * counter   >= half max or max
 */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_INTERR 0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS field value from a register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET(value) (((value) << 29) & 0x20000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT.
 */
struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s
{
    const uint32_t  rxipv4gfis     :  1;  /* MMC Receive IPV4 Good Frame Counter Interrupt Status */
    const uint32_t  rxipv4herfis   :  1;  /* MMC Receive IPV4 Header Error Frame Counter Interrupt Status */
    const uint32_t  rxipv4nopayfis :  1;  /* MMC Receive IPV4 No Payload Frame Counter Interrupt Status */
    const uint32_t  rxipv4fragfis  :  1;  /* MMC Receive IPV4 Fragmented Frame Counter Interrupt Status */
    const uint32_t  rxipv4udsblfis :  1;  /* MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status */
    const uint32_t  rxipv6gfis     :  1;  /* MMC Receive IPV6 Good Frame Counter Interrupt Status */
    const uint32_t  rxipv6herfis   :  1;  /* MMC Receive IPV6 Header Error Frame Counter Interrupt Status */
    const uint32_t  rxipv6nopayfis :  1;  /* MMC Receive IPV6 No Payload Frame Counter Interrupt Status */
    const uint32_t  rxudpgfis      :  1;  /* MMC Receive UDP Good Frame Counter Interrupt Status */
    const uint32_t  rxudperfis     :  1;  /* MMC Receive UDP Error Frame Counter Interrupt Status */
    const uint32_t  rxtcpgfis      :  1;  /* MMC Receive TCP Good Frame Counter Interrupt Status */
    const uint32_t  rxtcperfis     :  1;  /* MMC Receive TCP Error Frame Counter Interrupt Status */
    const uint32_t  rxicmpgfis     :  1;  /* MMC Receive ICMP Good Frame Counter Interrupt Status */
    const uint32_t  rxicmperfis    :  1;  /* MMC Receive ICMP Error Frame Counter Interrupt Status */
    uint32_t                       :  2;  /* *UNDEFINED* */
    const uint32_t  rxipv4gois     :  1;  /* MMC Receive IPV4 Good Octet Counter Interrupt Status */
    const uint32_t  rxipv4herois   :  1;  /* MMC Receive IPV4 Header Error Octet Counter Interrupt Status */
    const uint32_t  rxipv4nopayois :  1;  /* MMC Receive IPV4 No Payload Octet Counter Interrupt Status */
    const uint32_t  rxipv4fragois  :  1;  /* MMC Receive IPV4 Fragmented Octet Counter Interrupt Status */
    const uint32_t  rxipv4udsblois :  1;  /* MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status */
    const uint32_t  rxipv6gois     :  1;  /* MMC Receive IPV6 Good Octet Counter Interrupt Status */
    const uint32_t  rxipv6herois   :  1;  /* MMC Receive IPV6 Header Error Octet Counter Interrupt Status */
    const uint32_t  rxipv6nopayois :  1;  /* MMC Receive IPV6 No Payload Octet Counter Interrupt Status */
    const uint32_t  rxudpgois      :  1;  /* MMC Receive UDP Good Octet Counter Interrupt Status */
    const uint32_t  rxudperois     :  1;  /* MMC Receive UDP Error Octet Counter Interrupt Status */
    const uint32_t  rxtcpgois      :  1;  /* MMC Receive TCP Good Octet Counter Interrupt Status */
    const uint32_t  rxtcperois     :  1;  /* MMC Receive TCP Error Octet Counter Interrupt Status */
    const uint32_t  rxicmpgois     :  1;  /* MMC Receive ICMP Good Octet Counter Interrupt Status */
    const uint32_t  rxicmperois    :  1;  /* MMC Receive ICMP Error Octet Counter Interrupt Status */
    uint32_t                       :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT. */
typedef volatile struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s  ALT_EMAC_GMAC_MMC_IPC_RX_INT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register from the beginning of the component. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST        0x208
/* The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register. */
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST))

/*
 * Register : Register 132 (rxipv4_gd_frms Register) - rxipv4_gd_frms
 * 
 * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | rxipv4_gd_frms
 * 
 */
/*
 * Field : rxipv4_gd_frms - cnt
 * 
 * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_GD_FRMS.
 */
struct ALT_EMAC_GMAC_RXIPV4_GD_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxipv4_gd_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_GD_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV4_GD_FRMS_s  ALT_EMAC_GMAC_RXIPV4_GD_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_OFST        0x210
/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_FRMS register. */
#define ALT_EMAC_GMAC_RXIPV4_GD_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_GD_FRMS_OFST))

/*
 * Register : Register 133 (rxipv4_hdrerr_frms Register) - rxipv4_hdrerr_frms
 * 
 * Number of IPv4 datagrams received with header (checksum, length, or version
 * mismatch) errors
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description       
 * :-------|:-------|:------|:-------------------
 *  [31:0] | R      | 0x0   | rxipv4_hdrerr_frms
 * 
 */
/*
 * Field : rxipv4_hdrerr_frms - cnt
 * 
 * Number of IPv4 datagrams received with header (checksum, length, or version
 * mismatch) errors
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS.
 */
struct ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxipv4_hdrerr_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_s  ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_OFST        0x214
/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS register. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_OFST))

/*
 * Register : Register 134 (rxipv4_nopay_frms Register) - rxipv4_nopay_frms
 * 
 * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP
 * payload processed by the Checksum engine
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description      
 * :-------|:-------|:------|:------------------
 *  [31:0] | R      | 0x0   | rxipv4_nopay_frms
 * 
 */
/*
 * Field : rxipv4_nopay_frms - cnt
 * 
 * Number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP
 * payload processed by the Checksum engine
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS.
 */
struct ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxipv4_nopay_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_s  ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_OFST        0x218
/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS register. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_OFST))

/*
 * Register : Register 135 (rxipv4_frag_frms Register) - rxipv4_frag_frms
 * 
 * Number of good IPv4 datagrams with fragmentation
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | R      | 0x0   | rxipv4_frag_frms
 * 
 */
/*
 * Field : rxipv4_frag_frms - cnt
 * 
 * Number of good IPv4 datagrams with fragmentation
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS.
 */
struct ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxipv4_frag_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_s  ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_OFST        0x21c
/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS register. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_OFST))

/*
 * Register : Register 136 (rxipv4_udsbl_frms Register) - rxipv4_udsbl_frms
 * 
 * Number of good IPv4 datagrams received that had a UDP payload with checksum
 * disabled
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description      
 * :-------|:-------|:------|:------------------
 *  [31:0] | R      | 0x0   | rxipv4_udsbl_frms
 * 
 */
/*
 * Field : rxipv4_udsbl_frms - cnt
 * 
 * Number of good IPv4 datagrams received that had a UDP payload with checksum
 * disabled
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS.
 */
struct ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxipv4_udsbl_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_s  ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_OFST        0x220
/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS register. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_OFST))

/*
 * Register : Register 137 (rxipv6_gd_frms Register) - rxipv6_gd_frms
 * 
 * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | rxipv6_gd_frms
 * 
 */
/*
 * Field : rxipv6_gd_frms - cnt
 * 
 * Number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_GD_FRMS.
 */
struct ALT_EMAC_GMAC_RXIPV6_GD_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxipv6_gd_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_GD_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV6_GD_FRMS_s  ALT_EMAC_GMAC_RXIPV6_GD_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_OFST        0x224
/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_FRMS register. */
#define ALT_EMAC_GMAC_RXIPV6_GD_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_GD_FRMS_OFST))

/*
 * Register : Register 138 (rxipv6_hdrerr_frms Register) - rxipv6_hdrerr_frms
 * 
 * Number of IPv6 datagrams received with header errors (length or version
 * mismatch)
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description       
 * :-------|:-------|:------|:-------------------
 *  [31:0] | R      | 0x0   | rxipv6_hdrerr_frms
 * 
 */
/*
 * Field : rxipv6_hdrerr_frms - cnt
 * 
 * Number of IPv6 datagrams received with header errors (length or version
 * mismatch)
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS.
 */
struct ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxipv6_hdrerr_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_s  ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_OFST        0x228
/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS register. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_OFST))

/*
 * Register : Register 139 (rxipv6_nopay_frms) - rxipv6_nopay_frms
 * 
 * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP
 * payload. This includes all IPv6 datagrams with fragmentation or security
 * extension headers
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description      
 * :-------|:-------|:------|:------------------
 *  [31:0] | R      | 0x0   | rxipv6_nopay_frms
 * 
 */
/*
 * Field : rxipv6_nopay_frms - cnt
 * 
 * Number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP
 * payload. This includes all IPv6 datagrams with fragmentation or security
 * extension headers
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS.
 */
struct ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxipv6_nopay_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_s  ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_OFST        0x22c
/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS register. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_OFST))

/*
 * Register : Register 140 (rxudp_gd_frms Register) - rxudp_gd_frms
 * 
 * Number of good IP datagrams with a good UDP payload. This counter is not updated
 * when the counter is incremented
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description  
 * :-------|:-------|:------|:--------------
 *  [31:0] | R      | 0x0   | rxudp_gd_frms
 * 
 */
/*
 * Field : rxudp_gd_frms - cnt
 * 
 * Number of good IP datagrams with a good UDP payload. This counter is not updated
 * when the counter is incremented
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXUDP_GD_FRMS.
 */
struct ALT_EMAC_GMAC_RXUDP_GD_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxudp_gd_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_GD_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXUDP_GD_FRMS_s  ALT_EMAC_GMAC_RXUDP_GD_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_OFST        0x230
/* The address of the ALT_EMAC_GMAC_RXUDP_GD_FRMS register. */
#define ALT_EMAC_GMAC_RXUDP_GD_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_GD_FRMS_OFST))

/*
 * Register : Register 141 (rxudp_err_frms Register) - rxudp_err_frms
 * 
 * Number of good IP datagrams whose UDP payload has a checksum error
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | rxudp_err_frms
 * 
 */
/*
 * Field : rxudp_err_frms - cnt
 * 
 * Number of good IP datagrams whose UDP payload has a checksum error
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXUDP_ERR_FRMS.
 */
struct ALT_EMAC_GMAC_RXUDP_ERR_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxudp_err_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_ERR_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXUDP_ERR_FRMS_s  ALT_EMAC_GMAC_RXUDP_ERR_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_OFST        0x234
/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_FRMS register. */
#define ALT_EMAC_GMAC_RXUDP_ERR_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_ERR_FRMS_OFST))

/*
 * Register : Register 142 (rxtcp_gd_frms Register) - rxtcp_gd_frms
 * 
 * Number of good IP datagrams with a good TCP payload
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description           
 * :-------|:-------|:------|:-----------------------
 *  [31:0] | R      | 0x0   | rxtcp_gd_frms Register
 * 
 */
/*
 * Field : rxtcp_gd_frms Register - cnt
 * 
 * Number of good IP datagrams with a good TCP payload
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXTCP_GD_FRMS.
 */
struct ALT_EMAC_GMAC_RXTCP_GD_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxtcp_gd_frms Register */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_GD_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXTCP_GD_FRMS_s  ALT_EMAC_GMAC_RXTCP_GD_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_OFST        0x238
/* The address of the ALT_EMAC_GMAC_RXTCP_GD_FRMS register. */
#define ALT_EMAC_GMAC_RXTCP_GD_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_GD_FRMS_OFST))

/*
 * Register : Register 143 (rxtcp_err_frms Register) - rxtcp_err_frms
 * 
 * Number of good IP datagrams whose TCP payload has a checksum error
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | rxtcp_err_frms
 * 
 */
/*
 * Field : rxtcp_err_frms - cnt
 * 
 * Number of good IP datagrams whose TCP payload has a checksum error
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXTCP_ERR_FRMS.
 */
struct ALT_EMAC_GMAC_RXTCP_ERR_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxtcp_err_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_ERR_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXTCP_ERR_FRMS_s  ALT_EMAC_GMAC_RXTCP_ERR_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_OFST        0x23c
/* The address of the ALT_EMAC_GMAC_RXTCP_ERR_FRMS register. */
#define ALT_EMAC_GMAC_RXTCP_ERR_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_ERR_FRMS_OFST))

/*
 * Register : Register 144 (rxicmp_gd_frms Register) - rxicmp_gd_frms
 * 
 * Number of good IP datagrams with a good ICMP payload
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description   
 * :-------|:-------|:------|:---------------
 *  [31:0] | R      | 0x0   | rxicmp_gd_frms
 * 
 */
/*
 * Field : rxicmp_gd_frms - cnt
 * 
 * Number of good IP datagrams with a good ICMP payload
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXICMP_GD_FRMS.
 */
struct ALT_EMAC_GMAC_RXICMP_GD_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxicmp_gd_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_GD_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXICMP_GD_FRMS_s  ALT_EMAC_GMAC_RXICMP_GD_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_OFST        0x240
/* The address of the ALT_EMAC_GMAC_RXICMP_GD_FRMS register. */
#define ALT_EMAC_GMAC_RXICMP_GD_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_GD_FRMS_OFST))

/*
 * Register : Register 145 (rxicmp_err_frms Register) - rxicmp_err_frms
 * 
 * Number of good IP datagrams whose ICMP payload has a checksum error
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description    
 * :-------|:-------|:------|:----------------
 *  [31:0] | R      | 0x0   | rxicmp_err_frms
 * 
 */
/*
 * Field : rxicmp_err_frms - cnt
 * 
 * Number of good IP datagrams whose ICMP payload has a checksum error
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value. */
#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXICMP_ERR_FRMS.
 */
struct ALT_EMAC_GMAC_RXICMP_ERR_FRMS_s
{
    const uint32_t  cnt : 32;  /* rxicmp_err_frms */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_ERR_FRMS. */
typedef volatile struct ALT_EMAC_GMAC_RXICMP_ERR_FRMS_s  ALT_EMAC_GMAC_RXICMP_ERR_FRMS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_OFST        0x244
/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_FRMS register. */
#define ALT_EMAC_GMAC_RXICMP_ERR_FRMS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_ERR_FRMS_OFST))

/*
 * Register : Register 148 (rxipv4_gd_octets Register) - rxipv4_gd_octets
 * 
 * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP
 * data
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | R      | 0x0   | rxipv4_gd_octets
 * 
 */
/*
 * Field : rxipv4_gd_octets - cnt
 * 
 * Number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP
 * data
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_GD_OCTETS.
 */
struct ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxipv4_gd_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_GD_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_s  ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_OFST        0x250
/* The address of the ALT_EMAC_GMAC_RXIPV4_GD_OCTETS register. */
#define ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_OFST))

/*
 * Register : Register 149 (rxipv4_hdrerr_octets) - rxipv4_hdrerr_octets
 * 
 * Number of bytes received in IPv4 datagrams with header errors (checksum, length,
 * version mismatch). The value in the Length field of IPv4 header is used to
 * update this counter
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                  
 * :-------|:-------|:------|:------------------------------
 *  [31:0] | R      | 0x0   | rxipv4_hdrerr_octets Register
 * 
 */
/*
 * Field : rxipv4_hdrerr_octets Register - cnt
 * 
 * Number of bytes received in IPv4 datagrams with header errors (checksum, length,
 * version mismatch). The value in the Length field of IPv4 header is used to
 * update this counter
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS.
 */
struct ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxipv4_hdrerr_octets Register */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_s  ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_OFST        0x254
/* The address of the ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS register. */
#define ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_OFST))

/*
 * Register : Register 150 (rxipv4_nopay_octets Register) - rxipv4_nopay_octets
 * 
 * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP
 * payload. The value in the IPv4 headers Length field is used to update this
 * counter
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | rxipv4_nopay_octets
 * 
 */
/*
 * Field : rxipv4_nopay_octets - cnt
 * 
 * Number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP
 * payload. The value in the IPv4 headers Length field is used to update this
 * counter
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS.
 */
struct ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxipv4_nopay_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_s  ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_OFST        0x258
/* The address of the ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS register. */
#define ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_OFST))

/*
 * Register : Register 151 (rxipv4_frag_octets Register) - rxipv4_frag_octets
 * 
 * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4
 * headers Length field is used to update this counter
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description       
 * :-------|:-------|:------|:-------------------
 *  [31:0] | R      | 0x0   | rxipv4_frag_octets
 * 
 */
/*
 * Field : rxipv4_frag_octets - cnt
 * 
 * Number of bytes received in fragmented IPv4 datagrams. The value in the IPv4
 * headers Length field is used to update this counter
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS.
 */
struct ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxipv4_frag_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_s  ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_OFST        0x25c
/* The address of the ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS register. */
#define ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_OFST))

/*
 * Register : Register 152 (rxipv4_udsbl_octets Register) - rxipv4_udsbl_octets
 * 
 * Number of bytes received in a UDP segment that had the UDP checksum disabled.
 * This counter does not count IP Header bytes
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | rxipv4_udsbl_octets
 * 
 */
/*
 * Field : rxipv4_udsbl_octets - cnt
 * 
 * Number of bytes received in a UDP segment that had the UDP checksum disabled.
 * This counter does not count IP Header bytes
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS.
 */
struct ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxipv4_udsbl_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_s  ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_OFST        0x260
/* The address of the ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS register. */
#define ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_OFST))

/*
 * Register : Register 153 (rxipv6_gd_octets Register) - rxipv6_gd_octets
 * 
 * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6
 * data
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | R      | 0x0   | rxipv6_gd_octets
 * 
 */
/*
 * Field : rxipv6_gd_octets - cnt
 * 
 * Number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6
 * data
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_GD_OCTETS.
 */
struct ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxipv6_gd_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_GD_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_s  ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_OFST        0x264
/* The address of the ALT_EMAC_GMAC_RXIPV6_GD_OCTETS register. */
#define ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_OFST))

/*
 * Register : Register 154 (rxipv6_hdrerr_octets Register) - rxipv6_hdrerr_octets
 * 
 * Number of bytes received in IPv6 datagrams with header errors (length, version
 * mismatch). The value in the IPv6 headers Length field is used to update this
 * counter
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description         
 * :-------|:-------|:------|:---------------------
 *  [31:0] | R      | 0x0   | rxipv6_hdrerr_octets
 * 
 */
/*
 * Field : rxipv6_hdrerr_octets - cnt
 * 
 * Number of bytes received in IPv6 datagrams with header errors (length, version
 * mismatch). The value in the IPv6 headers Length field is used to update this
 * counter
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS.
 */
struct ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxipv6_hdrerr_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_s  ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_OFST        0x268
/* The address of the ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS register. */
#define ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_OFST))

/*
 * Register : Register 155 (rxipv6_nopay_octets Register) - rxipv6_nopay_octets
 * 
 * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP
 * payload. The value in the IPv6 headers Length field is used to update this
 * counter
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | R      | 0x0   | rxipv6_nopay_octets
 * 
 */
/*
 * Field : rxipv6_nopay_octets - cnt
 * 
 * Number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP
 * payload. The value in the IPv6 headers Length field is used to update this
 * counter
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS.
 */
struct ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxipv6_nopay_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_s  ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_OFST        0x26c
/* The address of the ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS register. */
#define ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_OFST))

/*
 * Register : Register 156 (rxudp_gd_octets Register) - rxudp_gd_octets
 * 
 * Number of bytes received in a good UDP segment. This counter does not count IP
 * header bytes
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description    
 * :-------|:-------|:------|:----------------
 *  [31:0] | R      | 0x0   | rxudp_gd_octets
 * 
 */
/*
 * Field : rxudp_gd_octets - cnt
 * 
 * Number of bytes received in a good UDP segment. This counter does not count IP
 * header bytes
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXUDP_GD_OCTETS.
 */
struct ALT_EMAC_GMAC_RXUDP_GD_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxudp_gd_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_GD_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXUDP_GD_OCTETS_s  ALT_EMAC_GMAC_RXUDP_GD_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_OFST        0x270
/* The address of the ALT_EMAC_GMAC_RXUDP_GD_OCTETS register. */
#define ALT_EMAC_GMAC_RXUDP_GD_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_GD_OCTETS_OFST))

/*
 * Register : Register 157 (rxudp_err_octets Register) - rxudp_err_octets
 * 
 * Number of bytes received in a UDP segment that had checksum errors
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | R      | 0x0   | rxudp_err_octets
 * 
 */
/*
 * Field : rxudp_err_octets - cnt
 * 
 * Number of bytes received in a UDP segment that had checksum errors
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXUDP_ERR_OCTETS.
 */
struct ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxudp_err_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXUDP_ERR_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_s  ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_OFST        0x274
/* The address of the ALT_EMAC_GMAC_RXUDP_ERR_OCTETS register. */
#define ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_OFST))

/*
 * Register : Register 158 (rxtcp_gd_octets Register) - rxtcp_gd_octets
 * 
 * Number of bytes received in a good TCP segment
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description    
 * :-------|:-------|:------|:----------------
 *  [31:0] | R      | 0x0   | rxtcp_gd_octets
 * 
 */
/*
 * Field : rxtcp_gd_octets - cnt
 * 
 * Number of bytes received in a good TCP segment
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXTCP_GD_OCTETS.
 */
struct ALT_EMAC_GMAC_RXTCP_GD_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxtcp_gd_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXTCP_GD_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXTCP_GD_OCTETS_s  ALT_EMAC_GMAC_RXTCP_GD_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_OFST        0x278
/* The address of the ALT_EMAC_GMAC_RXTCP_GD_OCTETS register. */
#define ALT_EMAC_GMAC_RXTCP_GD_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCP_GD_OCTETS_OFST))

/*
 * Register : Register 159 (rxtcp_err_octets Register) - rxtcperroctets
 * 
 * Number of bytes received in a TCP segment with checksum errors
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | R      | 0x0   | rxtcp_err_octets
 * 
 */
/*
 * Field : rxtcp_err_octets - rxtcp_err_octets
 * 
 * Number of bytes received in a TCP segment with checksum errors
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value. */
#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value. */
#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field. */
#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS field value from a register. */
#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXTCPERROCTETS_RXTCP_ERR_OCTETS_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXTCPERROCTETS.
 */
struct ALT_EMAC_GMAC_RXTCPERROCTETS_s
{
    const uint32_t  rxtcp_err_octets : 32;  /* rxtcp_err_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXTCPERROCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXTCPERROCTETS_s  ALT_EMAC_GMAC_RXTCPERROCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXTCPERROCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXTCPERROCTETS_OFST        0x27c
/* The address of the ALT_EMAC_GMAC_RXTCPERROCTETS register. */
#define ALT_EMAC_GMAC_RXTCPERROCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXTCPERROCTETS_OFST))

/*
 * Register : Register 160 (rxicmp_gd_octets Register) - rxicmp_gd_octets
 * 
 * Number of bytes received in a good ICMP segment
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | R      | 0x0   | rxicmp_gd_octets
 * 
 */
/*
 * Field : rxicmp_gd_octets - cnt
 * 
 * Number of bytes received in a good ICMP segment
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXICMP_GD_OCTETS.
 */
struct ALT_EMAC_GMAC_RXICMP_GD_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxicmp_gd_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_GD_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXICMP_GD_OCTETS_s  ALT_EMAC_GMAC_RXICMP_GD_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_OFST        0x280
/* The address of the ALT_EMAC_GMAC_RXICMP_GD_OCTETS register. */
#define ALT_EMAC_GMAC_RXICMP_GD_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_GD_OCTETS_OFST))

/*
 * Register : Register 161 (rxicmp_err_octets Register) - rxicmp_err_octets
 * 
 * Number of bytes received in an ICMP segment with checksum errors
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description      
 * :-------|:-------|:------|:------------------
 *  [31:0] | R      | 0x0   | rxicmp_err_octets
 * 
 */
/*
 * Field : rxicmp_err_octets - cnt
 * 
 * Number of bytes received in an ICMP segment with checksum errors
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value. */
#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field. */
#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT field value from a register. */
#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_CNT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_RXICMP_ERR_OCTETS.
 */
struct ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_s
{
    const uint32_t  cnt : 32;  /* rxicmp_err_octets */
};

/* The typedef declaration for register ALT_EMAC_GMAC_RXICMP_ERR_OCTETS. */
typedef volatile struct ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_s  ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register from the beginning of the component. */
#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_OFST        0x284
/* The address of the ALT_EMAC_GMAC_RXICMP_ERR_OCTETS register. */
#define ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_OFST))

/*
 * Register : Register 256 (Layer 3 and Layer 4 Control Register 0) - L3_L4_Control0
 * 
 * This register controls the operations of the filter 0 of Layer 3 and Layer 4.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                  
 * :--------|:-------|:------|:----------------------------------------------
 *  [0]     | RW     | 0x0   | Layer 3 Protocol Enable                      
 *  [1]     | ???    | 0x0   | *UNDEFINED*                                  
 *  [2]     | RW     | 0x0   | Layer 3 IP SA Match Enable                   
 *  [3]     | RW     | 0x0   | Layer 3 IP SA Inverse Match Enable           
 *  [4]     | RW     | 0x0   | Layer 3 IP DA Match Enable                   
 *  [5]     | RW     | 0x0   | Layer 3 IP DA Inverse Match Enable           
 *  [10:6]  | RW     | 0x0   | Layer 3 IP SA Higher Bits Match              
 *  [15:11] | RW     | 0x0   | Layer 3 IP DA Higher Bits Match              
 *  [16]    | RW     | 0x0   | Layer 4 Protocol Enable                      
 *  [17]    | ???    | 0x0   | *UNDEFINED*                                  
 *  [18]    | RW     | 0x0   | Layer 4 Source Port Match Enable             
 *  [19]    | RW     | 0x0   | Layer 4 Source Port Inverse Match Enable     
 *  [20]    | RW     | 0x0   | Layer 4 Destination Port Match Enable        
 *  [21]    | RW     | 0x0   | Layer 4 Destination Port Inverse Match Enable
 *  [31:22] | ???    | 0x0   | *UNDEFINED*                                  
 * 
 */
/*
 * Field : Layer 3 Protocol Enable - l3pen0
 * 
 * When set, this bit indicates that the Layer 3 IP Source or Destination Address
 * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
 * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
 * frames.
 * 
 * The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Layer 3 IP SA Match Enable - l3sam0
 * 
 * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
 * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
 * for matching.
 * 
 * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 4
 * (L3DAM0) because either IPv6 SA or DA can be checked for filtering.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Layer 3 IP SA Inverse Match Enable - l3saim0
 * 
 * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
 * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
 * Address field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 2 (L3SAM0) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Layer 3 IP DA Match Enable - l3dam0
 * 
 * When set, this bit indicates that Layer 3 IP Destination Address field is
 * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
 * Address field for matching.
 * 
 * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2
 * (L3SAM0) because either IPv6 DA or SA can be checked for filtering.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Layer 3 IP DA Inverse Match Enable - l3daim0
 * 
 * When set, this bit indicates that the Layer 3 IP Destination Address field is
 * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
 * Destination Address field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 4 (L3DAM0) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Layer 3 IP SA Higher Bits Match - l3hsbm0
 * 
 * IPv4 Frames:
 * 
 * This field contains the number of lower bits of IP Source Address that are
 * masked for matching in the IPv4 frames. The following list describes the values
 * of this field:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 31: All bits except MSb are masked.
 * 
 * IPv6 Frames:
 * 
 * This field contains Bits [4:0] of the field that indicates the number of higher
 * bits of IP Source or Destination Address matched in the IPv6 frames.
 * 
 * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET_MSK    0x000007c0
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_CLR_MSK    0xfffff83f
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_GET(value) (((value) & 0x000007c0) >> 6)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET(value) (((value) << 6) & 0x000007c0)

/*
 * Field : Layer 3 IP DA Higher Bits Match - l3hdbm0
 * 
 * IPv4 Frames:
 * 
 * This field contains the number of higher bits of IP Destination Address that are
 * matched in the IPv4 frames. The following list describes the values of this
 * field:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 31: All bits except MSb are masked.
 * 
 * IPv6 Frames:
 * 
 * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate
 * the number of lower bits of IP Source or Destination Address that are masked in
 * the IPv6 frames. The following list describes the concatenated values of the
 * L3HDBM0[1:0] and L3HSBM0 bits:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 127: All bits except MSb are masked.
 * 
 * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET_MSK    0x0000f800
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_CLR_MSK    0xffff07ff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_GET(value) (((value) & 0x0000f800) >> 11)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET(value) (((value) << 11) & 0x0000f800)

/*
 * Field : Layer 4 Protocol Enable - l4pen0
 * 
 * When set, this bit indicates that the Source and Destination Port number fields
 * for UDP frames are used for matching. When reset, this bit indicates that the
 * Source and Destination Port number fields for TCP frames are used for matching.
 * 
 * The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Layer 4 Source Port Match Enable - l4spm0
 * 
 * When set, this bit indicates that the Layer 4 Source Port number field is
 * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number
 * field for matching.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : Layer 4 Source Port Inverse Match Enable - l4spim0
 * 
 * When set, this bit indicates that the Layer 4 Source Port number field is
 * enabled for inverse matching. When reset, this bit indicates that the Layer 4
 * Source Port number field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 18 (L4SPM0) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : Layer 4 Destination Port Match Enable - l4dpm0
 * 
 * When set, this bit indicates that the Layer 4 Destination Port number field is
 * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port
 * number field for matching.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim0
 * 
 * When set, this bit indicates that the Layer 4 Destination Port number field is
 * enabled for inverse matching. When reset, this bit indicates that the Layer 4
 * Destination Port number field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET(value) (((value) << 21) & 0x00200000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL0.
 */
struct ALT_EMAC_GMAC_L3_L4_CTL0_s
{
    uint32_t  l3pen0  :  1;  /* Layer 3 Protocol Enable */
    uint32_t          :  1;  /* *UNDEFINED* */
    uint32_t  l3sam0  :  1;  /* Layer 3 IP SA Match Enable */
    uint32_t  l3saim0 :  1;  /* Layer 3 IP SA Inverse Match Enable */
    uint32_t  l3dam0  :  1;  /* Layer 3 IP DA Match Enable */
    uint32_t  l3daim0 :  1;  /* Layer 3 IP DA Inverse Match Enable */
    uint32_t  l3hsbm0 :  5;  /* Layer 3 IP SA Higher Bits Match */
    uint32_t  l3hdbm0 :  5;  /* Layer 3 IP DA Higher Bits Match */
    uint32_t  l4pen0  :  1;  /* Layer 4 Protocol Enable */
    uint32_t          :  1;  /* *UNDEFINED* */
    uint32_t  l4spm0  :  1;  /* Layer 4 Source Port Match Enable */
    uint32_t  l4spim0 :  1;  /* Layer 4 Source Port Inverse Match Enable */
    uint32_t  l4dpm0  :  1;  /* Layer 4 Destination Port Match Enable */
    uint32_t  l4dpim0 :  1;  /* Layer 4 Destination Port Inverse Match Enable */
    uint32_t          : 10;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL0. */
typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL0_s  ALT_EMAC_GMAC_L3_L4_CTL0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL0 register from the beginning of the component. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_OFST        0x400
/* The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register. */
#define ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL0_OFST))

/*
 * Register : Register 257 (Layer 4 Address Register 0) - Layer4_Address0
 * 
 * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
 * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
 * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
 * Layer 4 Address Registers are written. For proper synchronization updates, you
 * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
 * Registers after at least four clock cycles delay of the destination clock.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                          
 * :--------|:-------|:------|:--------------------------------------
 *  [15:0]  | RW     | 0x0   | Layer 4 Source Port Number Field     
 *  [31:16] | RW     | 0x0   | Layer 4 Destination Port Number Field
 * 
 */
/*
 * Field : Layer 4 Source Port Number Field - l4sp0
 * 
 * Layer 4 Source Port Number Field
 * 
 * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer
 * 3 and Layer 4 Control Register 0), this field contains the value to be matched
 * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
 * 
 * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 0), this field contains the value to be matched with
 * the UDP Source Port Number field in the IPv4 or IPv6 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 field value from a register. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Layer 4 Destination Port Number Field - l4dp0
 * 
 * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer
 * 3 and Layer 4 Control Register 0), this field contains the value to be matched
 * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
 * 
 * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 0), this field contains the value to be matched with
 * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET_MSK    0xffff0000
/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_CLR_MSK    0x0000ffff
/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 field value from a register. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET(value) (((value) << 16) & 0xffff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR0.
 */
struct ALT_EMAC_GMAC_LYR4_ADDR0_s
{
    uint32_t  l4sp0 : 16;  /* Layer 4 Source Port Number Field */
    uint32_t  l4dp0 : 16;  /* Layer 4 Destination Port Number Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR0. */
typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR0_s  ALT_EMAC_GMAC_LYR4_ADDR0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR0 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_OFST        0x404
/* The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register. */
#define ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR0_OFST))

/*
 * Register : Register 260 (Layer 3 Address 0 Register 0) - Layer3_Addr0_Reg0
 * 
 * For IPv4 frames, the Layer 3 Address 0 Register 0 contains the 32-bit IP Source
 * Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source
 * Address or Destination Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 0 Field
 * 
 */
/*
 * Field : Layer 3 Address 0 Field - l3a00
 * 
 * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 0), this field contains the value to be matched with
 * Bits[31:0] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 0), this field contains the value to be matched with
 * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3
 * and Layer 4 Control Register 0), this field contains the value to be matched
 * with the IP Source Address field in the IPv4 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG0.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s
{
    uint32_t  l3a00 : 32;  /* Layer 3 Address 0 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG0. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s  ALT_EMAC_GMAC_LYR3_ADDR0_REG0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST        0x410
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST))

/*
 * Register : Register 261 (Layer 3 Address 1 Register 0) - Layer3_Addr1_Reg0
 * 
 * For IPv4 frames, the Layer 3 Address 1 Register 0 contains the 32-bit IP
 * Destination Address field. For IPv6 frames, it contains Bits[63:32] of the
 * 128-bit IP Source Address or Destination Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 1 Field
 * 
 */
/*
 * Field : Layer 3 Address 1 Field - l3a10
 * 
 * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 0), this field contains the value to be matched with
 * Bits [63:32] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 0), this field contains the value to be matched with
 * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3
 * and Layer 4 Control Register 0), this field contains the value to be matched
 * with the IP Destination Address field in the IPv4 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_L3A10_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG0.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR1_REG0_s
{
    uint32_t  l3a10 : 32;  /* Layer 3 Address 1 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG0. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG0_s  ALT_EMAC_GMAC_LYR3_ADDR1_REG0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_OFST        0x414
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG0 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG0_OFST))

/*
 * Register : Register 262 (Layer 3 Address 2 Register 0) - Layer3_Addr2_Reg0
 * 
 * For IPv4 frames, the Layer 3 Address 2 Register 0 is reserved. For IPv6 frames,
 * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
 * field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 2 Field
 * 
 */
/*
 * Field : Layer 3 Address 2 Field - l3a20
 * 
 * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 0), this field contains the value to be matched with
 * Bits [95:64] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 0), this field contains value to be matched with Bits
 * [95:64] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control
 * Register 0), this register is not used.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_L3A20_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG0.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR2_REG0_s
{
    uint32_t  l3a20 : 32;  /* Layer 3 Address 2 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG0. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG0_s  ALT_EMAC_GMAC_LYR3_ADDR2_REG0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_OFST        0x418
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG0 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG0_OFST))

/*
 * Register : Register 263 (Layer 3 Address 3 Register 0) - Layer3_Addr3_Reg0
 * 
 * For IPv4 frames, the Layer 3 Address 3 Register 0 is reserved. For IPv6 frames,
 * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
 * Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 3 Field
 * 
 */
/*
 * Field : Layer 3 Address 3 Field - l3a30
 * 
 * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 0), this field contains the value to be matched with
 * Bits [127:96] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 0), this field contains the value to be matched with
 * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control
 * Register 0), this register is not used.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_L3A30_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG0.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR3_REG0_s
{
    uint32_t  l3a30 : 32;  /* Layer 3 Address 3 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG0. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG0_s  ALT_EMAC_GMAC_LYR3_ADDR3_REG0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_OFST        0x41c
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG0 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG0_OFST))

/*
 * Register : Register 268 (Layer 3 and Layer 4 Control Register 1) - L3_L4_Control1
 * 
 * This register controls the operations of the filter 0 of Layer 3 and Layer 4.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                  
 * :--------|:-------|:------|:----------------------------------------------
 *  [0]     | RW     | 0x0   | Layer 3 Protocol Enable                      
 *  [1]     | ???    | 0x0   | *UNDEFINED*                                  
 *  [2]     | RW     | 0x0   | Layer 3 IP SA Match Enable                   
 *  [3]     | RW     | 0x0   | Layer 3 IP SA Inverse Match Enable           
 *  [4]     | RW     | 0x0   | Layer 3 IP DA Match Enable                   
 *  [5]     | RW     | 0x0   | Layer 3 IP DA Inverse Match Enable           
 *  [10:6]  | RW     | 0x0   | Layer 3 IP SA Higher Bits Match              
 *  [15:11] | RW     | 0x0   | Layer 3 IP DA Higher Bits Match              
 *  [16]    | RW     | 0x0   | Layer 4 Protocol Enable                      
 *  [17]    | ???    | 0x0   | *UNDEFINED*                                  
 *  [18]    | RW     | 0x0   | Layer 4 Source Port Match Enable             
 *  [19]    | RW     | 0x0   | Layer 4 Source Port Inverse Match Enable     
 *  [20]    | RW     | 0x0   | Layer 4 Destination Port Match Enable        
 *  [21]    | RW     | 0x0   | Layer 4 Destination Port Inverse Match Enable
 *  [31:22] | ???    | 0x0   | *UNDEFINED*                                  
 * 
 */
/*
 * Field : Layer 3 Protocol Enable - l3pen1
 * 
 * When set, this bit indicates that the Layer 3 IP Source or Destination Address
 * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
 * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
 * frames.
 * 
 * The Layer 3 matching is done only when either L3SAM1 or L3DAM1 bit is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3PEN1_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Layer 3 IP SA Match Enable - l3sam1
 * 
 * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
 * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
 * for matching.
 * 
 * Note: When Bit 0 (L3PEN1) is set, you should set either this bit or Bit 4
 * (L3DAM1) because either IPv6 SA or DA can be checked for filtering.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAM1_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Layer 3 IP SA Inverse Match Enable - l3saim1
 * 
 * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
 * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
 * Address field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 2 (L3SAM1) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3SAIM1_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Layer 3 IP DA Match Enable - l3dam1
 * 
 * When set, this bit indicates that Layer 3 IP Destination Address field is
 * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
 * Address field for matching.
 * 
 * Note: When Bit 1 (L3PEN1) is set, you should set either this bit or Bit 2
 * (L3SAM1) because either IPv6 DA or SA can be checked for filtering.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAM1_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Layer 3 IP DA Inverse Match Enable - l3daim1
 * 
 * When set, this bit indicates that the Layer 3 IP Destination Address field is
 * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
 * Destination Address field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 4 (L3DAM1) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3DAIM1_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Layer 3 IP SA Higher Bits Match - l3hsbm1
 * 
 * IPv4 Frames:
 * 
 * This field contains the number of lower bits of IP Source Address that are
 * masked for matching in the IPv4 frames. The following list describes the values
 * of this field:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 31: All bits except MSb are masked.
 * 
 * IPv6 Frames:
 * 
 * This field contains Bits [4:0] of the field that indicates the number of higher
 * bits of IP Source or Destination Address matched in the IPv6 frames.
 * 
 * This field is valid and applicable only if L3DAM1 or L3SAM1 is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_SET_MSK    0x000007c0
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_CLR_MSK    0xfffff83f
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_GET(value) (((value) & 0x000007c0) >> 6)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HSBM1_SET(value) (((value) << 6) & 0x000007c0)

/*
 * Field : Layer 3 IP DA Higher Bits Match - l3hdbm1
 * 
 * IPv4 Frames:
 * 
 * This field contains the number of higher bits of IP Destination Address that are
 * matched in the IPv4 frames. The following list describes the values of this
 * field:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 31: All bits except MSb are masked.
 * 
 * IPv6 Frames:
 * 
 * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM1, which indicate
 * the number of lower bits of IP Source or Destination Address that are masked in
 * the IPv6 frames. The following list describes the concatenated values of the
 * L3HDBM1[1:0] and L3HSBM1 bits:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 127: All bits except MSb are masked.
 * 
 * This field is valid and applicable only if L3DAM1 or L3SAM1 is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_SET_MSK    0x0000f800
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_CLR_MSK    0xffff07ff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_GET(value) (((value) & 0x0000f800) >> 11)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L3HDBM1_SET(value) (((value) << 11) & 0x0000f800)

/*
 * Field : Layer 4 Protocol Enable - l4pen1
 * 
 * When set, this bit indicates that the Source and Destination Port number fields
 * for UDP frames are used for matching. When reset, this bit indicates that the
 * Source and Destination Port number fields for TCP frames are used for matching.
 * 
 * The Layer 4 matching is done only when either L4SPM1 or L4DPM1 bit is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4PEN1_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Layer 4 Source Port Match Enable - l4spm1
 * 
 * When set, this bit indicates that the Layer 4 Source Port number field is
 * enabled for matching.
 * 
 * When reset, the MAC ignores the Layer 4 Source Port number field for matching.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPM1_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : Layer 4 Source Port Inverse Match Enable - l4spim1
 * 
 * When set, this bit indicates that the Layer 4 Source Port number field is
 * enabled for inverse matching.
 * 
 * When reset, this bit indicates that the Layer 4 Source Port number field is
 * enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 18 (L4SPM1) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4SPIM1_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : Layer 4 Destination Port Match Enable - l4dpm1
 * 
 * When set, this bit indicates that the Layer 4 Destination Port number field is
 * enabled for matching.
 * 
 * When reset, the MAC ignores the Layer 4 Destination Port number field for
 * matching.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPM1_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim1
 * 
 * When set, this bit indicates that the Layer 4 Destination Port number field is
 * enabled for inverse matching.
 * 
 * When reset, this bit indicates that the Layer 4 Destination Port number field is
 * enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 20 (L4DPM1) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_L4DPIM1_SET(value) (((value) << 21) & 0x00200000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL1.
 */
struct ALT_EMAC_GMAC_L3_L4_CTL1_s
{
    uint32_t  l3pen1  :  1;  /* Layer 3 Protocol Enable */
    uint32_t          :  1;  /* *UNDEFINED* */
    uint32_t  l3sam1  :  1;  /* Layer 3 IP SA Match Enable */
    uint32_t  l3saim1 :  1;  /* Layer 3 IP SA Inverse Match Enable */
    uint32_t  l3dam1  :  1;  /* Layer 3 IP DA Match Enable */
    uint32_t  l3daim1 :  1;  /* Layer 3 IP DA Inverse Match Enable */
    uint32_t  l3hsbm1 :  5;  /* Layer 3 IP SA Higher Bits Match */
    uint32_t  l3hdbm1 :  5;  /* Layer 3 IP DA Higher Bits Match */
    uint32_t  l4pen1  :  1;  /* Layer 4 Protocol Enable */
    uint32_t          :  1;  /* *UNDEFINED* */
    uint32_t  l4spm1  :  1;  /* Layer 4 Source Port Match Enable */
    uint32_t  l4spim1 :  1;  /* Layer 4 Source Port Inverse Match Enable */
    uint32_t  l4dpm1  :  1;  /* Layer 4 Destination Port Match Enable */
    uint32_t  l4dpim1 :  1;  /* Layer 4 Destination Port Inverse Match Enable */
    uint32_t          : 10;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL1. */
typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL1_s  ALT_EMAC_GMAC_L3_L4_CTL1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL1 register from the beginning of the component. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_OFST        0x430
/* The address of the ALT_EMAC_GMAC_L3_L4_CTL1 register. */
#define ALT_EMAC_GMAC_L3_L4_CTL1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL1_OFST))

/*
 * Register : Register 269 (Layer 4 Address Register 1) - Layer4_Address1
 * 
 * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
 * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
 * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
 * Layer 4 Address Registers are written. For proper synchronization updates, you
 * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
 * Registers after at least four clock cycles delay of the destination clock.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                          
 * :--------|:-------|:------|:--------------------------------------
 *  [15:0]  | RW     | 0x0   | Layer 4 Source Port Number Field     
 *  [31:16] | RW     | 0x0   | Layer 4 Destination Port Number Field
 * 
 */
/*
 * Field : Layer 4 Source Port Number Field - l4sp1
 * 
 * When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer
 * 3 and Layer 4 Control Register 1), this field contains the value to be matched
 * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
 * 
 * When Bit 16 (L4PEN1) and Bit 20 (L4DPM1) are set in Register 268 (Layer 3 and
 * Layer 4 Control Register 1), this field contains the value to be matched with
 * the UDP Source Port Number field in the IPv4 or IPv6 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 field value from a register. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4SP1_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Layer 4 Destination Port Number Field - l4dp1
 * 
 * When Bit 16 (L4PEN1) is reset and Bit 20 (L4DPM1) is set in Register 268 (Layer
 * 3 and Layer 4 Control Register 0), this field contains the value to be matched
 * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
 * 
 * When Bit 16 (L4PEN1) and Bit 20 (L4DPM1) are set in Register 268 (Layer 3 and
 * Layer 4 Control Register 1), this field contains the value to be matched with
 * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_SET_MSK    0xffff0000
/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_CLR_MSK    0x0000ffff
/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 field value from a register. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_L4DP1_SET(value) (((value) << 16) & 0xffff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR1.
 */
struct ALT_EMAC_GMAC_LYR4_ADDR1_s
{
    uint32_t  l4sp1 : 16;  /* Layer 4 Source Port Number Field */
    uint32_t  l4dp1 : 16;  /* Layer 4 Destination Port Number Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR1. */
typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR1_s  ALT_EMAC_GMAC_LYR4_ADDR1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR1 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_OFST        0x434
/* The address of the ALT_EMAC_GMAC_LYR4_ADDR1 register. */
#define ALT_EMAC_GMAC_LYR4_ADDR1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR1_OFST))

/*
 * Register : Register 272 (Layer 3 Address 0 Register 1) - Layer3_Addr0_Reg1
 * 
 * For IPv4 frames, the Layer 3 Address 0 Register 1 contains the 32-bit IP Source
 * Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source
 * Address or Destination Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 0 Field
 * 
 */
/*
 * Field : Layer 3 Address 0 Field - l3a01
 * 
 * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
 * Layer 4 Control Register 1), this field contains the value to be matched with
 * Bits[31:0] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
 * Layer 4 Control Register 1), this field contains the value to be matched with
 * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN1) is reset and Bit 2 (L3SAM1) is set in Register 268 (Layer 3
 * and Layer 4 Control Register 1), this field contains the value to be matched
 * with the IP Source Address field in the IPv4 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_L3A01_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG1.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR0_REG1_s
{
    uint32_t  l3a01 : 32;  /* Layer 3 Address 0 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG1. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG1_s  ALT_EMAC_GMAC_LYR3_ADDR0_REG1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_OFST        0x440
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG1 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG1_OFST))

/*
 * Register : Register 273 (Layer 3 Address 1 Register 1) - Layer3_Addr1_Reg1
 * 
 * For IPv4 frames, the Layer 3 Address 1 Register 1 contains the 32-bit IP
 * Destination Address field. For IPv6 frames, it contains Bits[63:32] of the
 * 128-bit IP Source Address or Destination Address field
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 1 Field
 * 
 */
/*
 * Field : Layer 3 Address 1 Field - l3a11
 * 
 * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
 * Layer 4 Control Register 1), this field contains the value to be matched with
 * Bits [63:32] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
 * Layer 4 Control Register 1), this field contains the value to be matched with
 * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN1) is reset and Bit 4 (L3DAM1) is set in Register 268 (Layer 3
 * and Layer 4 Control Register 1), this field contains the value to be matched
 * with the IP Destination Address field in the IPv4 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_L3A11_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG1.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR1_REG1_s
{
    uint32_t  l3a11 : 32;  /* Layer 3 Address 1 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG1. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG1_s  ALT_EMAC_GMAC_LYR3_ADDR1_REG1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_OFST        0x444
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG1 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG1_OFST))

/*
 * Register : Register 274 (Layer 3 Address 2 Register 1) - Layer3_Addr2_Reg1
 * 
 * For IPv4 frames, the Layer 3 Address 2 Register 1 is reserved. For IPv6 frames,
 * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
 * field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 2 Field
 * 
 */
/*
 * Field : Layer 3 Address 2 Field - l3a21
 * 
 * When Bit 0 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
 * Layer 4 Control Register 1), this field contains the value to be matched with
 * Bits [95:64] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
 * Layer 4 Control Register 1), this field contains value to be matched with Bits
 * [95:64] of the IP Destination Address field in the IPv6 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_L3A21_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG1.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR2_REG1_s
{
    uint32_t  l3a21 : 32;  /* Layer 3 Address 2 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG1. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG1_s  ALT_EMAC_GMAC_LYR3_ADDR2_REG1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_OFST        0x448
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG1 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG1_OFST))

/*
 * Register : Register 275 (Layer 3 Address 3 Register 1) - Layer3_Addr3_Reg1
 * 
 * For IPv4 frames, the Layer 3 Address 3 Register 1 is reserved. For IPv6 frames,
 * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
 * Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 3 Field
 * 
 */
/*
 * Field : Layer 3 Address 3 Field - l3a31
 * 
 * When Bit 1 (L3PEN1) and Bit 2 (L3SAM1) are set in Register 268 (Layer 3 and
 * Layer 4 Control Register 1), this field contains the value to be matched with
 * Bits [127:96] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN1) and Bit 4 (L3DAM1) are set in Register 268 (Layer 3 and
 * Layer 4 Control Register 1), this field contains the value to be matched with
 * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN1) is reset in Register 268 (Layer 3 and Layer 4 Control
 * Register 1), this register is not used.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_L3A31_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG1.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR3_REG1_s
{
    uint32_t  l3a31 : 32;  /* Layer 3 Address 3 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG1. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG1_s  ALT_EMAC_GMAC_LYR3_ADDR3_REG1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_OFST        0x44c
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG1 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG1_OFST))

/*
 * Register : Register 280 (Layer 3 and Layer 4 Control Register 2) - L3_L4_Control2
 * 
 * This register controls the operations of the filter 2 of Layer 3 and Layer 4.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                  
 * :--------|:-------|:------|:----------------------------------------------
 *  [0]     | RW     | 0x0   | Layer 3 Protocol Enable                      
 *  [1]     | ???    | 0x0   | *UNDEFINED*                                  
 *  [2]     | RW     | 0x0   | Layer 3 IP SA Match Enable                   
 *  [3]     | RW     | 0x0   | Layer 3 IP SA Inverse Match Enable           
 *  [4]     | RW     | 0x0   | Layer 3 IP DA Match Enable                   
 *  [5]     | RW     | 0x0   | Layer 3 IP DA Inverse Match Enable           
 *  [10:6]  | RW     | 0x0   | ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2             
 *  [15:11] | RW     | 0x0   | Layer 3 IP DA Higher Bits Match              
 *  [16]    | RW     | 0x0   | Layer 4 Protocol Enable                      
 *  [17]    | ???    | 0x0   | *UNDEFINED*                                  
 *  [18]    | RW     | 0x0   | Layer 4 Source Port Match Enable             
 *  [19]    | RW     | 0x0   | Layer 4 Source Port Inverse Match Enable     
 *  [20]    | RW     | 0x0   | Layer 4 Destination Port Match Enable        
 *  [21]    | RW     | 0x0   | Layer 4 Destination Port Inverse Match Enable
 *  [31:22] | ???    | 0x0   | *UNDEFINED*                                  
 * 
 */
/*
 * Field : Layer 3 Protocol Enable - l3pen2
 * 
 * When set, this bit indicates that the Layer 3 IP Source or Destination Address
 * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
 * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
 * frames.
 * 
 * The Layer 3 matching is done only when either L3SAM2 or L3DAM2 bit is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Layer 3 IP SA Match Enable - l3sam2
 * 
 * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
 * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
 * for matching.
 * 
 * Note: When Bit 0 (L3PEN2) is set, you should set either this bit or Bit 4
 * (L3DAM2) because either IPv6 SA or DA can be checked for filtering.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Layer 3 IP SA Inverse Match Enable - l3saim2
 * 
 * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
 * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
 * Address field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 2 (L3SAM2) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Layer 3 IP DA Match Enable - l3dam2
 * 
 * When set, this bit indicates that Layer 3 IP Destination Address field is
 * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
 * Address field for matching.
 * 
 * Note: When Bit 0 (L3PEN2) is set, you should set either this bit or Bit 2
 * (L3SAM2) because either IPv6 DA or SA can be checked for filtering.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Layer 3 IP DA Inverse Match Enable - l3daim2
 * 
 * When set, this bit indicates that the Layer 3 IP Destination Address field is
 * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
 * Destination Address field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 4 (L3DAM2) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : l3hsbm2
 * 
 * Layer 3 IP SA Higher Bits Match
 * 
 * IPv4 Frames:
 * 
 * This field contains the number of lower bits of IP Source Address that are
 * masked for matching in the IPv4 frames. The following list describes the values
 * of this field:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 31: All bits except MSb are masked.
 * 
 * IPv6 Frames:
 * 
 * This field contains Bits [4:0] of the field that indicates the number of higher
 * bits of IP Source or Destination Address matched in the IPv6 frames.
 * 
 * This field is valid and applicable only if L3DAM2 or L3SAM2 is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET_MSK    0x000007c0
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_CLR_MSK    0xfffff83f
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_GET(value) (((value) & 0x000007c0) >> 6)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET(value) (((value) << 6) & 0x000007c0)

/*
 * Field : Layer 3 IP DA Higher Bits Match - l3hdbm2
 * 
 * IPv4 Frames:
 * 
 * This field contains the number of higher bits of IP Destination Address that are
 * matched in the IPv4 frames. The following list describes the values of this
 * field:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 31: All bits except MSb are masked.
 * 
 * IPv6 Frames:
 * 
 * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM2, which indicate
 * the number of lower bits of IP Source or Destination Address that are masked in
 * the IPv6 frames. The following list describes the concatenated values of the
 * L3HDBM2[1:0] and L3HSBM2 bits:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 127: All bits except MSb are masked.
 * 
 * This field is valid and applicable only if L3DAM2 or L3SAM2 is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET_MSK    0x0000f800
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_CLR_MSK    0xffff07ff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_GET(value) (((value) & 0x0000f800) >> 11)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET(value) (((value) << 11) & 0x0000f800)

/*
 * Field : Layer 4 Protocol Enable - l4pen2
 * 
 * When set, this bit indicates that the Source and Destination Port number fields
 * for UDP frames are used for matching. When reset, this bit indicates that the
 * Source and Destination Port number fields for TCP frames are used for matching.
 * 
 * The Layer 4 matching is done only when either L4SPM2 or L4DPM2 bit is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Layer 4 Source Port Match Enable - l4spm2
 * 
 * When set, this bit indicates that the Layer 4 Source Port number field is
 * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number
 * field for matching.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : Layer 4 Source Port Inverse Match Enable - l4spim2
 * 
 * When set, this bit indicates that the Layer 4 Source Port number field is
 * enabled for inverse matching. When reset, this bit indicates that the Layer 4
 * Source Port number field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 18 (L4SPM2) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : Layer 4 Destination Port Match Enable - l4dpm2
 * 
 * When set, this bit indicates that the Layer 4 Destination Port number field is
 * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port
 * number field for matching.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim2
 * 
 * When set, this bit indicates that the Layer 4 Destination Port number field is
 * enabled for inverse matching. When reset, this bit indicates that the Layer 4
 * Destination Port number field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET(value) (((value) << 21) & 0x00200000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL2.
 */
struct ALT_EMAC_GMAC_L3_L4_CTL2_s
{
    uint32_t  l3pen2  :  1;  /* Layer 3 Protocol Enable */
    uint32_t          :  1;  /* *UNDEFINED* */
    uint32_t  l3sam2  :  1;  /* Layer 3 IP SA Match Enable */
    uint32_t  l3saim2 :  1;  /* Layer 3 IP SA Inverse Match Enable */
    uint32_t  l3dam2  :  1;  /* Layer 3 IP DA Match Enable */
    uint32_t  l3daim2 :  1;  /* Layer 3 IP DA Inverse Match Enable */
    uint32_t  l3hsbm2 :  5;  /* ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 */
    uint32_t  l3hdbm2 :  5;  /* Layer 3 IP DA Higher Bits Match */
    uint32_t  l4pen2  :  1;  /* Layer 4 Protocol Enable */
    uint32_t          :  1;  /* *UNDEFINED* */
    uint32_t  l4spm2  :  1;  /* Layer 4 Source Port Match Enable */
    uint32_t  l4spim2 :  1;  /* Layer 4 Source Port Inverse Match Enable */
    uint32_t  l4dpm2  :  1;  /* Layer 4 Destination Port Match Enable */
    uint32_t  l4dpim2 :  1;  /* Layer 4 Destination Port Inverse Match Enable */
    uint32_t          : 10;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL2. */
typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL2_s  ALT_EMAC_GMAC_L3_L4_CTL2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL2 register from the beginning of the component. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_OFST        0x460
/* The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register. */
#define ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL2_OFST))

/*
 * Register : Register 281 (Layer 4 Address Register 2) - Layer4_Address2
 * 
 * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
 * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
 * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
 * Layer 4 Address Registers are written. For proper synchronization updates, you
 * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
 * Registers after at least four clock cycles delay of the destination clock.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                          
 * :--------|:-------|:------|:--------------------------------------
 *  [15:0]  | RW     | 0x0   | Layer 4 Source Port Number Field     
 *  [31:16] | RW     | 0x0   | Layer 4 Destination Port Number Field
 * 
 */
/*
 * Field : Layer 4 Source Port Number Field - l4sp2
 * 
 * When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer
 * 3 and Layer 4 Control Register 2), this field contains the value to be matched
 * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
 * 
 * When Bit 16 (L4PEN2) and Bit 20 (L4DPM2) are set in Register 280 (Layer 3 and
 * Layer 4 Control Register 2), this field contains the value to be matched with
 * the UDP Source Port Number field in the IPv4 or IPv6 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 field value from a register. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4SP2_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Layer 4 Destination Port Number Field - l4dp2
 * 
 * When Bit 16 (L4PEN2) is reset and Bit 20 (L4DPM2) is set in Register 280 (Layer
 * 3 and Layer 4 Control Register 2), this field contains the value to be matched
 * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
 * 
 * When Bit 16 (L4PEN2) and Bit 20 (L4DPM2) are set in Register 280 (Layer 3 and
 * Layer 4 Control Register 2), this field contains the value to be matched with
 * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_SET_MSK    0xffff0000
/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_CLR_MSK    0x0000ffff
/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 field value from a register. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_L4DP2_SET(value) (((value) << 16) & 0xffff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR2.
 */
struct ALT_EMAC_GMAC_LYR4_ADDR2_s
{
    uint32_t  l4sp2 : 16;  /* Layer 4 Source Port Number Field */
    uint32_t  l4dp2 : 16;  /* Layer 4 Destination Port Number Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR2. */
typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR2_s  ALT_EMAC_GMAC_LYR4_ADDR2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR2 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_OFST        0x464
/* The address of the ALT_EMAC_GMAC_LYR4_ADDR2 register. */
#define ALT_EMAC_GMAC_LYR4_ADDR2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR2_OFST))

/*
 * Register : Register 284 (Layer 3 Address 0 Register 2) - Layer3_Addr0_Reg2
 * 
 * For IPv4 frames, the Layer 3 Address 0 Register 2 contains the 32-bit IP Source
 * Address field. For IPv6 frames, it contains Bits [31:0] of the 128-bit IP Source
 * Address or Destination Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 0 Field
 * 
 */
/*
 * Field : Layer 3 Address 0 Field - l3a02
 * 
 * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
 * Layer 4 Control Register 2), this field contains the value to be matched with
 * Bits [31:0] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and
 * Layer 4 Control Register 2), this field contains the value to be matched with
 * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN2) is reset and Bit 2 (L3SAM2) is set in Register 280 (Layer 3
 * and Layer 4 Control Register 2), this field contains the value to be matched
 * with the IP Source Address field in the IPv4 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_L3A02_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG2.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR0_REG2_s
{
    uint32_t  l3a02 : 32;  /* Layer 3 Address 0 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG2. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG2_s  ALT_EMAC_GMAC_LYR3_ADDR0_REG2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_OFST        0x470
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG2 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG2_OFST))

/*
 * Register : Register 285 (Layer 3 Address 1 Register 2) - Layer3_Addr1_Reg2
 * 
 * For IPv4 frames, the Layer 3 Address 1 Register 2 contains the 32-bit IP
 * Destination Address field. For IPv6 frames, it contains Bits [63:32] of the
 * 128-bit IP Source Address or Destination Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 1 Field
 * 
 */
/*
 * Field : Layer 3 Address 1 Field - l3a12
 * 
 * Layer 3 Address 1 Field
 * 
 * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
 * Layer 4 Control Register 2), this field contains the value to be matched with
 * Bits [63:32] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and
 * Layer 4 Control Register 2), this field contains the value to be matched with
 * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN2) is reset and Bit 4 (L3DAM2) is set in Register 280 (Layer 3
 * and Layer 4 Control Register 2), this field contains the value to be matched
 * with the IP Destination Address field in the IPv4 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_L3A12_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG2.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR1_REG2_s
{
    uint32_t  l3a12 : 32;  /* Layer 3 Address 1 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG2. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG2_s  ALT_EMAC_GMAC_LYR3_ADDR1_REG2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_OFST        0x474
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG2 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG2_OFST))

/*
 * Register : Register 286 (Layer 3 Address 2 Register 2) - Layer3_Addr2_Reg2
 * 
 * For IPv4 frames, the Layer 3 Address 2 Register 2 is reserved. For IPv6 frames,
 * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
 * field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 2 Field
 * 
 */
/*
 * Field : Layer 3 Address 2 Field - l3a22
 * 
 * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
 * Layer 4 Control Register 2), this field contains the value to be matched with
 * Bits [95:64] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 256 (Layer 3 and
 * Layer 4 Control Register 2), this field contains value to be matched with Bits
 * [95:64] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN2) is reset in Register 280 (Layer 3 and Layer 4 Control
 * Register 2), this register is not used.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_L3A22_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG2.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR2_REG2_s
{
    uint32_t  l3a22 : 32;  /* Layer 3 Address 2 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG2. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG2_s  ALT_EMAC_GMAC_LYR3_ADDR2_REG2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_OFST        0x478
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG2 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG2_OFST))

/*
 * Register : Register 287 (Layer 3 Address 3 Register 2) - Layer3_Addr3_Reg2
 * 
 * For IPv4 frames, the Layer 3 Address 3 Register 2 is reserved. For IPv6 frames,
 * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
 * Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 3 Field
 * 
 */
/*
 * Field : Layer 3 Address 3 Field - l3a32
 * 
 * When Bit 0 (L3PEN2) and Bit 2 (L3SAM2) are set in Register 280 (Layer 3 and
 * Layer 4 Control Register 2), this field contains the value to be matched with
 * Bits [127:96] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN2) and Bit 4 (L3DAM2) are set in Register 280 (Layer 3 and
 * Layer 4 Control Register 2), this field contains the value to be matched with
 * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN2) is reset in Register 280 (Layer 3 and Layer 4 Control
 * Register 2), this register is not used.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_L3A32_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG2.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR3_REG2_s
{
    uint32_t  l3a32 : 32;  /* Layer 3 Address 3 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG2. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG2_s  ALT_EMAC_GMAC_LYR3_ADDR3_REG2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_OFST        0x47c
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG2 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG2_OFST))

/*
 * Register : Register 292 (Layer 3 and Layer 4 Control Register 3) - L3_L4_Control3
 * 
 * This register controls the operations of the filter 0 of Layer 3 and Layer 4.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                  
 * :--------|:-------|:------|:----------------------------------------------
 *  [0]     | RW     | 0x0   | Layer 3 Protocol Enable                      
 *  [1]     | ???    | 0x0   | *UNDEFINED*                                  
 *  [2]     | RW     | 0x0   | Layer 3 IP SA Match Enable                   
 *  [3]     | RW     | 0x0   | Layer 3 IP SA Inverse Match Enable           
 *  [4]     | RW     | 0x0   | Layer 3 IP DA Match Enable                   
 *  [5]     | RW     | 0x0   | Layer 3 IP DA Inverse Match Enable           
 *  [10:6]  | RW     | 0x0   | Layer 3 IP SA Higher Bits Match              
 *  [15:11] | RW     | 0x0   | ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3             
 *  [16]    | RW     | 0x0   | Layer 4 Protocol Enable                      
 *  [17]    | ???    | 0x0   | *UNDEFINED*                                  
 *  [18]    | RW     | 0x0   | Layer 4 Source Port Match Enable             
 *  [19]    | RW     | 0x0   | Layer 4 Source Port Inverse Match Enable     
 *  [20]    | RW     | 0x0   | Layer 4 Destination Port Match Enable        
 *  [21]    | RW     | 0x0   | Layer 4 Destination Port Inverse Match Enable
 *  [31:22] | ???    | 0x0   | *UNDEFINED*                                  
 * 
 */
/*
 * Field : Layer 3 Protocol Enable - l3pen3
 * 
 * When set, this bit indicates that the Layer 3 IP Source or Destination Address
 * matching is enabled for the IPv6 frames. When reset, this bit indicates that the
 * Layer 3 IP Source or Destination Address matching is enabled for the IPv4
 * frames.
 * 
 * The Layer 3 matching is done only when either L3SAM3 or L3DAM3 bit is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Layer 3 IP SA Match Enable - l3sam3
 * 
 * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
 * for matching. When reset, the MAC ignores the Layer 3 IP Source Address field
 * for matching.
 * 
 * Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 4
 * (L3DAM3) because either IPv6 SA or DA can be checked for filtering.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Layer 3 IP SA Inverse Match Enable - l3saim3
 * 
 * When set, this bit indicates that the Layer 3 IP Source Address field is enabled
 * for inverse matching. When reset, this bit indicates that the Layer 3 IP Source
 * Address field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 2 (L3SAM3) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Layer 3 IP DA Match Enable - l3dam3
 * 
 * When set, this bit indicates that Layer 3 IP Destination Address field is
 * enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination
 * Address field for matching.
 * 
 * Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 2
 * (L3SAM3) because either IPv6 DA or SA can be checked for filtering.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Layer 3 IP DA Inverse Match Enable - l3daim3
 * 
 * When set, this bit indicates that the Layer 3 IP Destination Address field is
 * enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP
 * Destination Address field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 4 (L3DAM3) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Layer 3 IP SA Higher Bits Match - l3hsbm3
 * 
 * IPv4 Frames:
 * 
 * This field contains the number of lower bits of IP Source Address that are
 * masked for matching in the IPv4 frames. The following list describes the values
 * of this field:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 31: All bits except MSb are masked.
 * 
 * IPv6 Frames:
 * 
 * This field contains Bits [4:0] of the field that indicates the number of higher
 * bits of IP Source or Destination Address matched in the IPv6 frames.
 * 
 * This field is valid and applicable only if L3DAM3 or L3SAM3 is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET_MSK    0x000007c0
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_CLR_MSK    0xfffff83f
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_GET(value) (((value) & 0x000007c0) >> 6)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET(value) (((value) << 6) & 0x000007c0)

/*
 * Field : l3hdbm3
 * 
 * Layer 3 IP DA Higher Bits Match
 * 
 * IPv4 Frames:
 * 
 * This field contains the number of higher bits of IP Destination Address that are
 * matched in the IPv4 frames. The following list describes the values of this
 * field:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 31: All bits except MSb are masked.
 * 
 * IPv6 Frames:
 * 
 * Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM3, which indicate
 * the number of lower bits of IP Source or Destination Address that are masked in
 * the IPv6 frames. The following list describes the concatenated values of the
 * L3HDBM3[1:0] and L3HSBM3 bits:
 * 
 * * 0: No bits are masked.
 * 
 * * 1: LSb[0] is masked.
 * 
 * * 2: Two LSbs [1:0] are masked.
 * 
 * * ...
 * 
 * * 127: All bits except MSb are masked.
 * 
 * This field is valid and applicable only if L3DAM3 or L3SAM3 is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET_MSK    0x0000f800
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_CLR_MSK    0xffff07ff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_GET(value) (((value) & 0x0000f800) >> 11)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET(value) (((value) << 11) & 0x0000f800)

/*
 * Field : Layer 4 Protocol Enable - l4pen3
 * 
 * When set, this bit indicates that the Source and Destination Port number fields
 * for UDP frames are used for matching. When reset, this bit indicates that the
 * Source and Destination Port number fields for TCP frames are used for matching.
 * 
 * The Layer 4 matching is done only when either L4SPM3 or L4DPM3 bit is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_MSB        16
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Layer 4 Source Port Match Enable - l4spm3
 * 
 * When set, this bit indicates that the Layer 4 Source Port number field is
 * enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number
 * field for matching.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : Layer 4 Source Port Inverse Match Enable - l4spim3
 * 
 * When set, this bit indicates that the Layer 4 Source Port number field is
 * enabled for inverse matching. When reset, this bit indicates that the Layer 4
 * Source Port number field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 18 (L4SPM3) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : Layer 4 Destination Port Match Enable - l4dpm3
 * 
 * When set, this bit indicates that the Layer 4 Destination Port number field is
 * enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port
 * number field for matching.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_MSB        20
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Layer 4 Destination Port Inverse Match Enable - l4dpim3
 * 
 * When set, this bit indicates that the Layer 4 Destination Port number field is
 * enabled for inverse matching. When reset, this bit indicates that the Layer 4
 * Destination Port number field is enabled for perfect matching.
 * 
 * This bit is valid and applicable only when Bit 20 (L4DPM3) is set high.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_MSB        21
/* The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 field value from a register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET(value) (((value) << 21) & 0x00200000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL3.
 */
struct ALT_EMAC_GMAC_L3_L4_CTL3_s
{
    uint32_t  l3pen3  :  1;  /* Layer 3 Protocol Enable */
    uint32_t          :  1;  /* *UNDEFINED* */
    uint32_t  l3sam3  :  1;  /* Layer 3 IP SA Match Enable */
    uint32_t  l3saim3 :  1;  /* Layer 3 IP SA Inverse Match Enable */
    uint32_t  l3dam3  :  1;  /* Layer 3 IP DA Match Enable */
    uint32_t  l3daim3 :  1;  /* Layer 3 IP DA Inverse Match Enable */
    uint32_t  l3hsbm3 :  5;  /* Layer 3 IP SA Higher Bits Match */
    uint32_t  l3hdbm3 :  5;  /* ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 */
    uint32_t  l4pen3  :  1;  /* Layer 4 Protocol Enable */
    uint32_t          :  1;  /* *UNDEFINED* */
    uint32_t  l4spm3  :  1;  /* Layer 4 Source Port Match Enable */
    uint32_t  l4spim3 :  1;  /* Layer 4 Source Port Inverse Match Enable */
    uint32_t  l4dpm3  :  1;  /* Layer 4 Destination Port Match Enable */
    uint32_t  l4dpim3 :  1;  /* Layer 4 Destination Port Inverse Match Enable */
    uint32_t          : 10;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL3. */
typedef volatile struct ALT_EMAC_GMAC_L3_L4_CTL3_s  ALT_EMAC_GMAC_L3_L4_CTL3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL3 register from the beginning of the component. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_OFST        0x490
/* The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register. */
#define ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL3_OFST))

/*
 * Register : Register 293 (Layer 4 Address Register 3) - Layer4_Address3
 * 
 * Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the
 * Rx clock domains, then the synchronization is triggered only when Bits[31:24]
 * (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and
 * Layer 4 Address Registers are written. For proper synchronization updates, you
 * should perform the consecutive writes to the same Layer 3 and Layer 4 Address
 * Registers after at least four clock cycles delay of the destination clock.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                          
 * :--------|:-------|:------|:--------------------------------------
 *  [15:0]  | RW     | 0x0   | Layer 4 Source Port Number Field     
 *  [31:16] | RW     | 0x0   | Layer 4 Destination Port Number Field
 * 
 */
/*
 * Field : Layer 4 Source Port Number Field - l4sp3
 * 
 * When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer
 * 3 and Layer 4 Control Register 3), this field contains the value to be matched
 * with the TCP Source Port Number field in the IPv4 or IPv6 frames.
 * 
 * When Bit 16 (L4PEN3) and Bit 20 (L4DPM3) are set in Register 292 (Layer 3 and
 * Layer 4 Control Register 3), this field contains the value to be matched with
 * the UDP Source Port Number field in the IPv4 or IPv6 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 field value from a register. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4SP3_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Layer 4 Destination Port Number Field - l4dp3
 * 
 * When Bit 16 (L4PEN3) is reset and Bit 20 (L4DPM3) is set in Register 292 (Layer
 * 3 and Layer 4 Control Register 3), this field contains the value to be matched
 * with the TCP Destination Port Number field in the IPv4 or IPv6 frames.
 * 
 * When Bit 16 (L4PEN3) and Bit 20 (L4DPM3) are set in Register 292 (Layer 3 and
 * Layer 4 Control Register 3), this field contains the value to be matched with
 * the UDP Destination Port Number field in the IPv4 or IPv6 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_SET_MSK    0xffff0000
/* The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_CLR_MSK    0x0000ffff
/* The reset value of the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 field value from a register. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_GET(value) (((value) & 0xffff0000) >> 16)
/* Produces a ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_L4DP3_SET(value) (((value) << 16) & 0xffff0000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR3.
 */
struct ALT_EMAC_GMAC_LYR4_ADDR3_s
{
    uint32_t  l4sp3 : 16;  /* Layer 4 Source Port Number Field */
    uint32_t  l4dp3 : 16;  /* Layer 4 Destination Port Number Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR3. */
typedef volatile struct ALT_EMAC_GMAC_LYR4_ADDR3_s  ALT_EMAC_GMAC_LYR4_ADDR3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR3 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_OFST        0x494
/* The address of the ALT_EMAC_GMAC_LYR4_ADDR3 register. */
#define ALT_EMAC_GMAC_LYR4_ADDR3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR3_OFST))

/*
 * Register : Register 296 (Layer 3 Address 0 Register 3) - Layer3_Addr0_Reg3
 * 
 * For IPv4 frames, the Layer 3 Address 0 Register 3 contains the 32-bit IP Source
 * Address field. For IPv6 frames, it contains Bits [31:0] of the 128-bit IP Source
 * Address or Destination Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 0 Field
 * 
 */
/*
 * Field : Layer 3 Address 0 Field - l3a03
 * 
 * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
 * Layer 4 Control Register 3), this field contains the value to be matched with
 * Bits [31:0] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
 * Layer 4 Control Register 3), this field contains the value to be matched with
 * Bits [31:0] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN3) is reset and Bit 2 (L3SAM3) is set in Register 292 (Layer 3
 * and Layer 4 Control Register 3), this field contains the value to be matched
 * with the IP Source Address field in the IPv4 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_L3A03_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG3.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR0_REG3_s
{
    uint32_t  l3a03 : 32;  /* Layer 3 Address 0 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG3. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR0_REG3_s  ALT_EMAC_GMAC_LYR3_ADDR0_REG3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_OFST        0x4a0
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG3 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG3_OFST))

/*
 * Register : Register 297 (Layer 3 Address 1 Register 3) - Layer3_Addr1_Reg3
 * 
 * For IPv4 frames, the Layer 3 Address 1 Register 3 contains the 32-bit IP
 * Destination Address field. For IPv6 frames, it contains Bits [63:32] of the
 * 128-bit IP Source Address or Destination Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 1 Field
 * 
 */
/*
 * Field : Layer 3 Address 1 Field - l3a13
 * 
 * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
 * Layer 4 Control Register 3), this field contains the value to be matched with
 * Bits [63:32] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
 * Layer 4 Control Register 3), this field contains the value to be matched with
 * Bits [63:32] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN3) is reset and Bit 4 (L3DAM3) is set in Register 292 (Layer 3
 * and Layer 4 Control Register 3), this field contains the value to be matched
 * with the IP Destination Address field in the IPv4 frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_L3A13_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG3.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR1_REG3_s
{
    uint32_t  l3a13 : 32;  /* Layer 3 Address 1 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR1_REG3. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR1_REG3_s  ALT_EMAC_GMAC_LYR3_ADDR1_REG3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_OFST        0x4a4
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR1_REG3 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR1_REG3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR1_REG3_OFST))

/*
 * Register : Register 298 (Layer 3 Address 2 Register 3) - Layer3_Addr2_Reg3
 * 
 * For IPv4 frames, the Layer 3 Address 2 Register 3 is reserved. For IPv6 frames,
 * it contains Bits [95:64] of the 128-bit IP Source Address or Destination Address
 * field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 2 Field
 * 
 */
/*
 * Field : Layer 3 Address 2 Field - l3a23
 * 
 * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
 * Layer 4 Control Register 3), this field contains the value to be matched with
 * Bits [95:64] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
 * Layer 4 Control Register 3), this field contains value to be matched with Bits
 * [95:64] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN3) is reset in Register 292 (Layer 3 and Layer 4 Control
 * Register 3), this register is not used.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_L3A23_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG3.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR2_REG3_s
{
    uint32_t  l3a23 : 32;  /* Layer 3 Address 2 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR2_REG3. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR2_REG3_s  ALT_EMAC_GMAC_LYR3_ADDR2_REG3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_OFST        0x4a8
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR2_REG3 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR2_REG3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR2_REG3_OFST))

/*
 * Register : Register 299 (Layer 3 Address 3 Register 3) - Layer3_Addr3_Reg3
 * 
 * For IPv4 frames, the Layer 3 Address 3 Register 3 is reserved. For IPv6 frames,
 * it contains Bits [127:96] of the 128-bit IP Source Address or Destination
 * Address field.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [31:0] | RW     | 0x0   | Layer 3 Address 3 Field
 * 
 */
/*
 * Field : Layer 3 Address 3 Field - l3a33
 * 
 * When Bit 0 (L3PEN3) and Bit 2 (L3SAM3) are set in Register 292 (Layer 3 and
 * Layer 4 Control Register 3), this field contains the value to be matched with
 * Bits [127:96] of the IP Source Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN3) and Bit 4 (L3DAM3) are set in Register 292 (Layer 3 and
 * Layer 4 Control Register 3), this field contains the value to be matched with
 * Bits [127:96] of the IP Destination Address field in the IPv6 frames.
 * 
 * When Bit 0 (L3PEN3) is reset in Register 292 (Layer 3 and Layer 4 Control
 * Register 3), this register is not used.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 field value from a register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_L3A33_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG3.
 */
struct ALT_EMAC_GMAC_LYR3_ADDR3_REG3_s
{
    uint32_t  l3a33 : 32;  /* Layer 3 Address 3 Field */
};

/* The typedef declaration for register ALT_EMAC_GMAC_LYR3_ADDR3_REG3. */
typedef volatile struct ALT_EMAC_GMAC_LYR3_ADDR3_REG3_s  ALT_EMAC_GMAC_LYR3_ADDR3_REG3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register from the beginning of the component. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_OFST        0x4ac
/* The address of the ALT_EMAC_GMAC_LYR3_ADDR3_REG3 register. */
#define ALT_EMAC_GMAC_LYR3_ADDR3_REG3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR3_REG3_OFST))

/*
 * Register : Register 320 (Hash Table Register 0) - Hash_Table_Reg0
 * 
 * This register contains the first 32 bits of the hash table.
 * 
 * The 256-bit Hash table is used for group address filtering. For hash filtering,
 * the content of the destination address in the incoming frame is passed through
 * the CRC logic and the upper eight bits of the CRC register are used to index the
 * content of the Hash table. The most significant bits determines the register to
 * be used (Hash Table Register X), and the least significant five bits determine
 * the bit within the register. For example, a hash value of 8b'10111111 selects
 * Bit 31 of the Hash Table Register 5.
 * 
 * The hash value of the destination address is calculated in the following way:
 * 
 * 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the
 * steps to calculate CRC32).
 * 
 * 2. Perform bitwise reversal for the value obtained in Step 1.
 * 
 * 3. Take the upper 8 bits from the value obtained in Step 2.
 * 
 * If the corresponding bit value of the register is 1'b1, the frame is accepted.
 * Otherwise, it is rejected. If the Bit 1 (Pass All Multicast) is set in Register
 * 1 (MAC Frame Filter), then all multicast frames are accepted regardless of the
 * multicast hash values.
 * 
 * Because the Hash Table register is double-synchronized to the (G)MII clock
 * domain, the synchronization is triggered only when Bits[31:24] (in little-endian
 * mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers
 * are written.
 * 
 * Note: Because of double-synchronization, consecutive writes to this register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                
 * :-------|:-------|:------|:----------------------------
 *  [31:0] | RW     | 0x0   | First 32 bits of Hash Table
 * 
 */
/*
 * Field : First 32 bits of Hash Table - ht31t0
 * 
 * This field contains the first 32 Bits (31:0) of the Hash table.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 field value from a register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG0.
 */
struct ALT_EMAC_GMAC_HASH_TABLE_REG0_s
{
    uint32_t  ht31t0 : 32;  /* First 32 bits of Hash Table */
};

/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG0. */
typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG0_s  ALT_EMAC_GMAC_HASH_TABLE_REG0_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register from the beginning of the component. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST        0x500
/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST))

/*
 * Register : Register 321 (Hash Table Register 1) - Hash_Table_Reg1
 * 
 * This register contains the second 32 bits of the hash table.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                 
 * :-------|:-------|:------|:-----------------------------
 *  [31:0] | RW     | 0x0   | Second 32 bits of Hash Table
 * 
 */
/*
 * Field : Second 32 bits of Hash Table - ht63t32
 * 
 * This field contains the second 32 Bits (63:32) of the Hash table.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 field value from a register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG1_HT63T32_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG1.
 */
struct ALT_EMAC_GMAC_HASH_TABLE_REG1_s
{
    uint32_t  ht63t32 : 32;  /* Second 32 bits of Hash Table */
};

/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG1. */
typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG1_s  ALT_EMAC_GMAC_HASH_TABLE_REG1_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register from the beginning of the component. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG1_OFST        0x504
/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG1 register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG1_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG1_OFST))

/*
 * Register : Register 322 (Hash Table Register 2) - Hash_Table_Reg2
 * 
 * This register contains the third 32 bits of the hash table.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                
 * :-------|:-------|:------|:----------------------------
 *  [31:0] | RW     | 0x0   | Third 32 bits of Hash Table
 * 
 */
/*
 * Field : Third 32 bits of Hash Table - ht95t64
 * 
 * This field contains the third 32 Bits (95:64) of the Hash table.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 field value from a register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG2_HT95T64_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG2.
 */
struct ALT_EMAC_GMAC_HASH_TABLE_REG2_s
{
    uint32_t  ht95t64 : 32;  /* Third 32 bits of Hash Table */
};

/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG2. */
typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG2_s  ALT_EMAC_GMAC_HASH_TABLE_REG2_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register from the beginning of the component. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG2_OFST        0x508
/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG2 register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG2_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG2_OFST))

/*
 * Register : Register 323 (Hash Table Register 3) - Hash_Table_Reg3
 * 
 * This register contains the fourth 32 bits of the hash table.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                 
 * :-------|:-------|:------|:-----------------------------
 *  [31:0] | RW     | 0x0   | Fourth 32 bits of Hash Table
 * 
 */
/*
 * Field : Fourth 32 bits of Hash Table - ht127t96
 * 
 * This field contains the fourth 32 Bits (127:96) of the Hash table.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 field value from a register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG3_HT127T96_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG3.
 */
struct ALT_EMAC_GMAC_HASH_TABLE_REG3_s
{
    uint32_t  ht127t96 : 32;  /* Fourth 32 bits of Hash Table */
};

/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG3. */
typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG3_s  ALT_EMAC_GMAC_HASH_TABLE_REG3_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register from the beginning of the component. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG3_OFST        0x50c
/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG3 register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG3_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG3_OFST))

/*
 * Register : Register 324 (Hash Table Register 4) - Hash_Table_Reg4
 * 
 * This register contains the fifth 32 bits of the hash table.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                
 * :-------|:-------|:------|:----------------------------
 *  [31:0] | RW     | 0x0   | Fifth 32 bits of Hash Table
 * 
 */
/*
 * Field : Fifth 32 bits of Hash Table - ht159t128
 * 
 * This field contains the fifth 32 Bits (159:128) of the Hash table.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 field value from a register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG4_HT159T128_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG4.
 */
struct ALT_EMAC_GMAC_HASH_TABLE_REG4_s
{
    uint32_t  ht159t128 : 32;  /* Fifth 32 bits of Hash Table */
};

/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG4. */
typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG4_s  ALT_EMAC_GMAC_HASH_TABLE_REG4_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register from the beginning of the component. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG4_OFST        0x510
/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG4 register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG4_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG4_OFST))

/*
 * Register : Register 325 (Hash Table Register 5) - Hash_Table_Reg5
 * 
 * This register contains the sixth 32 bits of the hash table.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                
 * :-------|:-------|:------|:----------------------------
 *  [31:0] | RW     | 0x0   | Sixth 32 bits of Hash Table
 * 
 */
/*
 * Field : Sixth 32 bits of Hash Table - ht191t160
 * 
 * This field contains the sixth 32 Bits (191:160) of the Hash table.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 field value from a register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG5_HT191T160_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG5.
 */
struct ALT_EMAC_GMAC_HASH_TABLE_REG5_s
{
    uint32_t  ht191t160 : 32;  /* Sixth 32 bits of Hash Table */
};

/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG5. */
typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG5_s  ALT_EMAC_GMAC_HASH_TABLE_REG5_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register from the beginning of the component. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG5_OFST        0x514
/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG5 register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG5_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG5_OFST))

/*
 * Register : Register 326 (Hash Table Register 6) - Hash_Table_Reg6
 * 
 * This register contains the seventh 32 bits of the hash table.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                  
 * :-------|:-------|:------|:------------------------------
 *  [31:0] | RW     | 0x0   | Seventh 32 bits of Hash Table
 * 
 */
/*
 * Field : Seventh 32 bits of Hash Table - ht223t196
 * 
 * This field contains the seventh 32 Bits (223:196) of the Hash table.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 field value from a register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG6_HT223T196_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG6.
 */
struct ALT_EMAC_GMAC_HASH_TABLE_REG6_s
{
    uint32_t  ht223t196 : 32;  /* Seventh 32 bits of Hash Table */
};

/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG6. */
typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG6_s  ALT_EMAC_GMAC_HASH_TABLE_REG6_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register from the beginning of the component. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG6_OFST        0x518
/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG6 register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG6_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG6_OFST))

/*
 * Register : Register 327 (Hash Table Register 7) - Hash_Table_Reg7
 * 
 * This register contains the eighth 32 bits of the hash table.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                 
 * :-------|:-------|:------|:-----------------------------
 *  [31:0] | RW     | 0x0   | Eighth 32 bits of Hash Table
 * 
 */
/*
 * Field : Eighth 32 bits of Hash Table - ht255t224
 * 
 * This field contains the eighth 32 Bits (255:224) of the Hash table.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 field value from a register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG7_HT255T224_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG7.
 */
struct ALT_EMAC_GMAC_HASH_TABLE_REG7_s
{
    uint32_t  ht255t224 : 32;  /* Eighth 32 bits of Hash Table */
};

/* The typedef declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG7. */
typedef volatile struct ALT_EMAC_GMAC_HASH_TABLE_REG7_s  ALT_EMAC_GMAC_HASH_TABLE_REG7_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register from the beginning of the component. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG7_OFST        0x51c
/* The address of the ALT_EMAC_GMAC_HASH_TABLE_REG7 register. */
#define ALT_EMAC_GMAC_HASH_TABLE_REG7_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG7_OFST))

/*
 * Register : Register 353 (VLAN Tag Inclusion or Replacement Register) - VLAN_Incl_Reg
 * 
 * The VLAN Tag Inclusion or Replacement register contains the VLAN tag for
 * insertion or replacement in the transmit frames.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset   | Description                        
 * :--------|:-------|:--------|:------------------------------------
 *  [15:0]  | RW     | Unknown | VLAN Tag for Transmit Frames       
 *  [17:16] | RW     | Unknown | VLAN Tag Control in Transmit Frames
 *  [18]    | RW     | Unknown | VLAN Priority Control              
 *  [19]    | RW     | Unknown | C-VLAN or S-VLAN                   
 *  [31:20] | ???    | 0x0     | *UNDEFINED*                        
 * 
 */
/*
 * Field : VLAN Tag for Transmit Frames - vlt
 * 
 * This field contains the value of the VLAN tag to be inserted or replaced. The
 * value must only be changed when the transmit lines are inactive or during the
 * initialization phase. Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI,
 * and Bits[11:0] are the VLAN tag's VID field.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field is UNKNOWN. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLT field value from a register. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLT_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : VLAN Tag Control in Transmit Frames - vlc
 * 
 * * 2'b00: No VLAN tag deletion, insertion, or replacement
 * 
 * * 2'b01: VLAN tag deletion
 * 
 * The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16)
 * of all transmitted frames with VLAN tags.
 * 
 * * 2'b10: VLAN tag insertion
 * 
 * The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type
 * value (0x8100/0x88a8) in bytes 13 and 14. This operation is performed on all
 * transmitted frames, irrespective of whether they already have a VLAN tag.
 * 
 * * 2'b11: VLAN tag replacement
 * 
 * The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames
 * (Bytes 13 and 14 are 0x8100/0x88a8).
 * 
 * Note: Changes to this field take effect only on the start of a frame. If you
 * write this register field when a frame is being transmitted, only the subsequent
 * frame can use the updated value, that is, the current frame does not use the
 * updated value.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_MSB        17
/* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_SET_MSK    0x00030000
/* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_CLR_MSK    0xfffcffff
/* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field is UNKNOWN. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLC field value from a register. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_GET(value) (((value) & 0x00030000) >> 16)
/* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLC register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLC_SET(value) (((value) << 16) & 0x00030000)

/*
 * Field : VLAN Priority Control - vlp
 * 
 * When this bit is set, the control Bits [17:16] are used for VLAN deletion,
 * insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control
 * input is used, and Bits [17:16] are ignored.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field is UNKNOWN. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_VLP field value from a register. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_VLP register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_VLP_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : C-VLAN or S-VLAN - csvl
 * 
 * When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th
 * and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type
 * (0x8100) is inserted or replaced in the transmitted frames.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field is UNKNOWN. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL field value from a register. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_CSVL_SET(value) (((value) << 19) & 0x00080000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_VLAN_INCL_REG.
 */
struct ALT_EMAC_GMAC_VLAN_INCL_REG_s
{
    uint32_t  vlt  : 16;  /* VLAN Tag for Transmit Frames */
    uint32_t  vlc  :  2;  /* VLAN Tag Control in Transmit Frames */
    uint32_t  vlp  :  1;  /* VLAN Priority Control */
    uint32_t  csvl :  1;  /* C-VLAN or S-VLAN */
    uint32_t       : 12;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_VLAN_INCL_REG. */
typedef volatile struct ALT_EMAC_GMAC_VLAN_INCL_REG_s  ALT_EMAC_GMAC_VLAN_INCL_REG_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_VLAN_INCL_REG register from the beginning of the component. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_OFST        0x584
/* The address of the ALT_EMAC_GMAC_VLAN_INCL_REG register. */
#define ALT_EMAC_GMAC_VLAN_INCL_REG_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_INCL_REG_OFST))

/*
 * Register : Register 354 (VLAN Hash Table Register) - VLAN_Hash_Table_Reg
 * 
 * The 16-bit Hash table is used for group address filtering based on VLAN tag when
 * Bit 18 (VTHM) of Register 7 (VLAN Tag Register) is set. For hash filtering, the
 * content of the 16-bit VLAN tag or 12-bit VLAN ID (based on Bit 16 (ETV) of VLAN
 * Tag Register) in the incoming frame is passed through the CRC logic and the
 * upper four bits of the calculated CRC are used to index the contents of the VLAN
 * Hash table. For example, a hash value of 4b'1000 selects Bit 8 of the VLAN Hash
 * table.
 * 
 * The hash value of the destination address is calculated in the following way:
 * 
 * 1. Calculate the 32-bit CRC for the VLAN tag or ID (See IEEE 802.3, Section
 * 3.2.8 for the steps to calculate CRC32).
 * 
 * 2. Perform bitwise reversal for the value obtained in Step 1.
 * 
 * 3. Take the upper four bits from the value obtained in Step 2.
 * 
 * If the corresponding bit value of the register is 1'b1, the frame is accepted.
 * Otherwise, it is rejected. Because the Hash Table register is double-
 * synchronized to the (G)MII clock domain, the synchronization is triggered only
 * when Bits[15:8] (in little-endian mode) or Bits[7:0] (in big-endian mode) of
 * this register are written.
 * 
 * Notes:
 * 
 * * Because of double-synchronization, consecutive writes to this register should
 *   be performed after at least four clock cycles in the destination clock domain.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description    
 * :--------|:-------|:------|:----------------
 *  [15:0]  | RW     | 0x0   | VLAN Hash Table
 *  [31:16] | ???    | 0x0   | *UNDEFINED*    
 * 
 */
/*
 * Field : VLAN Hash Table - vlht
 * 
 * This field contains the 16-bit VLAN Hash Table.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value. */
#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value. */
#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field. */
#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT field value from a register. */
#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_VLHT_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG.
 */
struct ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_s
{
    uint32_t  vlht : 16;  /* VLAN Hash Table */
    uint32_t       : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG. */
typedef volatile struct ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_s  ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register from the beginning of the component. */
#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_OFST        0x588
/* The address of the ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG register. */
#define ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_OFST))

/*
 * Register : Register 448 (Timestamp Control Register) - Timestamp_Control
 * 
 * This register controls the operation of the System Time generator and the
 * processing of PTP packets for timestamping in the Receiver.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                       
 * :--------|:-------|:------|:---------------------------------------------------
 *  [0]     | RW     | 0x0   | Timestamp Enable                                  
 *  [1]     | RW     | 0x0   | Timestamp Fine or Coarse Update                   
 *  [2]     | RW     | 0x0   | Timestamp Initialize                              
 *  [3]     | RW     | 0x0   | Timestamp Update                                  
 *  [4]     | RW     | 0x0   | Timestamp Interrupt Trigger Enable                
 *  [5]     | RW     | 0x0   | Addend Reg Update                                 
 *  [7:6]   | ???    | 0x0   | *UNDEFINED*                                       
 *  [8]     | RW     | 0x0   | Enable Timestamp for All Frames                   
 *  [9]     | RW     | 0x0   | Timestamp Digital or Binary Rollover Control      
 *  [10]    | RW     | 0x0   | Enable PTP packet Processing for Version 2 Format 
 *  [11]    | RW     | 0x0   | Enable Processing of PTP over Ethernet Frames     
 *  [12]    | RW     | 0x0   | Enable Processing of PTP Frames Sent Over IPv6-UDP
 *  [13]    | RW     | 0x1   | Enable Processing of PTP Frames Sent over IPv4-UDP
 *  [14]    | RW     | 0x0   | Enable Timestamp Snapshot for Event Messages      
 *  [15]    | RW     | 0x0   | Enable Snapshot for Messages Relevant to Master   
 *  [17:16] | RW     | 0x0   | Select PTP packets for Taking Snapshots           
 *  [18]    | RW     | 0x0   | Enable MAC address for PTP Frame Filtering        
 *  [23:19] | ???    | 0x0   | *UNDEFINED*                                       
 *  [24]    | RW     | 0x0   | Auxiliary Snapshot FIFO Clear                     
 *  [25]    | RW     | 0x0   | Auxiliary Snapshot 0 Enable                       
 *  [31:26] | ???    | 0x0   | *UNDEFINED*                                       
 * 
 */
/*
 * Field : Timestamp Enable - tsena
 * 
 * When set, the timestamp is added for the transmit and receive frames. When
 * disabled, timestamp is not added for the transmit and receive frames and the
 * Timestamp Generator is also suspended. You need to initialize the Timestamp
 * (system time) after enabling this mode.
 * 
 * On the receive side, the MAC processes the 1588 frames only if this bit is set.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                             
 * :----------------------------------|:------|:-----------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS | 0x0   | Timestamp not added                     
 *  ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS   | 0x1   | Timestamp added for transmit and receive
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA
 * 
 * Timestamp not added
 */
#define ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA
 * 
 * Timestamp added for transmit and receive
 */
#define ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENA_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENA_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSENA_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSENA_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENA field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSENA_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSENA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSENA_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Timestamp Fine or Coarse Update - tscfupdt
 * 
 * When set, this bit indicates that the system times update should be done using
 * the fine update method. When reset, it indicates the system timestamp update
 * should be done using the Coarse method.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description     
 * :------------------------------------------|:------|:-----------------
 *  ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE | 0x0   | Timestamp Coarse
 *  ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE   | 0x1   | Timestamp Fine  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT
 * 
 * Timestamp Coarse
 */
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT
 * 
 * Timestamp Fine
 */
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Timestamp Initialize - tsinit
 * 
 * When set, the system time is initialized (overwritten) with the value specified
 * in the Register 452 (System Time - Seconds Update Register) and Register 453
 * (System Time - Nanoseconds Update Register).
 * 
 * This bit should be read zero before updating it. This bit is reset when the
 * initialization is complete. The Timestamp Higher Word register can only be
 * initialized.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                                     
 * :----------------------------------------|:------|:-------------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT | 0x0   | Timestamp not initialized (overwritten) by      
 * :                                        |       | values in Register 452 and Register 453         
 *  ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT   | 0x1   | Timestamp initialized (overwritten) by values in
 * :                                        |       | Register 452 and Register 453                   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT
 * 
 * Timestamp not initialized (overwritten) by values in Register 452 and Register
 * 453
 */
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT
 * 
 * Timestamp initialized (overwritten) by values in Register 452 and Register 453
 */
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSINIT field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSINIT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timestamp Update - tsupdt
 * 
 * When set, the system time is updated (added or subtracted) with the value
 * specified in Register 452 (System Time - Seconds Update Register) and Register
 * 453 (System Time - Nanoseconds Update Register).
 * 
 * This bit should be read zero before updating it. This bit is reset when the
 * update is completed in hardware. The Timestamp Higher Word register is not
 * updated.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                       | Value | Description                                     
 * :-------------------------------------------|:------|:-------------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED | 0x0   | Timestamp not updated (added or subtracted) with
 * :                                           |       | values in Register 452 and Register 453         
 *  ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED   | 0x1   | Timestamp updated (added or subtracted) with    
 * :                                           |       | values in Register 452 and Register 453         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT
 * 
 * Timestamp not updated (added or subtracted) with values in Register 452 and
 * Register 453
 */
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT
 * 
 * Timestamp updated (added or subtracted) with values in Register 452 and Register
 * 453
 */
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSUPDT field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Timestamp Interrupt Trigger Enable - tstrig
 * 
 * When set, the timestamp interrupt is generated when the System Time becomes
 * greater than the value written in the Target Time register. This bit is reset
 * after the generation of the Timestamp Trigger Interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description            
 * :------------------------------------------------|:------|:------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN | 0x0   | Timestamp not generated
 *  ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN   | 0x1   | Timestamp generated    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG
 * 
 * Timestamp not generated
 */
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG
 * 
 * Timestamp generated
 */
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSTRIG field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Addend Reg Update - tsaddreg
 * 
 * When set, the content of the Timestamp Addend register is updated in the PTP
 * block for fine correction. This is cleared when the update is completed. This
 * register bit should be zero before setting it.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                | Value | Description                             
 * :----------------------------------------------------|:------|:-----------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED | 0x0   | Timestamp Addend register is not updated
 *  ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED   | 0x1   | Timestamp Addend register is updated    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG
 * 
 * Timestamp Addend register is not updated
 */
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG
 * 
 * Timestamp Addend register is updated
 */
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_MSB        5
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSADDREG field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Enable Timestamp for All Frames - tsenall
 * 
 * When set, the timestamp snapshot is enabled for all frames received by the MAC.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                
 * :------------------------------------|:------|:----------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD | 0x0   | Timestamp snapshot disabled
 *  ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END  | 0x1   | Timestamp snapshot enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL
 * 
 * Timestamp snapshot disabled
 */
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL
 * 
 * Timestamp snapshot enabled
 */
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_MSB        8
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENALL field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSENALL register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Timestamp Digital or Binary Rollover Control - tsctrlssr
 * 
 * When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that
 * is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When
 * reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second
 * increment has to be programmed correctly depending on the PTP reference clock
 * frequency and the value of this bit.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description                                     
 * :--------------------------------------------------|:------|:-------------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX | 0x0   | Timestamp Low register rolls over at 0x7FFF_FFFF
 *  ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS   | 0x1   | Timestamp Low register rolls over at 1ns        
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR
 * 
 * Timestamp Low register rolls over at 0x7FFF_FFFF
 */
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR
 * 
 * Timestamp Low register rolls over at 1ns
 */
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_MSB        9
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Enable PTP packet Processing for Version 2 Format - tsver2ena
 * 
 * When set, the PTP packets are processed using the 1588 version 2 format.
 * Otherwise, the PTP packets are processed using the version 1 format.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                                     
 * :-----------------------------------------------|:------|:-------------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 | 0x0   | PTP packets processed with 1588 version 1 format
 *  ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 | 0x1   | PTP packets processed with 1588 version 2 format
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA
 * 
 * PTP packets processed with 1588 version 1 format
 */
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA
 * 
 * PTP packets processed with 1588 version 2 format
 */
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_MSB        10
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : Enable Processing of PTP over Ethernet Frames - tsipena
 * 
 * When set, the MAC receiver processes the PTP packets encapsulated directly in
 * the Ethernet frames. When this bit is clear, the MAC ignores the PTP over
 * Ethernet packets.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                                 
 * :----------------------------------------------|:------|:---------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP | 0x0   | Don't process PTP packets in Ethernet frames
 *  ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP    | 0x1   | Process PTP packets in Ethernet frames      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA
 * 
 * Don't process PTP packets in Ethernet frames
 */
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA
 * 
 * Process PTP packets in Ethernet frames
 */
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_MSB        11
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET_MSK    0x00000800
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPENA field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : Enable Processing of PTP Frames Sent Over IPv6-UDP - tsipv6ena
 * 
 * When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6
 * packets. When this bit is clear, the MAC ignores the PTP transported over UDP-
 * IPv6 packets.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description                               
 * :------------------------------------------------|:------|:-------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP | 0x0   | Don't process PTP packets in UDP over IPv6
 *  ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP    | 0x1   | Process PTP packets in UDP over IPv6      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA
 * 
 * Don't process PTP packets in UDP over IPv6
 */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA
 * 
 * Process PTP packets in UDP over IPv6
 */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_MSB        12
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET_MSK    0x00001000
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_CLR_MSK    0xffffefff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : Enable Processing of PTP Frames Sent over IPv4-UDP - tsipv4ena
 * 
 * When set, the MAC receiver processes the PTP packets encapsulated in UDP over
 * IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over
 * UDP-IPv4 packets. This bit is set by default.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                            | Value | Description                               
 * :------------------------------------------------|:------|:-------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP | 0x0   | Don't process PTP packets in UDP over IPv4
 *  ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP    | 0x1   | Process PTP packets in UDP over IPv4      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA
 * 
 * Don't process PTP packets in UDP over IPv4
 */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA
 * 
 * Process PTP packets in UDP over IPv4
 */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_MSB        13
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_RESET      0x1
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : Enable Timestamp Snapshot for Event Messages - tsevntena
 * 
 * When set, the timestamp snapshot is taken only for event messages (SYNC,
 * Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for
 * all messages except Announce, Management, and Signaling.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                                   
 * :--------------------------------------|:------|:-----------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD | 0x0   | Timestamp snapshot disabled for event messages
 *  ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END  | 0x1   | Timestamp snapshot only for event messages    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA
 * 
 * Timestamp snapshot disabled for event messages
 */
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA
 * 
 * Timestamp snapshot only for event messages
 */
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_MSB        14
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET_MSK    0x00004000
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_CLR_MSK    0xffffbfff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : Enable Snapshot for Messages Relevant to Master - tsmstrena
 * 
 * When set, the snapshot is taken only for the messages relevant to the master
 * node. Otherwise, the snapshot is taken for the messages relevant to the slave
 * node.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                                   
 * :-------------------------------------|:------|:-----------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV | 0x0   | Timestamp snapshot taken for messages relevant
 * :                                     |       | to slave node                                 
 *  ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST | 0x1   | Timestamp snapshot taken for messages relevant
 * :                                     |       | to master node                                
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA
 * 
 * Timestamp snapshot taken for messages relevant to slave node
 */
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA
 * 
 * Timestamp snapshot taken for messages relevant to master node
 */
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET_MSK    0x00008000
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_CLR_MSK    0xffff7fff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Select PTP packets for Taking Snapshots - snaptypsel
 * 
 * These bits along with Bits 15 and 14 decide the set of PTP packet types for
 * which snapshot needs to be taken.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_MSB        17
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value. */
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET_MSK    0x00030000
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value. */
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_CLR_MSK    0xfffcffff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field. */
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_GET(value) (((value) & 0x00030000) >> 16)
/* Produces a ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET(value) (((value) << 16) & 0x00030000)

/*
 * Field : Enable MAC address for PTP Frame Filtering - tsenmacaddr
 * 
 * When set, the DA MAC address (that matches any MAC Address register) is used to
 * filter the PTP frames when PTP is directly sent over Ethernet.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                             
 * :----------------------------------------|:------|:-----------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD | 0x0   | DA MAC address doesn't filter PTP frames
 *  ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END  | 0x1   | DA MAC address filters PTP frames       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR
 * 
 * DA MAC address doesn't filter PTP frames
 */
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR
 * 
 * DA MAC address filters PTP frames
 */
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_MSB        18
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value. */
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field. */
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : Auxiliary Snapshot FIFO Clear - atsfc
 * 
 * When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is
 * cleared when the pointers are reset and the FIFO is empty. When this bit is
 * high, auxiliary snapshots get stored in the FIFO.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                                 
 * :----------------------------------|:------|:---------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD | 0x0   | Don't reset Auxiliary Snapshot FIFO pointers
 *  ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END  | 0x1   | Reset Auxiliary Snapshot FIFO pointers      
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC
 * 
 * Don't reset Auxiliary Snapshot FIFO pointers
 */
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC
 * 
 * Reset Auxiliary Snapshot FIFO pointers
 */
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value. */
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value. */
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field. */
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSFC field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_TS_CTL_ATSFC register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Auxiliary Snapshot 0 Enable - atsen0
 * 
 * This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is
 * set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When
 * this bit is reset, the events on this input are ignored.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                                     
 * :-----------------------------------|:------|:-------------------------------------------------
 *  ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD | 0x0   | Auxiliary snapshot of event on ptp_aux_trig_i[0]
 * :                                   |       | input is disabled.                              
 *  ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END  | 0x1   | Auxiliary snapshot of event on ptp_aux_trig_i[0]
 * :                                   |       | input is enabled.                               
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0
 * 
 * Auxiliary snapshot of event on ptp_aux_trig_i[0] input is disabled.
 */
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0
 * 
 * Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled.
 */
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value. */
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value. */
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field. */
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN0 field value from a register. */
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET(value) (((value) << 25) & 0x02000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TS_CTL.
 */
struct ALT_EMAC_GMAC_TS_CTL_s
{
    uint32_t  tsena       :  1;  /* Timestamp Enable */
    uint32_t  tscfupdt    :  1;  /* Timestamp Fine or Coarse Update */
    uint32_t  tsinit      :  1;  /* Timestamp Initialize */
    uint32_t  tsupdt      :  1;  /* Timestamp Update */
    uint32_t  tstrig      :  1;  /* Timestamp Interrupt Trigger Enable */
    uint32_t  tsaddreg    :  1;  /* Addend Reg Update */
    uint32_t              :  2;  /* *UNDEFINED* */
    uint32_t  tsenall     :  1;  /* Enable Timestamp for All Frames */
    uint32_t  tsctrlssr   :  1;  /* Timestamp Digital or Binary Rollover Control */
    uint32_t  tsver2ena   :  1;  /* Enable PTP packet Processing for Version 2 Format */
    uint32_t  tsipena     :  1;  /* Enable Processing of PTP over Ethernet Frames */
    uint32_t  tsipv6ena   :  1;  /* Enable Processing of PTP Frames Sent Over IPv6-UDP */
    uint32_t  tsipv4ena   :  1;  /* Enable Processing of PTP Frames Sent over IPv4-UDP */
    uint32_t  tsevntena   :  1;  /* Enable Timestamp Snapshot for Event Messages */
    uint32_t  tsmstrena   :  1;  /* Enable Snapshot for Messages Relevant to Master */
    uint32_t  snaptypsel  :  2;  /* Select PTP packets for Taking Snapshots */
    uint32_t  tsenmacaddr :  1;  /* Enable MAC address for PTP Frame Filtering */
    uint32_t              :  5;  /* *UNDEFINED* */
    uint32_t  atsfc       :  1;  /* Auxiliary Snapshot FIFO Clear */
    uint32_t  atsen0      :  1;  /* Auxiliary Snapshot 0 Enable */
    uint32_t              :  6;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TS_CTL. */
typedef volatile struct ALT_EMAC_GMAC_TS_CTL_s  ALT_EMAC_GMAC_TS_CTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TS_CTL register from the beginning of the component. */
#define ALT_EMAC_GMAC_TS_CTL_OFST        0x700
/* The address of the ALT_EMAC_GMAC_TS_CTL register. */
#define ALT_EMAC_GMAC_TS_CTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_CTL_OFST))

/*
 * Register : Register 449 (Sub-Second Increment Register) - Sub_Second_Increment
 * 
 * In the Coarse Update mode (TSCFUPDT bit in Register 448), the value in this
 * register is added to the system time every clock cycle of clk_ptp_ref_i. In the
 * Fine Update mode, the value in this register is added to the system time
 * whenever the Accumulator gets an overflow.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description               
 * :-------|:-------|:------|:---------------------------
 *  [7:0]  | RW     | 0x0   | Sub-second Increment Value
 *  [31:8] | ???    | 0x0   | *UNDEFINED*               
 * 
 */
/*
 * Field : Sub-second Increment Value - ssinc
 * 
 * The value programmed in this field is accumulated every clock cycle (of
 * clk_ptp_i) with the contents of the sub-second register. For example, when PTP
 * clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System
 * Time-Nanoseconds register has an accuracy of 1 ns (TSCTRLSSR bit is set). When
 * TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In
 * this case, you should program a value of 43 (0x2B) that is derived by
 * 20ns/0.465.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_MSB        7
/* The width in bits of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_WIDTH      8
/* The mask used to set the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value. */
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET_MSK    0x000000ff
/* The mask used to clear the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value. */
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_CLR_MSK    0xffffff00
/* The reset value of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field. */
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC field value from a register. */
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_GET(value) (((value) & 0x000000ff) >> 0)
/* Produces a ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET(value) (((value) << 0) & 0x000000ff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_SUB_SEC_INCREMENT.
 */
struct ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s
{
    uint32_t  ssinc :  8;  /* Sub-second Increment Value */
    uint32_t        : 24;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_SUB_SEC_INCREMENT. */
typedef volatile struct ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s  ALT_EMAC_GMAC_SUB_SEC_INCREMENT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register from the beginning of the component. */
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST        0x704
/* The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register. */
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST))

/*
 * Register : Register 450 (System Time - Seconds Register) - System_Time_Seconds
 * 
 * The System Time -Seconds register, along with System-TimeNanoseconds register,
 * indicates the current value of the system time maintained by the MAC. Though it
 * is updated on a continuous basis, there is some delay from the actual time
 * because of clock domain transfer latencies (from clk_ptp_ref_i to l3_sp_clk).
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | R      | 0x0   | Timestamp Second
 * 
 */
/*
 * Field : Timestamp Second - tss
 * 
 * The value in this field indicates the current value in seconds of the System
 * Time maintained by the MAC.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_SYS_TIME_SECS_TSS field value from a register. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_SYS_TIME_SECS_TSS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_TSS_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS.
 */
struct ALT_EMAC_GMAC_SYS_TIME_SECS_s
{
    const uint32_t  tss : 32;  /* Timestamp Second */
};

/* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS. */
typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_SECS_s  ALT_EMAC_GMAC_SYS_TIME_SECS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_SECS register from the beginning of the component. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_OFST        0x708
/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS register. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_SECS_OFST))

/*
 * Register : Register 451 (System Time - Nanoseconds Register) - System_Time_Nanoseconds
 * 
 * The value in this field has the sub second representation of time, with an
 * accuracy of 0.46 ns. When TSCTRLSSR is set, each bit represents 1 ns and the
 * maximum value is 0x3B9A_C9FF, after which it rolls-over to zero.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description          
 * :-------|:-------|:------|:----------------------
 *  [30:0] | R      | 0x0   | Timestamp Sub Seconds
 *  [31]   | ???    | 0x0   | *UNDEFINED*          
 * 
 */
/*
 * Field : Timestamp Sub Seconds - tsss
 * 
 * The value in this field has the sub second representation of time, with an
 * accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp
 * Control Register), each bit represents 1 ns and the maximum value is
 * 0x3B9A_C9FF, after which it rolls-over to zero.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_WIDTH      31
/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_SET_MSK    0x7fffffff
/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_CLR_MSK    0x80000000
/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS field value from a register. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_GET(value) (((value) & 0x7fffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_TSSS_SET(value) (((value) << 0) & 0x7fffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS.
 */
struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_s
{
    const uint32_t  tsss : 31;  /* Timestamp Sub Seconds */
    uint32_t             :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS. */
typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_s  ALT_EMAC_GMAC_SYS_TIME_NANOSECS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register from the beginning of the component. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_OFST        0x70c
/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS register. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_NANOSECS_OFST))

/*
 * Register : Register 452 (System Time - Seconds Update Register) - System_Time_Seconds_Update
 * 
 * The System Time - Seconds Update register, along with the System Time -
 * Nanoseconds Update register, initializes or updates the system time maintained
 * by the MAC. You must write both of these registers before setting the TSINIT or
 * TSUPDT bits in the Timestamp Control register.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description     
 * :-------|:-------|:------|:-----------------
 *  [31:0] | RW     | 0x0   | Timestamp Second
 * 
 */
/*
 * Field : Timestamp Second - tss
 * 
 * The value in this field indicates the time in seconds to be initialized or added
 * to the system time.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS field value from a register. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_TSS_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE.
 */
struct ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_s
{
    uint32_t  tss : 32;  /* Timestamp Second */
};

/* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE. */
typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_s  ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register from the beginning of the component. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_OFST        0x710
/* The address of the ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE register. */
#define ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_OFST))

/*
 * Register : Register 453 (System Time - Nanoseconds Update Register) - System_Time_Nanoseconds_Update
 * 
 * Update system time
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description         
 * :-------|:-------|:------|:---------------------
 *  [30:0] | RW     | 0x0   | Timestamp Sub Second
 *  [31]   | RW     | 0x0   | Add or subtract time
 * 
 */
/*
 * Field : Timestamp Sub Second - tsss
 * 
 * The value in this field has the sub second representation of time, with an
 * accuracy of 0.46 ns. When bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp
 * Control Register), each bit represents 1 ns and the programmed value should not
 * exceed 0x3B9A_C9FF.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_WIDTH      31
/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_SET_MSK    0x7fffffff
/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_CLR_MSK    0x80000000
/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS field value from a register. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_GET(value) (((value) & 0x7fffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_TSSS_SET(value) (((value) << 0) & 0x7fffffff)

/*
 * Field : Add or subtract time - addsub
 * 
 * When this bit is set, the time value is subtracted with the contents of the
 * update register. When this bit is reset, the time value is added with the
 * contents of the update register.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                                 | Value | Description                      
 * :-----------------------------------------------------|:------|:----------------------------------
 *  ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_DISD | 0x0   | Add Time Value from update reg   
 *  ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_END  | 0x1   | Subtract Time Value of update reg
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB
 * 
 * Add Time Value from update reg
 */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB
 * 
 * Subtract Time Value of update reg
 */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB field value from a register. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDSUB_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE.
 */
struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_s
{
    uint32_t  tsss   : 31;  /* Timestamp Sub Second */
    uint32_t  addsub :  1;  /* Add or subtract time */
};

/* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE. */
typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_s  ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register from the beginning of the component. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_OFST        0x714
/* The address of the ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE register. */
#define ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_OFST))

/*
 * Register : Register 454 (Timestamp Addend Register) - Timestamp_Addend
 * 
 * This register value is used only when the system time is configured for Fine
 * Update mode (TSCFUPDT bit in Register 448). This register content is added to a
 * 32-bit accumulator in every clock cycle (of clk_ptp_ref_i) and the system time
 * is updated whenever the accumulator overflows.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description              
 * :-------|:-------|:------|:--------------------------
 *  [31:0] | RW     | 0x0   | Timestamp Addend Register
 * 
 */
/*
 * Field : Timestamp Addend Register - tsar
 * 
 * This field indicates the 32-bit time value to be added to the Accumulator
 * register to achieve time synchronization.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value. */
#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value. */
#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TS_ADDEND_TSAR register field. */
#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_ADDEND_TSAR field value from a register. */
#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TS_ADDEND_TSAR register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_ADDEND_TSAR_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TS_ADDEND.
 */
struct ALT_EMAC_GMAC_TS_ADDEND_s
{
    uint32_t  tsar : 32;  /* Timestamp Addend Register */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TS_ADDEND. */
typedef volatile struct ALT_EMAC_GMAC_TS_ADDEND_s  ALT_EMAC_GMAC_TS_ADDEND_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TS_ADDEND register from the beginning of the component. */
#define ALT_EMAC_GMAC_TS_ADDEND_OFST        0x718
/* The address of the ALT_EMAC_GMAC_TS_ADDEND register. */
#define ALT_EMAC_GMAC_TS_ADDEND_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_ADDEND_OFST))

/*
 * Register : Register 455 (Target Time Seconds Register) - Target_Time_Seconds
 * 
 * The Target Time Seconds register, along with Target Time Nanoseconds register,
 * is used to schedule an interrupt event (Register 458[1] when Advanced
 * Timestamping is enabled; otherwise, TS interrupt bit in Register14[9]) when the
 * system time exceeds the value programmed in these registers.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                 
 * :-------|:-------|:------|:-----------------------------
 *  [31:0] | RW     | 0x0   | Target Time Seconds Register
 * 
 */
/*
 * Field : Target Time Seconds Register - tstr
 * 
 * This register stores the time in seconds. When the timestamp value matches or
 * exceeds both Target Timestamp registers, then based on Bits [6:5] of Register
 * 459 (PPS Control Register), the MAC starts or stops the PPS signal output and
 * generates an interrupt (if enabled).
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value. */
#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value. */
#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field. */
#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR field value from a register. */
#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TGT_TIME_SECS_TSTR_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TGT_TIME_SECS.
 */
struct ALT_EMAC_GMAC_TGT_TIME_SECS_s
{
    uint32_t  tstr : 32;  /* Target Time Seconds Register */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TGT_TIME_SECS. */
typedef volatile struct ALT_EMAC_GMAC_TGT_TIME_SECS_s  ALT_EMAC_GMAC_TGT_TIME_SECS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TGT_TIME_SECS register from the beginning of the component. */
#define ALT_EMAC_GMAC_TGT_TIME_SECS_OFST        0x71c
/* The address of the ALT_EMAC_GMAC_TGT_TIME_SECS register. */
#define ALT_EMAC_GMAC_TGT_TIME_SECS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TGT_TIME_SECS_OFST))

/*
 * Register : Register 456 (Target Time Nanoseconds Register) - Target_Time_Nanoseconds
 * 
 * Target time
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                  
 * :-------|:-------|:------|:------------------------------
 *  [30:0] | RW     | 0x0   | Target Timestamp Low Register
 *  [31]   | R      | 0x0   | Target Time Register Busy    
 * 
 */
/*
 * Field : Target Timestamp Low Register - ttslo
 * 
 * This register stores the time in (signed) nanoseconds. When the value of the
 * timestamp matches the both Target Timestamp registers, then based on the
 * TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC
 * starts or stops the PPS signal output and generates an interrupt (if enabled).
 * 
 * This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Timestamp
 * control register. The actual start or stop time of the PPS signal output may
 * have an error margin up to one unit of sub-second increment value.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_WIDTH      31
/* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET_MSK    0x7fffffff
/* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_CLR_MSK    0x80000000
/* The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO field value from a register. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_GET(value) (((value) & 0x7fffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET(value) (((value) << 0) & 0x7fffffff)

/*
 * Field : Target Time Register Busy - trgtbusy
 * 
 * The MAC sets this bit when the PPSCMD field (Bits[3:0]) in Register 459 (PPS
 * Control Register) is programmed to 010 or 011. Programming the PPSCMD field to
 * 010 or 011, instructs the MAC to synchronize the Target Time Registers to the
 * PTP clock domain.
 * 
 * The MAC clears this bit after synchronizing the Target Time Registers to the PTP
 * clock domain The application must not update the Target Time Registers when this
 * bit is read as 1. Otherwise, the synchronization of the previous programmed time
 * gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second
 * Output feature is not selected.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY field value from a register. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TGT_TIME_NANOSECS.
 */
struct ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s
{
    uint32_t        ttslo    : 31;  /* Target Timestamp Low Register */
    const uint32_t  trgtbusy :  1;  /* Target Time Register Busy */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TGT_TIME_NANOSECS. */
typedef volatile struct ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s  ALT_EMAC_GMAC_TGT_TIME_NANOSECS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register from the beginning of the component. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST        0x720
/* The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register. */
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST))

/*
 * Register : Register 457 (System Time - Higher Word Seconds Register) - System_Time_Higher_Word_Seconds
 * 
 * System time higher word
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                   
 * :--------|:-------|:------|:-------------------------------
 *  [15:0]  | RW     | 0x0   | Timestamp Higher Word Register
 *  [31:16] | ???    | 0x0   | *UNDEFINED*                   
 * 
 */
/*
 * Field : Timestamp Higher Word Register - tshwr
 * 
 * This field contains the most significant 16-bits of the timestamp seconds value.
 * The register is directly written to initialize the value. This register is
 * incremented when there is an overflow from the 32-bits of the System Time -
 * Seconds register.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value. */
#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field. */
#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR field value from a register. */
#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_TSHWR_SET(value) (((value) << 0) & 0x0000ffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS.
 */
struct ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_s
{
    uint32_t  tshwr : 16;  /* Timestamp Higher Word Register */
    uint32_t        : 16;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS. */
typedef volatile struct ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_s  ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register from the beginning of the component. */
#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_OFST        0x724
/* The address of the ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS register. */
#define ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_OFST))

/*
 * Register : Register 458 (Timestamp Status Register) - Timestamp_Status
 * 
 * Timestamp status. All bits except Bits[27:25] get cleared when the host reads
 * this register.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                    
 * :--------|:-------|:------|:------------------------------------------------
 *  [0]     | R      | 0x0   | Timestamp Seconds Overflow                     
 *  [1]     | R      | 0x0   | Timestamp Target Time Reached                  
 *  [2]     | R      | 0x0   | Auxiliary Timestamp Trigger Snapshot           
 *  [3]     | R      | 0x0   | Timestamp Target Time Error                    
 *  [15:4]  | ???    | 0x0   | *UNDEFINED*                                    
 *  [19:16] | R      | 0x0   | Auxiliary Timestamp Snapshot Trigger Identifier
 *  [23:20] | ???    | 0x0   | *UNDEFINED*                                    
 *  [24]    | R      | 0x0   | Auxiliary Timestamp Snapshot Trigger Missed    
 *  [29:25] | R      | 0x0   | Number of Auxiliary Timestamp Snapshots        
 *  [31:30] | ???    | 0x0   | *UNDEFINED*                                    
 * 
 */
/*
 * Field : Timestamp Seconds Overflow - tssovf
 * 
 * When set, this bit indicates that the seconds value of the timestamp (when
 * supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description     
 * :-----------------------------------|:------|:-----------------
 *  ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_RST | 0x0   | No Overflow     
 *  ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_SET | 0x1   | Seconds Overflow
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSSOVF
 * 
 * No Overflow
 */
#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_RST  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSSOVF
 * 
 * Seconds Overflow
 */
#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_E_SET  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_MSB        0
/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value. */
#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value. */
#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSSOVF register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_STAT_TSSOVF field value from a register. */
#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_GMAC_TS_STAT_TSSOVF register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_STAT_TSSOVF_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Timestamp Target Time Reached - tstargt
 * 
 * When set, this bit indicates that the value of system time is greater or equal
 * to the value specified in the Register 455 (Target Time Seconds Register) and
 * Register 456 (Target Time Nanoseconds Register).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                | Value | Description                        
 * :------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_RST | 0x0   | System Time                        
 *  ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_SET | 0x1   | System Time is >= Reg455 and Reg456
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTARGT
 * 
 * System Time
 */
#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_RST 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTARGT
 * 
 * System Time is >= Reg455 and Reg456
 */
#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_E_SET 0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_MSB        1
/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value. */
#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value. */
#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSTARGT register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_STAT_TSTARGT field value from a register. */
#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_GMAC_TS_STAT_TSTARGT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_STAT_TSTARGT_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Auxiliary Timestamp Trigger Snapshot - auxtstrig
 * 
 * This bit is set high when the auxiliary snapshot is written to the FIFO.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                        
 * :--------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_RST | 0x0   | System Time                        
 *  ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_SET | 0x1   | System Time is >= Reg455 and Reg456
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG
 * 
 * System Time
 */
#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_RST   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG
 * 
 * System Time is >= Reg455 and Reg456
 */
#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_E_SET   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_MSB        2
/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value. */
#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value. */
#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field. */
#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG field value from a register. */
#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_STAT_AUXTSTRIG_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Timestamp Target Time Error - tstrgterr
 * 
 * This bit is set when the target time, being programmed in Target Time Registers,
 * is already elapsed. This bit is cleared when read by the application.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                           
 * :--------------------------------------|:------|:---------------------------------------
 *  ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_RST | 0x0   | When Read resets                      
 *  ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_SET | 0x1   | Target Time Elapsed -Reg455 and Reg456
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTRGTERR
 * 
 * When Read resets
 */
#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_RST   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_TSTRGTERR
 * 
 * Target Time Elapsed -Reg455 and Reg456
 */
#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_E_SET   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value. */
#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value. */
#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field. */
#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_STAT_TSTRGTERR field value from a register. */
#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_GMAC_TS_STAT_TSTRGTERR register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_STAT_TSTRGTERR_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Auxiliary Timestamp Snapshot Trigger Identifier - atsstn
 * 
 * These bits identify the Auxiliary trigger inputs for which the timestamp
 * available in the Auxiliary Snapshot Register is applicable. When more than one
 * bit is set at the same time, it means that corresponding auxiliary triggers were
 * sampled at the same clock. These bits are applicable only if the number of
 * Auxiliary snapshots is more than one. One bit is assigned for each trigger as
 * shown in the following list:
 * 
 * * Bit 16: Auxiliary trigger 0
 * 
 * * Bit 17: Auxiliary trigger 1
 * 
 * * Bit 18: Auxiliary trigger 2
 * 
 * * Bit 19: Auxiliary trigger 3
 * 
 * The software can read this register to find the triggers that are set when the
 * timestamp is taken.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_MSB        19
/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_WIDTH      4
/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_SET_MSK    0x000f0000
/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_CLR_MSK    0xfff0ffff
/* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSSTN register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSSTN field value from a register. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_GET(value) (((value) & 0x000f0000) >> 16)
/* Produces a ALT_EMAC_GMAC_TS_STAT_ATSSTN register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTN_SET(value) (((value) << 16) & 0x000f0000)

/*
 * Field : Auxiliary Timestamp Snapshot Trigger Missed - atsstm
 * 
 * This bit is set when the Auxiliary timestamp snapshot FIFO is full and external
 * trigger was set. This indicates that the latest snapshot is not stored in the
 * FIFO.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                
 * :---------------------------------------|:------|:----------------------------
 *  ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_NOTFULL | 0x0   | Not Active                 
 *  ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_FULL    | 0x1   | Aux timestamp snapshot full
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_ATSSTM
 * 
 * Not Active
 */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_NOTFULL  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_TS_STAT_ATSSTM
 * 
 * Aux timestamp snapshot full
 */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_E_FULL     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSSTM register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSSTM field value from a register. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_TS_STAT_ATSSTM register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_STAT_ATSSTM_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Number of Auxiliary Timestamp Snapshots - atsns
 * 
 * This field indicates the number of Snapshots available in the FIFO. A value of
 * 16 (equal to the depth of the FIFO) indicates that the Auxiliary Snapshot FIFO
 * is full. These bits are cleared (to 00000) when the Auxiliary snapshot FIFO
 * clear bit is set.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSNS_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSNS_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSNS_WIDTH      5
/* The mask used to set the ALT_EMAC_GMAC_TS_STAT_ATSNS register field value. */
#define ALT_EMAC_GMAC_TS_STAT_ATSNS_SET_MSK    0x3e000000
/* The mask used to clear the ALT_EMAC_GMAC_TS_STAT_ATSNS register field value. */
#define ALT_EMAC_GMAC_TS_STAT_ATSNS_CLR_MSK    0xc1ffffff
/* The reset value of the ALT_EMAC_GMAC_TS_STAT_ATSNS register field. */
#define ALT_EMAC_GMAC_TS_STAT_ATSNS_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_TS_STAT_ATSNS field value from a register. */
#define ALT_EMAC_GMAC_TS_STAT_ATSNS_GET(value) (((value) & 0x3e000000) >> 25)
/* Produces a ALT_EMAC_GMAC_TS_STAT_ATSNS register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_TS_STAT_ATSNS_SET(value) (((value) << 25) & 0x3e000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_TS_STAT.
 */
struct ALT_EMAC_GMAC_TS_STAT_s
{
    const uint32_t  tssovf    :  1;  /* Timestamp Seconds Overflow */
    const uint32_t  tstargt   :  1;  /* Timestamp Target Time Reached */
    const uint32_t  auxtstrig :  1;  /* Auxiliary Timestamp Trigger Snapshot */
    const uint32_t  tstrgterr :  1;  /* Timestamp Target Time Error */
    uint32_t                  : 12;  /* *UNDEFINED* */
    const uint32_t  atsstn    :  4;  /* Auxiliary Timestamp Snapshot Trigger Identifier */
    uint32_t                  :  4;  /* *UNDEFINED* */
    const uint32_t  atsstm    :  1;  /* Auxiliary Timestamp Snapshot Trigger Missed */
    const uint32_t  atsns     :  5;  /* Number of Auxiliary Timestamp Snapshots */
    uint32_t                  :  2;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_TS_STAT. */
typedef volatile struct ALT_EMAC_GMAC_TS_STAT_s  ALT_EMAC_GMAC_TS_STAT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_TS_STAT register from the beginning of the component. */
#define ALT_EMAC_GMAC_TS_STAT_OFST        0x728
/* The address of the ALT_EMAC_GMAC_TS_STAT register. */
#define ALT_EMAC_GMAC_TS_STAT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_STAT_OFST))

/*
 * Register : Register 459 (PPS Control Register) - PPS_Control
 * 
 * Controls timestamp Pulse-Per-Second output
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                              
 * :-------|:-------|:------|:------------------------------------------
 *  [3:0]  | RW     | 0x0   | PPSCTRL0 or PPSCMD0                      
 *  [4]    | RW     | 0x0   | Flexible PPS Output Mode Enable          
 *  [6:5]  | RW     | 0x0   | Target Time Register Mode for PPS0 Output
 *  [31:7] | ???    | 0x0   | *UNDEFINED*                              
 * 
 */
/*
 * Field : PPSCTRL0 or PPSCMD0 - ppsctrl_ppscmd
 * 
 * PPSCTRL0: PPS0 Output Frequency Control
 * 
 * This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The
 * default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width
 * clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a
 * generated clock of following frequencies:
 * 
 * * 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz.
 * 
 * * 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz.
 * 
 * * 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz.
 * 
 * * 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz.
 * 
 * * ...
 * 
 * * 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384
 *   KHz.
 * 
 * Note:
 * 
 * In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50
 * percent with these frequencies.
 * 
 * In the digital rollover mode, the PPS output frequency is an average number. The
 * actual clock is of different frequency that gets synchronized every second. For
 * example:
 * 
 *     - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high
 *       period of 463 ms
 * 
 *     - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of:
 * 
 * * One clock of 50 percent duty cycle and 537 ms period
 * 
 * * Second clock of 463 ms period (268 ms low and 195 ms high)
 * 
 *     - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of:
 * 
 * * Three clocks of 50 percent duty cycle and 268 ms period
 * 
 * * Fourth clock of 195 ms period (134 ms low and 61 ms high)
 * 
 * This behavior is because of the non-linear toggling of bits in the digital
 * rollover mode in Register 451 (System Time - Nanoseconds Register).
 * 
 * Flexible PPS0 Output (ptp_pps_o[0]) Control
 * 
 * Programming these bits with a non-zero value instructs the MAC to initiate an
 * event. Once the command is transferred or synchronized to the PTP clock domain,
 * these bits get cleared automatically. The Software should ensure that these bits
 * are programmed only when they are all-zero. The following list describes the
 * values of PPSCMD0:
 * 
 *     - 0000: No Command
 * 
 *     - 0001: START Single Pulse
 * 
 * This command generates single pulse rising at the start point defined in Target
 * Time Registers (register 455 and 456) and of a duration defined in the PPS0
 * Width Register.
 * 
 *     - 0010: START Pulse Train
 * 
 * This command generates the train of pulses rising at the start point defined in
 * the Target Time Registers and of a duration defined in the PPS0 Width Register
 * and repeated at interval defined in the PPS Interval Register. By default, the
 * PPS pulse train is free-running unless stopped by 'STOP Pulse train at time' or
 * 'STOP Pulse Train immediately' commands.
 * 
 *     - 0011: Cancel START
 * 
 * This command cancels the START Single Pulse and START Pulse Train commands if
 * the system time has not crossed the programmed start time.
 * 
 *     - 0100: STOP Pulse train at time
 * 
 * This command stops the train of pulses initiated by the START Pulse Train
 * command (PPSCMD = 0010) after the time programmed in the Target Time registers
 * elapses.
 * 
 *     - 0101: STOP Pulse Train immediately
 * 
 * This command immediately stops the train of pulses initiated by the START Pulse
 * Train command (PPSCMD = 0010).
 * 
 *     - 0110: Cancel STOP Pulse train
 * 
 * This command cancels the STOP pulse train at time command if the programmed stop
 * time has not elapsed. The PPS pulse train becomes free-running on the successful
 * execution of this command.
 * 
 *     - 0111-1111: Reserved
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_MSB        3
/* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_WIDTH      4
/* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET_MSK    0x0000000f
/* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_CLR_MSK    0xfffffff0
/* The reset value of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD field value from a register. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_GET(value) (((value) & 0x0000000f) >> 0)
/* Produces a ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET(value) (((value) << 0) & 0x0000000f)

/*
 * Field : Flexible PPS Output Mode Enable - ppsen0
 * 
 * When set low, Bits[3:0] function as PPSCTRL (backward compatible). When set
 * high, Bits[3:0] function as PPSCMD.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                   
 * :--------------------------------------|:------|:-------------------------------
 *  ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL | 0x0   | Bits[3:0] function as ppsctrl0
 *  ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD | 0x1   | Bits[3:0] function as ppscmd  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_PPSEN0
 * 
 * Bits[3:0] function as ppsctrl0
 */
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_PPSEN0
 * 
 * Bits[3:0] function as ppscmd
 */
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_MSB        4
/* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 field value from a register. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Target Time Register Mode for PPS0 Output - trgtmodsel0
 * 
 * This field indicates the Target Time registers (register 455 and 456) mode for
 * PPS0 output signal
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                              | Value | Description                                 
 * :--------------------------------------------------|:------|:---------------------------------------------
 *  ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY | 0x0   | Target Time regs generate interrupt event.  
 *  ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0   | 0x2   | Target Time gen. interr event and sig pps0  
 *  ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER   | 0x3   | Target Time No inter just start and stop sig
 * :                                                  |       | pps0                                        
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0
 * 
 * Target Time regs generate interrupt event.
 */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0
 * 
 * Target Time gen. interr event and sig pps0
 */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0     0x2
/*
 * Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0
 * 
 * Target Time No inter just start and stop sig pps0
 */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER     0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_MSB        6
/* The width in bits of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_WIDTH      2
/* The mask used to set the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value. */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET_MSK    0x00000060
/* The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value. */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_CLR_MSK    0xffffff9f
/* The reset value of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field. */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 field value from a register. */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_GET(value) (((value) & 0x00000060) >> 5)
/* Produces a ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET(value) (((value) << 5) & 0x00000060)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_PPS_CTL.
 */
struct ALT_EMAC_GMAC_PPS_CTL_s
{
    uint32_t  ppsctrl_ppscmd :  4;  /* PPSCTRL0 or PPSCMD0 */
    uint32_t  ppsen0         :  1;  /* Flexible PPS Output Mode Enable */
    uint32_t  trgtmodsel0    :  2;  /* Target Time Register Mode for PPS0 Output */
    uint32_t                 : 25;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_PPS_CTL. */
typedef volatile struct ALT_EMAC_GMAC_PPS_CTL_s  ALT_EMAC_GMAC_PPS_CTL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_PPS_CTL register from the beginning of the component. */
#define ALT_EMAC_GMAC_PPS_CTL_OFST        0x72c
/* The address of the ALT_EMAC_GMAC_PPS_CTL register. */
#define ALT_EMAC_GMAC_PPS_CTL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS_CTL_OFST))

/*
 * Register : Register 460 (Auxiliary Timestamp - Nanoseconds Register) - Auxiliary_Timestamp_Nanoseconds
 * 
 * This register, along with Register 461 (Auxiliary Timestamp  Seconds Register),
 * gives the 64-bit timestamp stored as auxiliary snapshot. The two registers
 * together form the read port of a 64-bit wide FIFO with a depth of 16. Multiple
 * snapshots can be stored in this FIFO. The ATSNS bits in the Timestamp Status
 * register indicate the fill-level of this FIFO. The top of the FIFO is removed
 * only when the last byte of Register 461 (Auxiliary Timestamp - Seconds Register)
 * is read. In the little-endian mode, this means when Bits[31:24] are read. In
 * big-endian mode, it corresponds to the reading of Bits[7:0] of Register 461
 * (Auxiliary Timestamp - Seconds Register).
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                          
 * :-------|:-------|:------|:--------------------------------------
 *  [30:0] | R      | 0x0   | ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO
 *  [31]   | ???    | 0x0   | *UNDEFINED*                          
 * 
 */
/*
 * Field : auxtslo
 * 
 * Contains the lower 32 bits (nano-seconds field) of the auxiliary timestamp.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_WIDTH      31
/* The mask used to set the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value. */
#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_SET_MSK    0x7fffffff
/* The mask used to clear the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value. */
#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_CLR_MSK    0x80000000
/* The reset value of the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field. */
#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO field value from a register. */
#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_GET(value) (((value) & 0x7fffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO_SET(value) (((value) << 0) & 0x7fffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_AUX_TS_NANOSECS.
 */
struct ALT_EMAC_GMAC_AUX_TS_NANOSECS_s
{
    const uint32_t  auxtslo : 31;  /* ALT_EMAC_GMAC_AUX_TS_NANOSECS_AUXTSLO */
    uint32_t                :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_GMAC_AUX_TS_NANOSECS. */
typedef volatile struct ALT_EMAC_GMAC_AUX_TS_NANOSECS_s  ALT_EMAC_GMAC_AUX_TS_NANOSECS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register from the beginning of the component. */
#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_OFST        0x730
/* The address of the ALT_EMAC_GMAC_AUX_TS_NANOSECS register. */
#define ALT_EMAC_GMAC_AUX_TS_NANOSECS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_AUX_TS_NANOSECS_OFST))

/*
 * Register : Register 461 (Auxiliary Timestamp - Seconds Register) - Auxiliary_Timestamp_Seconds
 * 
 * Contains the higher 32 bits (Seconds field) of the auxiliary timestamp.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                      
 * :-------|:-------|:------|:----------------------------------
 *  [31:0] | R      | 0x0   | ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI
 * 
 */
/*
 * Field : auxtshi
 * 
 * Contains the higher 32 bits (Seconds field) of the auxiliary timestamp.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value. */
#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value. */
#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field. */
#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI field value from a register. */
#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_AUX_TS_SECS.
 */
struct ALT_EMAC_GMAC_AUX_TS_SECS_s
{
    const uint32_t  auxtshi : 32;  /* ALT_EMAC_GMAC_AUX_TS_SECS_AUXTSHI */
};

/* The typedef declaration for register ALT_EMAC_GMAC_AUX_TS_SECS. */
typedef volatile struct ALT_EMAC_GMAC_AUX_TS_SECS_s  ALT_EMAC_GMAC_AUX_TS_SECS_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_AUX_TS_SECS register from the beginning of the component. */
#define ALT_EMAC_GMAC_AUX_TS_SECS_OFST        0x734
/* The address of the ALT_EMAC_GMAC_AUX_TS_SECS register. */
#define ALT_EMAC_GMAC_AUX_TS_SECS_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_AUX_TS_SECS_OFST))

/*
 * Register : Register 472 (PPS0 Interval Register) - PPS0_Interval
 * 
 * The PPS0 Interval register contains the number of units of sub-second increment
 * value between the rising edges of PPS0 signal output (ptp_pps_o[0]).
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                
 * :-------|:-------|:------|:----------------------------
 *  [31:0] | RW     | 0x0   | PPS0 Output Signal Interval
 * 
 */
/*
 * Field : PPS0 Output Signal Interval - ppsint
 * 
 * These bits store the interval between the rising edges of PPS0 signal output in
 * terms of units of sub-second increment value.
 * 
 * You need to program one value less than the required interval. For example, if
 * the PTP reference clock is 50 MHz (period of 20ns), and desired interval between
 * rising edges of PPS0 signal output is 100ns (that is, five units of sub-second
 * increment value), then you should program value 4 (5 -1) in this register.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value. */
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value. */
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field. */
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT field value from a register. */
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_PPS0_INTERVAL.
 */
struct ALT_EMAC_GMAC_PPS0_INTERVAL_s
{
    uint32_t  ppsint : 32;  /* PPS0 Output Signal Interval */
};

/* The typedef declaration for register ALT_EMAC_GMAC_PPS0_INTERVAL. */
typedef volatile struct ALT_EMAC_GMAC_PPS0_INTERVAL_s  ALT_EMAC_GMAC_PPS0_INTERVAL_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_PPS0_INTERVAL register from the beginning of the component. */
#define ALT_EMAC_GMAC_PPS0_INTERVAL_OFST        0x760
/* The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register. */
#define ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS0_INTERVAL_OFST))

/*
 * Register : Register 473 (PPS0 Width Register) - PPS0_Width
 * 
 * The PPS0 Width register contains the number of units of sub-second increment
 * value between the rising and corresponding falling edges of the PPS0 signal
 * output (ptp_pps_o[0]).
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description             
 * :-------|:-------|:------|:-------------------------
 *  [31:0] | RW     | 0x0   | PPS0 Output Signal Width
 * 
 */
/*
 * Field : PPS0 Output Signal Width - ppswidth
 * 
 * These bits store the width between the rising edge and corresponding falling
 * edge of the PPS0 signal output in terms of units of sub-second increment value.
 * 
 * You need to program one value less than the required interval. For example, if
 * PTP reference clock is 50 MHz (period of 20ns), and desired width between the
 * rising and corresponding falling edges of PPS0 signal output is 80ns (that is,
 * four units of sub-second increment value), then you should program value 3 (4-1)
 * in this register.
 * 
 * Note:
 * 
 * The value programmed in this register must be lesser than the value programmed
 * in Register 472 (PPS0 Interval Register).
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value. */
#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value. */
#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field. */
#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH field value from a register. */
#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_PPS0_WIDTH_PPSWIDTH_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_PPS0_WIDTH.
 */
struct ALT_EMAC_GMAC_PPS0_WIDTH_s
{
    uint32_t  ppswidth : 32;  /* PPS0 Output Signal Width */
};

/* The typedef declaration for register ALT_EMAC_GMAC_PPS0_WIDTH. */
typedef volatile struct ALT_EMAC_GMAC_PPS0_WIDTH_s  ALT_EMAC_GMAC_PPS0_WIDTH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_PPS0_WIDTH register from the beginning of the component. */
#define ALT_EMAC_GMAC_PPS0_WIDTH_OFST        0x764
/* The address of the ALT_EMAC_GMAC_PPS0_WIDTH register. */
#define ALT_EMAC_GMAC_PPS0_WIDTH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS0_WIDTH_OFST))

/*
 * Register : Register 512 (MAC Address16 High Register) - MAC_Address16_High
 * 
 * The MAC Address16 High register holds the upper 16 bits of the 17th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address16 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address16 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address16 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 17th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address16 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address16 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address16 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address16 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address16 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address16 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address16[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address16[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 17th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR16_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR16_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address16 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR16_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR16_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR16_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_OFST        0x800
/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR16_HIGH_OFST))

/*
 * Register : Register 513 (MAC Address16 Low Register) - MAC_Address16_Low
 * 
 * The MAC Address16 Low register holds the lower 32 bits of the 17th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address16 [31:0]
 * 
 */
/*
 * Field : MAC Address16 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 17th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR16_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR16_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address16 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR16_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR16_LOW_s  ALT_EMAC_GMAC_MAC_ADDR16_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_OFST        0x804
/* The address of the ALT_EMAC_GMAC_MAC_ADDR16_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR16_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR16_LOW_OFST))

/*
 * Register : Register 514 (MAC Address17 High Register) - MAC_Address17_High
 * 
 * The MAC Address17 High register holds the upper 16 bits of the 18th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address17 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address17 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address17 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 18th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address17 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address17 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address17 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address17 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address17 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address17 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address17[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address17[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 18th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR17_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR17_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address17 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR17_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR17_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR17_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_OFST        0x808
/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR17_HIGH_OFST))

/*
 * Register : Register 515 (MAC Address17 Low Register) - MAC_Address17_Low
 * 
 * The MAC Address17 Low register holds the lower 32 bits of the 18th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address17 [31:0]
 * 
 */
/*
 * Field : MAC Address17 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 18th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR17_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR17_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address17 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR17_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR17_LOW_s  ALT_EMAC_GMAC_MAC_ADDR17_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_OFST        0x80c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR17_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR17_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR17_LOW_OFST))

/*
 * Register : Register 516 (MAC Address18 High Register) - MAC_Address18_High
 * 
 * The MAC Address18 High register holds the upper 16 bits of the 19th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address18 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address18 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address18 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 19th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address18 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address18 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address18 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address18 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address18 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address18 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address18[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address18[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 19th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR18_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR18_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address18 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR18_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR18_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR18_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_OFST        0x810
/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR18_HIGH_OFST))

/*
 * Register : Register 517 (MAC Address18 Low Register) - MAC_Address18_Low
 * 
 * The MAC Address18 Low register holds the lower 32 bits of the 19th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address18 [31:0]
 * 
 */
/*
 * Field : MAC Address18 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 19th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR18_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR18_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address18 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR18_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR18_LOW_s  ALT_EMAC_GMAC_MAC_ADDR18_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_OFST        0x814
/* The address of the ALT_EMAC_GMAC_MAC_ADDR18_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR18_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR18_LOW_OFST))

/*
 * Register : Register 518 (MAC Address19 High Register) - MAC_Address19_High
 * 
 * The MAC Address19 High register holds the upper 16 bits of the 20th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address19 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address19 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address19 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 20th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address19 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address19 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address19 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address19 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address19 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address19 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address19[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address19[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 20th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR19_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR19_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address19 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR19_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR19_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR19_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_OFST        0x818
/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR19_HIGH_OFST))

/*
 * Register : Register 519 (MAC Address19 Low Register) - MAC_Address19_Low
 * 
 * The MAC Address19 Low register holds the lower 32 bits of the 20th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address19 [31:0]
 * 
 */
/*
 * Field : MAC Address19 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 20th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR19_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR19_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address19 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR19_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR19_LOW_s  ALT_EMAC_GMAC_MAC_ADDR19_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_OFST        0x81c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR19_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR19_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR19_LOW_OFST))

/*
 * Register : Register 520 (MAC Address20 High Register) - MAC_Address20_High
 * 
 * The MAC Address20 High register holds the upper 16 bits of the 21th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address20 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address20 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address20 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 21th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address20 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address20 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address20 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address20 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address20 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address20 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address20[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address20[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 21th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR20_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR20_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address20 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR20_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR20_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR20_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_OFST        0x820
/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR20_HIGH_OFST))

/*
 * Register : Register 521 (MAC Address20 Low Register) - MAC_Address20_Low
 * 
 * The MAC Address20 Low register holds the lower 32 bits of the 21th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address20 [31:0]
 * 
 */
/*
 * Field : MAC Address20 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 21th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR20_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR20_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address20 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR20_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR20_LOW_s  ALT_EMAC_GMAC_MAC_ADDR20_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_OFST        0x824
/* The address of the ALT_EMAC_GMAC_MAC_ADDR20_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR20_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR20_LOW_OFST))

/*
 * Register : Register 522 (MAC Address21 High Register) - MAC_Address21_High
 * 
 * The MAC Address21 High register holds the upper 16 bits of the 22th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address21 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address21 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address21 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 22th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address21 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address21 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address21 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address21 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address21 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address21 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address21[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address21[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 22th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR21_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR21_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address21 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR21_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR21_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR21_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_OFST        0x828
/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR21_HIGH_OFST))

/*
 * Register : Register 523 (MAC Address21 Low Register) - MAC_Address21_Low
 * 
 * The MAC Address21 Low register holds the lower 32 bits of the 22th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address21 [31:0]
 * 
 */
/*
 * Field : MAC Address21 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 22th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR21_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR21_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address21 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR21_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR21_LOW_s  ALT_EMAC_GMAC_MAC_ADDR21_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_OFST        0x82c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR21_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR21_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR21_LOW_OFST))

/*
 * Register : Register 524 (MAC Address22 High Register) - MAC_Address22_High
 * 
 * The MAC Address22 High register holds the upper 16 bits of the 23th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address22 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address22 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address22 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 23th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address22 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address22 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address22 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address22 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address22 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address22 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address22[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address22[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 23th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR22_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR22_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address22 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR22_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR22_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR22_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_OFST        0x830
/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR22_HIGH_OFST))

/*
 * Register : Register 525 (MAC Address22 Low Register) - MAC_Address22_Low
 * 
 * The MAC Address22 Low register holds the lower 32 bits of the 23th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address22 [31:0]
 * 
 */
/*
 * Field : MAC Address22 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 23th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR22_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR22_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address22 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR22_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR22_LOW_s  ALT_EMAC_GMAC_MAC_ADDR22_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_OFST        0x834
/* The address of the ALT_EMAC_GMAC_MAC_ADDR22_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR22_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR22_LOW_OFST))

/*
 * Register : Register 526 (MAC Address23 High Register) - MAC_Address23_High
 * 
 * The MAC Address23 High register holds the upper 16 bits of the 24th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address23 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address23 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address23 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 24th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address23 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address23 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address23 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address23 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address23 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address23 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address23[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address23[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 24th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR23_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR23_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address23 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR23_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR23_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR23_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_OFST        0x838
/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR23_HIGH_OFST))

/*
 * Register : Register 527 (MAC Address23 Low Register) - MAC_Address23_Low
 * 
 * The MAC Address23 Low register holds the lower 32 bits of the 24th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address23 [31:0]
 * 
 */
/*
 * Field : MAC Address23 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 24th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR23_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR23_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address23 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR23_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR23_LOW_s  ALT_EMAC_GMAC_MAC_ADDR23_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_OFST        0x83c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR23_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR23_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR23_LOW_OFST))

/*
 * Register : Register 528 (MAC Address24 High Register) - MAC_Address24_High
 * 
 * The MAC Address24 High register holds the upper 16 bits of the 25th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address24 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address24 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address24 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 25th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address24 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address24 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address24 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address24 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address24 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address24 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address24[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address24[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 25th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR24_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR24_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address24 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR24_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR24_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR24_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_OFST        0x840
/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR24_HIGH_OFST))

/*
 * Register : Register 529 (MAC Address24 Low Register) - MAC_Address24_Low
 * 
 * The MAC Address24 Low register holds the lower 32 bits of the 25th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address24 [31:0]
 * 
 */
/*
 * Field : MAC Address24 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 25th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR24_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR24_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address24 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR24_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR24_LOW_s  ALT_EMAC_GMAC_MAC_ADDR24_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_OFST        0x844
/* The address of the ALT_EMAC_GMAC_MAC_ADDR24_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR24_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR24_LOW_OFST))

/*
 * Register : Register 530 (MAC Address25 High Register) - MAC_Address25_High
 * 
 * The MAC Address25 High register holds the upper 16 bits of the 26th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address25 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address25 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address25 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 26th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address25 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address25 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address25 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address25 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address25 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address25 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address25[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address25[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 26th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR25_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR25_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address25 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR25_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR25_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR25_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_OFST        0x848
/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR25_HIGH_OFST))

/*
 * Register : Register 531 (MAC Address25 Low Register) - MAC_Address25_Low
 * 
 * The MAC Address25 Low register holds the lower 32 bits of the 26th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address25 [31:0]
 * 
 */
/*
 * Field : MAC Address25 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 26th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR25_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR25_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address25 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR25_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR25_LOW_s  ALT_EMAC_GMAC_MAC_ADDR25_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_OFST        0x84c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR25_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR25_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR25_LOW_OFST))

/*
 * Register : Register 532 (MAC Address26 High Register) - MAC_Address26_High
 * 
 * The MAC Address26 High register holds the upper 16 bits of the 27th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address26 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address26 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address26 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 27th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address26 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address26 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address26 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address26 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address26 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address26 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address26[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address26[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 27th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR26_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR26_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address26 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR26_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR26_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR26_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_OFST        0x850
/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR26_HIGH_OFST))

/*
 * Register : Register 533 (MAC Address26 Low Register) - MAC_Address26_Low
 * 
 * The MAC Address26 Low register holds the lower 32 bits of the 27th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address26 [31:0]
 * 
 */
/*
 * Field : MAC Address26 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 27th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR26_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR26_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address26 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR26_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR26_LOW_s  ALT_EMAC_GMAC_MAC_ADDR26_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_OFST        0x854
/* The address of the ALT_EMAC_GMAC_MAC_ADDR26_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR26_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR26_LOW_OFST))

/*
 * Register : Register 534 (MAC Address27 High Register) - MAC_Address27_High
 * 
 * The MAC Address27 High register holds the upper 16 bits of the 28th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address27 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address27 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address27 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 28th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address27 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address27 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address27 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address27 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address27 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address27 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address27[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address27[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 28th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR27_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR27_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address27 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR27_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR27_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR27_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_OFST        0x858
/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR27_HIGH_OFST))

/*
 * Register : Register 535 (MAC Address27 Low Register) - MAC_Address27_Low
 * 
 * The MAC Address27 Low register holds the lower 32 bits of the 28th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address27 [31:0]
 * 
 */
/*
 * Field : MAC Address27 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 28th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR27_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR27_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address27 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR27_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR27_LOW_s  ALT_EMAC_GMAC_MAC_ADDR27_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_OFST        0x85c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR27_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR27_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR27_LOW_OFST))

/*
 * Register : Register 536 (MAC Address28 High Register) - MAC_Address28_High
 * 
 * The MAC Address28 High register holds the upper 16 bits of the 29th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address28 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address28 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address28 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 29th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address28 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address28 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address28 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address28 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address28 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address28 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address28[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address28[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 29th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR28_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR28_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address28 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR28_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR28_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR28_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_OFST        0x860
/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR28_HIGH_OFST))

/*
 * Register : Register 537 (MAC Address28 Low Register) - MAC_Address28_Low
 * 
 * The MAC Address28 Low register holds the lower 32 bits of the 29th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address28 [31:0]
 * 
 */
/*
 * Field : MAC Address28 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 29th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR28_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR28_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address28 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR28_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR28_LOW_s  ALT_EMAC_GMAC_MAC_ADDR28_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_OFST        0x864
/* The address of the ALT_EMAC_GMAC_MAC_ADDR28_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR28_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR28_LOW_OFST))

/*
 * Register : Register 538 (MAC Address29 High Register) - MAC_Address29_High
 * 
 * The MAC Address29 High register holds the upper 16 bits of the 30th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address29 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address29 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address29 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 30th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address29 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address29 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address29 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address29 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address29 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address29 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address29[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address29[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 30th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR29_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR29_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address29 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR29_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR29_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR29_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_OFST        0x868
/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR29_HIGH_OFST))

/*
 * Register : Register 539 (MAC Address29 Low Register) - MAC_Address29_Low
 * 
 * The MAC Address29 Low register holds the lower 32 bits of the 30th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address29 [31:0]
 * 
 */
/*
 * Field : MAC Address29 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 30th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR29_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR29_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address29 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR29_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR29_LOW_s  ALT_EMAC_GMAC_MAC_ADDR29_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_OFST        0x86c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR29_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR29_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR29_LOW_OFST))

/*
 * Register : Register 540 (MAC Address30 High Register) - MAC_Address30_High
 * 
 * The MAC Address30 High register holds the upper 16 bits of the 31th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address30 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address30 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address30 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 31th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address30 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address30 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address30 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address30 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address30 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address30 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address30[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address30[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 31th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR30_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR30_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address30 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR30_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR30_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR30_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_OFST        0x870
/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR30_HIGH_OFST))

/*
 * Register : Register 541 (MAC Address30 Low Register) - MAC_Address30_Low
 * 
 * The MAC Address30 Low register holds the lower 32 bits of the 31th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address30 [31:0]
 * 
 */
/*
 * Field : MAC Address30 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 31th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR30_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR30_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address30 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR30_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR30_LOW_s  ALT_EMAC_GMAC_MAC_ADDR30_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_OFST        0x874
/* The address of the ALT_EMAC_GMAC_MAC_ADDR30_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR30_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR30_LOW_OFST))

/*
 * Register : Register 542 (MAC Address31 High Register) - MAC_Address31_High
 * 
 * The MAC Address31 High register holds the upper 16 bits of the 32th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address31 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address31 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address31 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 32th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address31 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address31 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address31 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address31 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address31 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address31 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address31[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address31[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 32th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR31_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR31_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address31 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR31_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR31_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR31_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_OFST        0x878
/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR31_HIGH_OFST))

/*
 * Register : Register 543 (MAC Address31 Low Register) - MAC_Address31_Low
 * 
 * The MAC Address31 Low register holds the lower 32 bits of the 32th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address31 [31:0]
 * 
 */
/*
 * Field : MAC Address31 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 32th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR31_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR31_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address31 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR31_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR31_LOW_s  ALT_EMAC_GMAC_MAC_ADDR31_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_OFST        0x87c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR31_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR31_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR31_LOW_OFST))

/*
 * Register : Register 544 (MAC Address32 High Register) - MAC_Address32_High
 * 
 * The MAC Address32 High register holds the upper 16 bits of the 33th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address32 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address32 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address32 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 33th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address32 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address32 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address32 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address32 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address32 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address32 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address32[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address32[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 33th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR32_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR32_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address32 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR32_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR32_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR32_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_OFST        0x880
/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR32_HIGH_OFST))

/*
 * Register : Register 545 (MAC Address32 Low Register) - MAC_Address32_Low
 * 
 * The MAC Address32 Low register holds the lower 32 bits of the 33th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address32 [31:0]
 * 
 */
/*
 * Field : MAC Address32 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 33th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR32_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR32_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address32 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR32_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR32_LOW_s  ALT_EMAC_GMAC_MAC_ADDR32_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_OFST        0x884
/* The address of the ALT_EMAC_GMAC_MAC_ADDR32_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR32_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR32_LOW_OFST))

/*
 * Register : Register 546 (MAC Address33 High Register) - MAC_Address33_High
 * 
 * The MAC Address33 High register holds the upper 16 bits of the 34th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address33 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address33 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address33 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 34th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address33 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address33 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address33 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address33 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address33 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address33 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address33[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address33[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 34th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR33_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR33_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address33 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR33_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR33_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR33_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_OFST        0x888
/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR33_HIGH_OFST))

/*
 * Register : Register 547 (MAC Address33 Low Register) - MAC_Address33_Low
 * 
 * The MAC Address33 Low register holds the lower 32 bits of the 34th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address33 [31:0]
 * 
 */
/*
 * Field : MAC Address33 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 34th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR33_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR33_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address33 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR33_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR33_LOW_s  ALT_EMAC_GMAC_MAC_ADDR33_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_OFST        0x88c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR33_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR33_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR33_LOW_OFST))

/*
 * Register : Register 548 (MAC Address34 High Register) - MAC_Address34_High
 * 
 * The MAC Address34 High register holds the upper 16 bits of the 35th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address34 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address34 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address34 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 35th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address34 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address34 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address34 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address34 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address34 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address34 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address34[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address34[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 35th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR34_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR34_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address34 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR34_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR34_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR34_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_OFST        0x890
/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR34_HIGH_OFST))

/*
 * Register : Register 549 (MAC Address34 Low Register) - MAC_Address34_Low
 * 
 * The MAC Address34 Low register holds the lower 32 bits of the 35th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address34 [31:0]
 * 
 */
/*
 * Field : MAC Address34 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 35th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR34_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR34_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address34 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR34_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR34_LOW_s  ALT_EMAC_GMAC_MAC_ADDR34_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_OFST        0x894
/* The address of the ALT_EMAC_GMAC_MAC_ADDR34_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR34_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR34_LOW_OFST))

/*
 * Register : Register 550 (MAC Address35 High Register) - MAC_Address35_High
 * 
 * The MAC Address35 High register holds the upper 16 bits of the 36th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address35 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address35 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address35 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 36th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address35 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address35 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address35 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address35 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address35 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address35 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address35[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address35[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 36th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR35_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR35_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address35 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR35_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR35_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR35_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_OFST        0x898
/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR35_HIGH_OFST))

/*
 * Register : Register 551 (MAC Address35 Low Register) - MAC_Address35_Low
 * 
 * The MAC Address35 Low register holds the lower 32 bits of the 36th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address35 [31:0]
 * 
 */
/*
 * Field : MAC Address35 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 36th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR35_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR35_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address35 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR35_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR35_LOW_s  ALT_EMAC_GMAC_MAC_ADDR35_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_OFST        0x89c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR35_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR35_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR35_LOW_OFST))

/*
 * Register : Register 552 (MAC Address36 High Register) - MAC_Address36_High
 * 
 * The MAC Address36 High register holds the upper 16 bits of the 37th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address36 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address36 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address36 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 37th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address36 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address36 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address36 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address36 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address36 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address36 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address36[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address36[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 37th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR36_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR36_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address36 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR36_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR36_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR36_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_OFST        0x8a0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR36_HIGH_OFST))

/*
 * Register : Register 553 (MAC Address36 Low Register) - MAC_Address36_Low
 * 
 * The MAC Address36 Low register holds the lower 32 bits of the 37th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address36 [31:0]
 * 
 */
/*
 * Field : MAC Address36 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 37th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR36_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR36_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address36 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR36_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR36_LOW_s  ALT_EMAC_GMAC_MAC_ADDR36_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_OFST        0x8a4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR36_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR36_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR36_LOW_OFST))

/*
 * Register : Register 554 (MAC Address37 High Register) - MAC_Address37_High
 * 
 * The MAC Address37 High register holds the upper 16 bits of the 38th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address37 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address37 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address37 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 38th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address37 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address37 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address37 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address37 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address37 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address37 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address37[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address37[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 38th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR37_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR37_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address37 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR37_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR37_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR37_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_OFST        0x8a8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR37_HIGH_OFST))

/*
 * Register : Register 555 (MAC Address37 Low Register) - MAC_Address37_Low
 * 
 * The MAC Address37 Low register holds the lower 32 bits of the 38th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address37 [31:0]
 * 
 */
/*
 * Field : MAC Address37 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 38th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR37_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR37_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address37 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR37_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR37_LOW_s  ALT_EMAC_GMAC_MAC_ADDR37_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_OFST        0x8ac
/* The address of the ALT_EMAC_GMAC_MAC_ADDR37_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR37_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR37_LOW_OFST))

/*
 * Register : Register 556 (MAC Address38 High Register) - MAC_Address38_High
 * 
 * The MAC Address38 High register holds the upper 16 bits of the 39th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address38 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address38 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address38 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 39th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address38 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address38 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address38 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address38 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address38 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address38 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address38[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address38[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 39th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR38_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR38_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address38 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR38_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR38_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR38_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_OFST        0x8b0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR38_HIGH_OFST))

/*
 * Register : Register 557 (MAC Address38 Low Register) - MAC_Address38_Low
 * 
 * The MAC Address38 Low register holds the lower 32 bits of the 39th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address38 [31:0]
 * 
 */
/*
 * Field : MAC Address38 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 39th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR38_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR38_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address38 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR38_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR38_LOW_s  ALT_EMAC_GMAC_MAC_ADDR38_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_OFST        0x8b4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR38_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR38_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR38_LOW_OFST))

/*
 * Register : Register 558 (MAC Address39 High Register) - MAC_Address39_High
 * 
 * The MAC Address39 High register holds the upper 16 bits of the 40th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address39 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address39 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address39 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 40th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address39 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address39 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address39 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address39 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address39 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address39 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address39[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address39[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 40th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR39_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR39_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address39 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR39_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR39_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR39_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_OFST        0x8b8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR39_HIGH_OFST))

/*
 * Register : Register 559 (MAC Address39 Low Register) - MAC_Address39_Low
 * 
 * The MAC Address39 Low register holds the lower 32 bits of the 40th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address39 [31:0]
 * 
 */
/*
 * Field : MAC Address39 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 40th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR39_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR39_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address39 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR39_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR39_LOW_s  ALT_EMAC_GMAC_MAC_ADDR39_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_OFST        0x8bc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR39_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR39_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR39_LOW_OFST))

/*
 * Register : Register 560 (MAC Address40 High Register) - MAC_Address40_High
 * 
 * The MAC Address40 High register holds the upper 16 bits of the 41th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address40 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address40 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address40 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 41th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address40 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address40 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address40 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address40 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address40 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address40 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address40[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address40[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 41th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR40_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR40_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address40 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR40_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR40_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR40_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_OFST        0x8c0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR40_HIGH_OFST))

/*
 * Register : Register 561 (MAC Address40 Low Register) - MAC_Address40_Low
 * 
 * The MAC Address40 Low register holds the lower 32 bits of the 41th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address40 [31:0]
 * 
 */
/*
 * Field : MAC Address40 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 41th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR40_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR40_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address40 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR40_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR40_LOW_s  ALT_EMAC_GMAC_MAC_ADDR40_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_OFST        0x8c4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR40_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR40_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR40_LOW_OFST))

/*
 * Register : Register 562 (MAC Address41 High Register) - MAC_Address41_High
 * 
 * The MAC Address41 High register holds the upper 16 bits of the 42th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address41 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address41 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address41 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 42th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address41 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address41 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address41 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address41 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address41 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address41 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address41[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address41[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 42th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR41_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR41_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address41 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR41_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR41_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR41_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_OFST        0x8c8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR41_HIGH_OFST))

/*
 * Register : Register 563 (MAC Address41 Low Register) - MAC_Address41_Low
 * 
 * The MAC Address41 Low register holds the lower 32 bits of the 42th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address41 [31:0]
 * 
 */
/*
 * Field : MAC Address41 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 42th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR41_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR41_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address41 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR41_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR41_LOW_s  ALT_EMAC_GMAC_MAC_ADDR41_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_OFST        0x8cc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR41_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR41_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR41_LOW_OFST))

/*
 * Register : Register 564 (MAC Address42 High Register) - MAC_Address42_High
 * 
 * The MAC Address42 High register holds the upper 16 bits of the 43th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address42 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address42 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address42 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 43th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address42 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address42 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address42 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address42 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address42 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address42 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address42[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address42[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 43th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR42_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR42_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address42 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR42_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR42_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR42_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_OFST        0x8d0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR42_HIGH_OFST))

/*
 * Register : Register 565 (MAC Address42 Low Register) - MAC_Address42_Low
 * 
 * The MAC Address42 Low register holds the lower 32 bits of the 43th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address42 [31:0]
 * 
 */
/*
 * Field : MAC Address42 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 43th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR42_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR42_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address42 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR42_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR42_LOW_s  ALT_EMAC_GMAC_MAC_ADDR42_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_OFST        0x8d4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR42_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR42_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR42_LOW_OFST))

/*
 * Register : Register 566 (MAC Address43 High Register) - MAC_Address43_High
 * 
 * The MAC Address43 High register holds the upper 16 bits of the 44th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address43 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address43 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address43 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 44th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address43 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address43 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address43 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address43 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address43 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address43 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address43[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address43[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 44th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR43_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR43_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address43 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR43_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR43_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR43_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_OFST        0x8d8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR43_HIGH_OFST))

/*
 * Register : Register 567 (MAC Address43 Low Register) - MAC_Address43_Low
 * 
 * The MAC Address43 Low register holds the lower 32 bits of the 44th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address43 [31:0]
 * 
 */
/*
 * Field : MAC Address43 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 44th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR43_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR43_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address43 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR43_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR43_LOW_s  ALT_EMAC_GMAC_MAC_ADDR43_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_OFST        0x8dc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR43_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR43_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR43_LOW_OFST))

/*
 * Register : Register 568 (MAC Address44 High Register) - MAC_Address44_High
 * 
 * The MAC Address44 High register holds the upper 16 bits of the 45th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address44 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address44 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address44 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 45th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address44 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address44 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address44 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address44 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address44 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address44 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address44[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address44[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 45th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR44_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR44_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address44 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR44_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR44_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR44_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_OFST        0x8e0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR44_HIGH_OFST))

/*
 * Register : Register 569 (MAC Address44 Low Register) - MAC_Address44_Low
 * 
 * The MAC Address44 Low register holds the lower 32 bits of the 45th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address44 [31:0]
 * 
 */
/*
 * Field : MAC Address44 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 45th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR44_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR44_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address44 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR44_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR44_LOW_s  ALT_EMAC_GMAC_MAC_ADDR44_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_OFST        0x8e4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR44_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR44_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR44_LOW_OFST))

/*
 * Register : Register 570 (MAC Address45 High Register) - MAC_Address45_High
 * 
 * The MAC Address45 High register holds the upper 16 bits of the 46th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address45 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address45 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address45 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 46th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address45 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address45 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address45 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address45 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address45 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address45 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address45[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address45[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 46th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR45_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR45_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address45 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR45_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR45_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR45_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_OFST        0x8e8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR45_HIGH_OFST))

/*
 * Register : Register 571 (MAC Address45 Low Register) - MAC_Address45_Low
 * 
 * The MAC Address45 Low register holds the lower 32 bits of the 46th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address45 [31:0]
 * 
 */
/*
 * Field : MAC Address45 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 46th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR45_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR45_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address45 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR45_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR45_LOW_s  ALT_EMAC_GMAC_MAC_ADDR45_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_OFST        0x8ec
/* The address of the ALT_EMAC_GMAC_MAC_ADDR45_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR45_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR45_LOW_OFST))

/*
 * Register : Register 572 (MAC Address46 High Register) - MAC_Address46_High
 * 
 * The MAC Address46 High register holds the upper 16 bits of the 47th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address46 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address46 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address46 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 47th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address46 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address46 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address46 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address46 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address46 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address46 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address46[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address46[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 47th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR46_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR46_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address46 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR46_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR46_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR46_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_OFST        0x8f0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR46_HIGH_OFST))

/*
 * Register : Register 573 (MAC Address46 Low Register) - MAC_Address46_Low
 * 
 * The MAC Address46 Low register holds the lower 32 bits of the 47th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address46 [31:0]
 * 
 */
/*
 * Field : MAC Address46 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 47th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR46_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR46_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address46 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR46_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR46_LOW_s  ALT_EMAC_GMAC_MAC_ADDR46_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_OFST        0x8f4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR46_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR46_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR46_LOW_OFST))

/*
 * Register : Register 574 (MAC Address47 High Register) - MAC_Address47_High
 * 
 * The MAC Address47 High register holds the upper 16 bits of the 48th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address47 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address47 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address47 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 48th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address47 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address47 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address47 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address47 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address47 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address47 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address47[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address47[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 48th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR47_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR47_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address47 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR47_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR47_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR47_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_OFST        0x8f8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR47_HIGH_OFST))

/*
 * Register : Register 575 (MAC Address47 Low Register) - MAC_Address47_Low
 * 
 * The MAC Address47 Low register holds the lower 32 bits of the 48th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address47 [31:0]
 * 
 */
/*
 * Field : MAC Address47 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 48th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR47_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR47_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address47 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR47_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR47_LOW_s  ALT_EMAC_GMAC_MAC_ADDR47_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_OFST        0x8fc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR47_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR47_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR47_LOW_OFST))

/*
 * Register : Register 576 (MAC Address48 High Register) - MAC_Address48_High
 * 
 * The MAC Address48 High register holds the upper 16 bits of the 49th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address48 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address48 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address48 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 49th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address48 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address48 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address48 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address48 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address48 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address48 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address48[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address48[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 49th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR48_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR48_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address48 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR48_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR48_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR48_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_OFST        0x900
/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR48_HIGH_OFST))

/*
 * Register : Register 577 (MAC Address48 Low Register) - MAC_Address48_Low
 * 
 * The MAC Address48 Low register holds the lower 32 bits of the 49th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address48 [31:0]
 * 
 */
/*
 * Field : MAC Address48 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 49th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR48_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR48_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address48 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR48_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR48_LOW_s  ALT_EMAC_GMAC_MAC_ADDR48_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_OFST        0x904
/* The address of the ALT_EMAC_GMAC_MAC_ADDR48_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR48_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR48_LOW_OFST))

/*
 * Register : Register 578 (MAC Address49 High Register) - MAC_Address49_High
 * 
 * The MAC Address49 High register holds the upper 16 bits of the 50th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address49 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address49 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address49 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 50th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address49 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address49 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address49 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address49 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address49 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address49 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address49[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address49[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 50th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR49_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR49_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address49 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR49_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR49_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR49_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_OFST        0x908
/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR49_HIGH_OFST))

/*
 * Register : Register 579 (MAC Address49 Low Register) - MAC_Address49_Low
 * 
 * The MAC Address49 Low register holds the lower 32 bits of the 50th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address49 [31:0]
 * 
 */
/*
 * Field : MAC Address49 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 50th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR49_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR49_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address49 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR49_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR49_LOW_s  ALT_EMAC_GMAC_MAC_ADDR49_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_OFST        0x90c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR49_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR49_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR49_LOW_OFST))

/*
 * Register : Register 580 (MAC Address50 High Register) - MAC_Address50_High
 * 
 * The MAC Address50 High register holds the upper 16 bits of the 51th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address50 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address50 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address50 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 51th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address50 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address50 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address50 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address50 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address50 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address50 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address50[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address50[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 51th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR50_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR50_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address50 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR50_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR50_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR50_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_OFST        0x910
/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR50_HIGH_OFST))

/*
 * Register : Register 581 (MAC Address50 Low Register) - MAC_Address50_Low
 * 
 * The MAC Address50 Low register holds the lower 32 bits of the 51th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address50 [31:0]
 * 
 */
/*
 * Field : MAC Address50 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 51th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR50_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR50_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address50 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR50_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR50_LOW_s  ALT_EMAC_GMAC_MAC_ADDR50_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_OFST        0x914
/* The address of the ALT_EMAC_GMAC_MAC_ADDR50_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR50_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR50_LOW_OFST))

/*
 * Register : Register 582 (MAC Address51 High Register) - MAC_Address51_High
 * 
 * The MAC Address51 High register holds the upper 16 bits of the 52th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address51 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address51 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address51 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 52th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address51 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address51 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address51 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address51 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address51 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address51 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address51[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address51[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 52th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR51_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR51_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address51 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR51_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR51_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR51_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_OFST        0x918
/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR51_HIGH_OFST))

/*
 * Register : Register 583 (MAC Address51 Low Register) - MAC_Address51_Low
 * 
 * The MAC Address51 Low register holds the lower 32 bits of the 52th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address51 [31:0]
 * 
 */
/*
 * Field : MAC Address51 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 52th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR51_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR51_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address51 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR51_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR51_LOW_s  ALT_EMAC_GMAC_MAC_ADDR51_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_OFST        0x91c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR51_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR51_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR51_LOW_OFST))

/*
 * Register : Register 584 (MAC Address52 High Register) - MAC_Address52_High
 * 
 * The MAC Address52 High register holds the upper 16 bits of the 53th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address52 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address52 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address52 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 53th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address52 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address52 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address52 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address52 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address52 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address52 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address52[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address52[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 53th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR52_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR52_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address52 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR52_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR52_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR52_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_OFST        0x920
/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR52_HIGH_OFST))

/*
 * Register : Register 585 (MAC Address52 Low Register) - MAC_Address52_Low
 * 
 * The MAC Address52 Low register holds the lower 32 bits of the 53th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address52 [31:0]
 * 
 */
/*
 * Field : MAC Address52 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 53th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR52_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR52_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address52 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR52_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR52_LOW_s  ALT_EMAC_GMAC_MAC_ADDR52_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_OFST        0x924
/* The address of the ALT_EMAC_GMAC_MAC_ADDR52_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR52_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR52_LOW_OFST))

/*
 * Register : Register 586 (MAC Address53 High Register) - MAC_Address53_High
 * 
 * The MAC Address53 High register holds the upper 16 bits of the 54th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address53 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address53 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address53 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 54th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address53 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address53 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address53 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address53 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address53 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address53 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address53[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address53[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 54th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR53_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR53_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address53 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR53_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR53_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR53_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_OFST        0x928
/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR53_HIGH_OFST))

/*
 * Register : Register 587 (MAC Address53 Low Register) - MAC_Address53_Low
 * 
 * The MAC Address53 Low register holds the lower 32 bits of the 54th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address53 [31:0]
 * 
 */
/*
 * Field : MAC Address53 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 54th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR53_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR53_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address53 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR53_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR53_LOW_s  ALT_EMAC_GMAC_MAC_ADDR53_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_OFST        0x92c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR53_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR53_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR53_LOW_OFST))

/*
 * Register : Register 588 (MAC Address54 High Register) - MAC_Address54_High
 * 
 * The MAC Address54 High register holds the upper 16 bits of the 55th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address54 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address54 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address54 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 55th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address54 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address54 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address54 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address54 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address54 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address54 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address54[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address54[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 55th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR54_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR54_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address54 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR54_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR54_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR54_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_OFST        0x930
/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR54_HIGH_OFST))

/*
 * Register : Register 589 (MAC Address54 Low Register) - MAC_Address54_Low
 * 
 * The MAC Address54 Low register holds the lower 32 bits of the 55th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address54 [31:0]
 * 
 */
/*
 * Field : MAC Address54 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 55th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR54_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR54_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address54 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR54_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR54_LOW_s  ALT_EMAC_GMAC_MAC_ADDR54_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_OFST        0x934
/* The address of the ALT_EMAC_GMAC_MAC_ADDR54_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR54_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR54_LOW_OFST))

/*
 * Register : Register 590 (MAC Address55 High Register) - MAC_Address55_High
 * 
 * The MAC Address55 High register holds the upper 16 bits of the 56th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address55 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address55 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address55 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 56th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address55 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address55 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address55 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address55 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address55 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address55 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address55[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address55[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 56th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR55_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR55_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address55 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR55_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR55_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR55_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_OFST        0x938
/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR55_HIGH_OFST))

/*
 * Register : Register 591 (MAC Address55 Low Register) - MAC_Address55_Low
 * 
 * The MAC Address55 Low register holds the lower 32 bits of the 56th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address55 [31:0]
 * 
 */
/*
 * Field : MAC Address55 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 56th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR55_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR55_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address55 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR55_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR55_LOW_s  ALT_EMAC_GMAC_MAC_ADDR55_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_OFST        0x93c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR55_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR55_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR55_LOW_OFST))

/*
 * Register : Register 592 (MAC Address56 High Register) - MAC_Address56_High
 * 
 * The MAC Address56 High register holds the upper 16 bits of the 57th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address56 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address56 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address56 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 57th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address56 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address56 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address56 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address56 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address56 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address56 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address56[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address56[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 57th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR56_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR56_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address56 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR56_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR56_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR56_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_OFST        0x940
/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR56_HIGH_OFST))

/*
 * Register : Register 593 (MAC Address56 Low Register) - MAC_Address56_Low
 * 
 * The MAC Address56 Low register holds the lower 32 bits of the 57th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address56 [31:0]
 * 
 */
/*
 * Field : MAC Address56 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 57th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR56_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR56_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address56 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR56_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR56_LOW_s  ALT_EMAC_GMAC_MAC_ADDR56_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_OFST        0x944
/* The address of the ALT_EMAC_GMAC_MAC_ADDR56_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR56_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR56_LOW_OFST))

/*
 * Register : Register 594 (MAC Address57 High Register) - MAC_Address57_High
 * 
 * The MAC Address57 High register holds the upper 16 bits of the 58th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address57 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address57 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address57 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 58th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address57 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address57 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address57 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address57 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address57 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address57 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address57[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address57[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 58th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR57_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR57_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address57 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR57_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR57_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR57_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_OFST        0x948
/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR57_HIGH_OFST))

/*
 * Register : Register 595 (MAC Address57 Low Register) - MAC_Address57_Low
 * 
 * The MAC Address57 Low register holds the lower 32 bits of the 58th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address57 [31:0]
 * 
 */
/*
 * Field : MAC Address57 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 58th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR57_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR57_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address57 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR57_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR57_LOW_s  ALT_EMAC_GMAC_MAC_ADDR57_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_OFST        0x94c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR57_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR57_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR57_LOW_OFST))

/*
 * Register : Register 596 (MAC Address58 High Register) - MAC_Address58_High
 * 
 * The MAC Address58 High register holds the upper 16 bits of the 59th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address58 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address58 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address58 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 59th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address58 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address58 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address58 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address58 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address58 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address58 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address58[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address58[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 59th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR58_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR58_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address58 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR58_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR58_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR58_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_OFST        0x950
/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR58_HIGH_OFST))

/*
 * Register : Register 597 (MAC Address58 Low Register) - MAC_Address58_Low
 * 
 * The MAC Address58 Low register holds the lower 32 bits of the 59th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address58 [31:0]
 * 
 */
/*
 * Field : MAC Address58 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 59th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR58_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR58_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address58 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR58_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR58_LOW_s  ALT_EMAC_GMAC_MAC_ADDR58_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_OFST        0x954
/* The address of the ALT_EMAC_GMAC_MAC_ADDR58_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR58_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR58_LOW_OFST))

/*
 * Register : Register 598 (MAC Address59 High Register) - MAC_Address59_High
 * 
 * The MAC Address59 High register holds the upper 16 bits of the 60th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address59 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address59 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address59 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 60th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address59 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address59 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address59 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address59 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address59 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address59 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address59[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address59[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 60th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR59_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR59_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address59 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR59_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR59_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR59_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_OFST        0x958
/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR59_HIGH_OFST))

/*
 * Register : Register 599 (MAC Address59 Low Register) - MAC_Address59_Low
 * 
 * The MAC Address59 Low register holds the lower 32 bits of the 60th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address59 [31:0]
 * 
 */
/*
 * Field : MAC Address59 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 60th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR59_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR59_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address59 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR59_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR59_LOW_s  ALT_EMAC_GMAC_MAC_ADDR59_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_OFST        0x95c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR59_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR59_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR59_LOW_OFST))

/*
 * Register : Register 600 (MAC Address60 High Register) - MAC_Address60_High
 * 
 * The MAC Address60 High register holds the upper 16 bits of the 61th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address60 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address60 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address60 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 61th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address60 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address60 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address60 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address60 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address60 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address60 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address60[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address60[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 61th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR60_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR60_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address60 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR60_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR60_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR60_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_OFST        0x960
/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR60_HIGH_OFST))

/*
 * Register : Register 601 (MAC Address60 Low Register) - MAC_Address60_Low
 * 
 * The MAC Address60 Low register holds the lower 32 bits of the 61th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address60 [31:0]
 * 
 */
/*
 * Field : MAC Address60 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 61th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR60_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR60_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address60 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR60_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR60_LOW_s  ALT_EMAC_GMAC_MAC_ADDR60_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_OFST        0x964
/* The address of the ALT_EMAC_GMAC_MAC_ADDR60_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR60_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR60_LOW_OFST))

/*
 * Register : Register 602 (MAC Address61 High Register) - MAC_Address61_High
 * 
 * The MAC Address61 High register holds the upper 16 bits of the 62th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address61 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address61 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address61 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 62th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address61 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address61 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address61 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address61 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address61 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address61 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address61[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address61[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 62th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR61_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR61_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address61 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR61_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR61_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR61_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_OFST        0x968
/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR61_HIGH_OFST))

/*
 * Register : Register 603 (MAC Address61 Low Register) - MAC_Address61_Low
 * 
 * The MAC Address61 Low register holds the lower 32 bits of the 62th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address61 [31:0]
 * 
 */
/*
 * Field : MAC Address61 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 62th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR61_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR61_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address61 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR61_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR61_LOW_s  ALT_EMAC_GMAC_MAC_ADDR61_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_OFST        0x96c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR61_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR61_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR61_LOW_OFST))

/*
 * Register : Register 604 (MAC Address62 High Register) - MAC_Address62_High
 * 
 * The MAC Address62 High register holds the upper 16 bits of the 63th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address62 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address62 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address62 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 63th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address62 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address62 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address62 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address62 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address62 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address62 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address62[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address62[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 63th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR62_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR62_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address62 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR62_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR62_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR62_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_OFST        0x970
/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR62_HIGH_OFST))

/*
 * Register : Register 605 (MAC Address62 Low Register) - MAC_Address62_Low
 * 
 * The MAC Address62 Low register holds the lower 32 bits of the 63th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address62 [31:0]
 * 
 */
/*
 * Field : MAC Address62 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 63th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR62_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR62_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address62 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR62_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR62_LOW_s  ALT_EMAC_GMAC_MAC_ADDR62_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_OFST        0x974
/* The address of the ALT_EMAC_GMAC_MAC_ADDR62_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR62_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR62_LOW_OFST))

/*
 * Register : Register 606 (MAC Address63 High Register) - MAC_Address63_High
 * 
 * The MAC Address63 High register holds the upper 16 bits of the 64th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address63 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address63 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address63 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 64th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address63 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address63 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address63 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address63 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address63 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address63 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address63[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address63[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 64th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR63_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR63_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address63 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR63_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR63_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR63_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_OFST        0x978
/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR63_HIGH_OFST))

/*
 * Register : Register 607 (MAC Address63 Low Register) - MAC_Address63_Low
 * 
 * The MAC Address63 Low register holds the lower 32 bits of the 64th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address63 [31:0]
 * 
 */
/*
 * Field : MAC Address63 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 64th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR63_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR63_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address63 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR63_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR63_LOW_s  ALT_EMAC_GMAC_MAC_ADDR63_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_OFST        0x97c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR63_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR63_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR63_LOW_OFST))

/*
 * Register : Register 608 (MAC Address64 High Register) - MAC_Address64_High
 * 
 * The MAC Address64 High register holds the upper 16 bits of the 65th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address64 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address64 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address64 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 65th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address64 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address64 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address64 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address64 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address64 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address64 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address64[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address64[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 65th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR64_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR64_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address64 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR64_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR64_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR64_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_OFST        0x980
/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR64_HIGH_OFST))

/*
 * Register : Register 609 (MAC Address64 Low Register) - MAC_Address64_Low
 * 
 * The MAC Address64 Low register holds the lower 32 bits of the 65th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address64 [31:0]
 * 
 */
/*
 * Field : MAC Address64 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 65th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR64_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR64_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address64 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR64_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR64_LOW_s  ALT_EMAC_GMAC_MAC_ADDR64_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_OFST        0x984
/* The address of the ALT_EMAC_GMAC_MAC_ADDR64_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR64_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR64_LOW_OFST))

/*
 * Register : Register 610 (MAC Address65 High Register) - MAC_Address65_High
 * 
 * The MAC Address65 High register holds the upper 16 bits of the 66th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address65 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address65 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address65 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 66th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address65 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address65 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address65 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address65 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address65 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address65 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address65[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address65[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 66th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR65_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR65_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address65 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR65_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR65_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR65_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_OFST        0x988
/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR65_HIGH_OFST))

/*
 * Register : Register 611 (MAC Address65 Low Register) - MAC_Address65_Low
 * 
 * The MAC Address65 Low register holds the lower 32 bits of the 66th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address65 [31:0]
 * 
 */
/*
 * Field : MAC Address65 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 66th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR65_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR65_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address65 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR65_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR65_LOW_s  ALT_EMAC_GMAC_MAC_ADDR65_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_OFST        0x98c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR65_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR65_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR65_LOW_OFST))

/*
 * Register : Register 612 (MAC Address66 High Register) - MAC_Address66_High
 * 
 * The MAC Address66 High register holds the upper 16 bits of the 67th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address66 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address66 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address66 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 67th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address66 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address66 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address66 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address66 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address66 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address66 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address66[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address66[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 67th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR66_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR66_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address66 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR66_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR66_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR66_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_OFST        0x990
/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR66_HIGH_OFST))

/*
 * Register : Register 613 (MAC Address66 Low Register) - MAC_Address66_Low
 * 
 * The MAC Address66 Low register holds the lower 32 bits of the 67th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address66 [31:0]
 * 
 */
/*
 * Field : MAC Address66 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 67th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR66_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR66_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address66 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR66_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR66_LOW_s  ALT_EMAC_GMAC_MAC_ADDR66_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_OFST        0x994
/* The address of the ALT_EMAC_GMAC_MAC_ADDR66_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR66_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR66_LOW_OFST))

/*
 * Register : Register 614 (MAC Address67 High Register) - MAC_Address67_High
 * 
 * The MAC Address67 High register holds the upper 16 bits of the 68th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address67 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address67 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address67 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 68th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address67 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address67 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address67 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address67 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address67 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address67 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address67[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address67[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 68th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR67_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR67_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address67 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR67_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR67_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR67_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_OFST        0x998
/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR67_HIGH_OFST))

/*
 * Register : Register 615 (MAC Address67 Low Register) - MAC_Address67_Low
 * 
 * The MAC Address67 Low register holds the lower 32 bits of the 68th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address67 [31:0]
 * 
 */
/*
 * Field : MAC Address67 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 68th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR67_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR67_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address67 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR67_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR67_LOW_s  ALT_EMAC_GMAC_MAC_ADDR67_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_OFST        0x99c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR67_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR67_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR67_LOW_OFST))

/*
 * Register : Register 616 (MAC Address68 High Register) - MAC_Address68_High
 * 
 * The MAC Address68 High register holds the upper 16 bits of the 69th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address68 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address68 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address68 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 69th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address68 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address68 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address68 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address68 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address68 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address68 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address68[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address68[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 69th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR68_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR68_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address68 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR68_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR68_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR68_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_OFST        0x9a0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR68_HIGH_OFST))

/*
 * Register : Register 617 (MAC Address68 Low Register) - MAC_Address68_Low
 * 
 * The MAC Address68 Low register holds the lower 32 bits of the 69th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address68 [31:0]
 * 
 */
/*
 * Field : MAC Address68 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 69th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR68_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR68_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address68 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR68_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR68_LOW_s  ALT_EMAC_GMAC_MAC_ADDR68_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_OFST        0x9a4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR68_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR68_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR68_LOW_OFST))

/*
 * Register : Register 618 (MAC Address69 High Register) - MAC_Address69_High
 * 
 * The MAC Address69 High register holds the upper 16 bits of the 70th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address69 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address69 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address69 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 70th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address69 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address69 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address69 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address69 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address69 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address69 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address69[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address69[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 70th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR69_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR69_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address69 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR69_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR69_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR69_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_OFST        0x9a8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR69_HIGH_OFST))

/*
 * Register : Register 619 (MAC Address69 Low Register) - MAC_Address69_Low
 * 
 * The MAC Address69 Low register holds the lower 32 bits of the 70th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address69 [31:0]
 * 
 */
/*
 * Field : MAC Address69 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 70th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR69_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR69_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address69 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR69_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR69_LOW_s  ALT_EMAC_GMAC_MAC_ADDR69_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_OFST        0x9ac
/* The address of the ALT_EMAC_GMAC_MAC_ADDR69_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR69_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR69_LOW_OFST))

/*
 * Register : Register 620 (MAC Address70 High Register) - MAC_Address70_High
 * 
 * The MAC Address70 High register holds the upper 16 bits of the 71th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address70 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address70 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address70 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 71th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address70 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address70 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address70 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address70 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address70 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address70 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address70[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address70[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 71th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR70_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR70_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address70 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR70_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR70_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR70_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_OFST        0x9b0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR70_HIGH_OFST))

/*
 * Register : Register 621 (MAC Address70 Low Register) - MAC_Address70_Low
 * 
 * The MAC Address70 Low register holds the lower 32 bits of the 71th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address70 [31:0]
 * 
 */
/*
 * Field : MAC Address70 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 71th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR70_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR70_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address70 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR70_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR70_LOW_s  ALT_EMAC_GMAC_MAC_ADDR70_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_OFST        0x9b4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR70_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR70_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR70_LOW_OFST))

/*
 * Register : Register 622 (MAC Address71 High Register) - MAC_Address71_High
 * 
 * The MAC Address71 High register holds the upper 16 bits of the 72th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address71 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address71 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address71 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 72th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address71 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address71 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address71 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address71 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address71 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address71 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address71[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address71[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 72th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR71_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR71_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address71 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR71_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR71_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR71_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_OFST        0x9b8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR71_HIGH_OFST))

/*
 * Register : Register 623 (MAC Address71 Low Register) - MAC_Address71_Low
 * 
 * The MAC Address71 Low register holds the lower 32 bits of the 72th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address71 [31:0]
 * 
 */
/*
 * Field : MAC Address71 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 72th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR71_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR71_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address71 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR71_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR71_LOW_s  ALT_EMAC_GMAC_MAC_ADDR71_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_OFST        0x9bc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR71_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR71_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR71_LOW_OFST))

/*
 * Register : Register 624 (MAC Address72 High Register) - MAC_Address72_High
 * 
 * The MAC Address72 High register holds the upper 16 bits of the 73th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address72 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address72 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address72 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 73th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address72 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address72 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address72 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address72 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address72 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address72 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address72[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address72[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 73th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR72_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR72_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address72 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR72_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR72_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR72_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_OFST        0x9c0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR72_HIGH_OFST))

/*
 * Register : Register 625 (MAC Address72 Low Register) - MAC_Address72_Low
 * 
 * The MAC Address72 Low register holds the lower 32 bits of the 73th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address72 [31:0]
 * 
 */
/*
 * Field : MAC Address72 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 73th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR72_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR72_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address72 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR72_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR72_LOW_s  ALT_EMAC_GMAC_MAC_ADDR72_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_OFST        0x9c4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR72_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR72_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR72_LOW_OFST))

/*
 * Register : Register 626 (MAC Address73 High Register) - MAC_Address73_High
 * 
 * The MAC Address73 High register holds the upper 16 bits of the 74th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address73 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address73 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address73 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 74th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address73 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address73 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address73 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address73 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address73 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address73 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address73[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address73[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 74th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR73_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR73_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address73 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR73_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR73_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR73_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_OFST        0x9c8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR73_HIGH_OFST))

/*
 * Register : Register 627 (MAC Address73 Low Register) - MAC_Address73_Low
 * 
 * The MAC Address73 Low register holds the lower 32 bits of the 74th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address73 [31:0]
 * 
 */
/*
 * Field : MAC Address73 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 74th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR73_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR73_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address73 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR73_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR73_LOW_s  ALT_EMAC_GMAC_MAC_ADDR73_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_OFST        0x9cc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR73_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR73_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR73_LOW_OFST))

/*
 * Register : Register 628 (MAC Address74 High Register) - MAC_Address74_High
 * 
 * The MAC Address74 High register holds the upper 16 bits of the 75th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address74 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address74 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address74 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 75th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address74 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address74 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address74 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address74 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address74 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address74 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address74[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address74[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 75th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR74_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR74_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address74 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR74_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR74_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR74_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_OFST        0x9d0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR74_HIGH_OFST))

/*
 * Register : Register 629 (MAC Address74 Low Register) - MAC_Address74_Low
 * 
 * The MAC Address74 Low register holds the lower 32 bits of the 75th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address74 [31:0]
 * 
 */
/*
 * Field : MAC Address74 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 75th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR74_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR74_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address74 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR74_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR74_LOW_s  ALT_EMAC_GMAC_MAC_ADDR74_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_OFST        0x9d4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR74_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR74_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR74_LOW_OFST))

/*
 * Register : Register 630 (MAC Address75 High Register) - MAC_Address75_High
 * 
 * The MAC Address75 High register holds the upper 16 bits of the 76th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address75 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address75 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address75 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 76th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address75 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address75 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address75 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address75 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address75 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address75 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address75[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address75[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 76th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR75_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR75_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address75 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR75_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR75_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR75_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_OFST        0x9d8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR75_HIGH_OFST))

/*
 * Register : Register 631 (MAC Address75 Low Register) - MAC_Address75_Low
 * 
 * The MAC Address75 Low register holds the lower 32 bits of the 76th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address75 [31:0]
 * 
 */
/*
 * Field : MAC Address75 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 76th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR75_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR75_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address75 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR75_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR75_LOW_s  ALT_EMAC_GMAC_MAC_ADDR75_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_OFST        0x9dc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR75_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR75_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR75_LOW_OFST))

/*
 * Register : Register 632 (MAC Address76 High Register) - MAC_Address76_High
 * 
 * The MAC Address76 High register holds the upper 16 bits of the 77th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address76 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address76 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address76 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 77th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address76 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address76 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address76 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address76 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address76 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address76 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address76[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address76[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 77th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR76_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR76_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address76 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR76_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR76_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR76_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_OFST        0x9e0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR76_HIGH_OFST))

/*
 * Register : Register 633 (MAC Address76 Low Register) - MAC_Address76_Low
 * 
 * The MAC Address76 Low register holds the lower 32 bits of the 77th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address76 [31:0]
 * 
 */
/*
 * Field : MAC Address76 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 77th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR76_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR76_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address76 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR76_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR76_LOW_s  ALT_EMAC_GMAC_MAC_ADDR76_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_OFST        0x9e4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR76_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR76_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR76_LOW_OFST))

/*
 * Register : Register 634 (MAC Address77 High Register) - MAC_Address77_High
 * 
 * The MAC Address77 High register holds the upper 16 bits of the 78th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address77 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address77 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address77 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 78th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address77 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address77 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address77 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address77 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address77 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address77 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address77[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address77[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 78th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR77_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR77_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address77 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR77_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR77_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR77_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_OFST        0x9e8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR77_HIGH_OFST))

/*
 * Register : Register 635 (MAC Address77 Low Register) - MAC_Address77_Low
 * 
 * The MAC Address77 Low register holds the lower 32 bits of the 78th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address77 [31:0]
 * 
 */
/*
 * Field : MAC Address77 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 78th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR77_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR77_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address77 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR77_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR77_LOW_s  ALT_EMAC_GMAC_MAC_ADDR77_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_OFST        0x9ec
/* The address of the ALT_EMAC_GMAC_MAC_ADDR77_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR77_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR77_LOW_OFST))

/*
 * Register : Register 636 (MAC Address78 High Register) - MAC_Address78_High
 * 
 * The MAC Address78 High register holds the upper 16 bits of the 79th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address78 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address78 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address78 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 79th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address78 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address78 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address78 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address78 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address78 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address78 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address78[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address78[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 79th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR78_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR78_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address78 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR78_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR78_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR78_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_OFST        0x9f0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR78_HIGH_OFST))

/*
 * Register : Register 637 (MAC Address78 Low Register) - MAC_Address78_Low
 * 
 * The MAC Address78 Low register holds the lower 32 bits of the 79th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address78 [31:0]
 * 
 */
/*
 * Field : MAC Address78 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 79th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR78_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR78_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address78 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR78_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR78_LOW_s  ALT_EMAC_GMAC_MAC_ADDR78_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_OFST        0x9f4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR78_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR78_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR78_LOW_OFST))

/*
 * Register : Register 638 (MAC Address79 High Register) - MAC_Address79_High
 * 
 * The MAC Address79 High register holds the upper 16 bits of the 80th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address79 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address79 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address79 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 80th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address79 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address79 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address79 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address79 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address79 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address79 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address79[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address79[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 80th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR79_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR79_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address79 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR79_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR79_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR79_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_OFST        0x9f8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR79_HIGH_OFST))

/*
 * Register : Register 639 (MAC Address79 Low Register) - MAC_Address79_Low
 * 
 * The MAC Address79 Low register holds the lower 32 bits of the 80th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address79 [31:0]
 * 
 */
/*
 * Field : MAC Address79 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 80th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR79_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR79_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address79 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR79_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR79_LOW_s  ALT_EMAC_GMAC_MAC_ADDR79_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_OFST        0x9fc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR79_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR79_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR79_LOW_OFST))

/*
 * Register : Register 640 (MAC Address80 High Register) - MAC_Address80_High
 * 
 * The MAC Address80 High register holds the upper 16 bits of the 81th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address80 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address80 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address80 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 81th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address80 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address80 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address80 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address80 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address80 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address80 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address80[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address80[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 81th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR80_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR80_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address80 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR80_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR80_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR80_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_OFST        0xa00
/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR80_HIGH_OFST))

/*
 * Register : Register 641 (MAC Address80 Low Register) - MAC_Address80_Low
 * 
 * The MAC Address80 Low register holds the lower 32 bits of the 81th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address80 [31:0]
 * 
 */
/*
 * Field : MAC Address80 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 81th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR80_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR80_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address80 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR80_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR80_LOW_s  ALT_EMAC_GMAC_MAC_ADDR80_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_OFST        0xa04
/* The address of the ALT_EMAC_GMAC_MAC_ADDR80_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR80_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR80_LOW_OFST))

/*
 * Register : Register 642 (MAC Address81 High Register) - MAC_Address81_High
 * 
 * The MAC Address81 High register holds the upper 16 bits of the 82th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address81 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address81 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address81 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 82th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address81 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address81 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address81 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address81 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address81 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address81 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address81[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address81[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 82th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR81_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR81_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address81 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR81_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR81_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR81_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_OFST        0xa08
/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR81_HIGH_OFST))

/*
 * Register : Register 643 (MAC Address81 Low Register) - MAC_Address81_Low
 * 
 * The MAC Address81 Low register holds the lower 32 bits of the 82th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address81 [31:0]
 * 
 */
/*
 * Field : MAC Address81 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 82th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR81_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR81_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address81 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR81_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR81_LOW_s  ALT_EMAC_GMAC_MAC_ADDR81_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_OFST        0xa0c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR81_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR81_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR81_LOW_OFST))

/*
 * Register : Register 644 (MAC Address82 High Register) - MAC_Address82_High
 * 
 * The MAC Address82 High register holds the upper 16 bits of the 83th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address82 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address82 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address82 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 83th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address82 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address82 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address82 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address82 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address82 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address82 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address82[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address82[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 83th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR82_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR82_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address82 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR82_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR82_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR82_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_OFST        0xa10
/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR82_HIGH_OFST))

/*
 * Register : Register 645 (MAC Address82 Low Register) - MAC_Address82_Low
 * 
 * The MAC Address82 Low register holds the lower 32 bits of the 83th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address82 [31:0]
 * 
 */
/*
 * Field : MAC Address82 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 83th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR82_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR82_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address82 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR82_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR82_LOW_s  ALT_EMAC_GMAC_MAC_ADDR82_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_OFST        0xa14
/* The address of the ALT_EMAC_GMAC_MAC_ADDR82_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR82_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR82_LOW_OFST))

/*
 * Register : Register 646 (MAC Address83 High Register) - MAC_Address83_High
 * 
 * The MAC Address83 High register holds the upper 16 bits of the 84th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address83 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address83 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address83 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 84th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address83 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address83 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address83 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address83 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address83 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address83 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address83[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address83[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 84th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR83_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR83_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address83 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR83_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR83_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR83_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_OFST        0xa18
/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR83_HIGH_OFST))

/*
 * Register : Register 647 (MAC Address83 Low Register) - MAC_Address83_Low
 * 
 * The MAC Address83 Low register holds the lower 32 bits of the 84th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address83 [31:0]
 * 
 */
/*
 * Field : MAC Address83 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 84th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR83_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR83_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address83 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR83_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR83_LOW_s  ALT_EMAC_GMAC_MAC_ADDR83_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_OFST        0xa1c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR83_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR83_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR83_LOW_OFST))

/*
 * Register : Register 648 (MAC Address84 High Register) - MAC_Address84_High
 * 
 * The MAC Address84 High register holds the upper 16 bits of the 85th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address84 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address84 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address84 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 85th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address84 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address84 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address84 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address84 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address84 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address84 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address84[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address84[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 85th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR84_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR84_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address84 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR84_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR84_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR84_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_OFST        0xa20
/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR84_HIGH_OFST))

/*
 * Register : Register 649 (MAC Address84 Low Register) - MAC_Address84_Low
 * 
 * The MAC Address84 Low register holds the lower 32 bits of the 85th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address84 [31:0]
 * 
 */
/*
 * Field : MAC Address84 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 85th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR84_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR84_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address84 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR84_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR84_LOW_s  ALT_EMAC_GMAC_MAC_ADDR84_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_OFST        0xa24
/* The address of the ALT_EMAC_GMAC_MAC_ADDR84_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR84_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR84_LOW_OFST))

/*
 * Register : Register 650 (MAC Address85 High Register) - MAC_Address85_High
 * 
 * The MAC Address85 High register holds the upper 16 bits of the 86th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address85 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address85 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address85 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 86th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address85 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address85 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address85 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address85 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address85 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address85 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address85[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address85[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 86th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR85_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR85_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address85 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR85_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR85_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR85_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_OFST        0xa28
/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR85_HIGH_OFST))

/*
 * Register : Register 651 (MAC Address85 Low Register) - MAC_Address85_Low
 * 
 * The MAC Address85 Low register holds the lower 32 bits of the 86th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address85 [31:0]
 * 
 */
/*
 * Field : MAC Address85 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 86th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR85_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR85_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address85 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR85_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR85_LOW_s  ALT_EMAC_GMAC_MAC_ADDR85_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_OFST        0xa2c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR85_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR85_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR85_LOW_OFST))

/*
 * Register : Register 652 (MAC Address86 High Register) - MAC_Address86_High
 * 
 * The MAC Address86 High register holds the upper 16 bits of the 87th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address86 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address86 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address86 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 87th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address86 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address86 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address86 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address86 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address86 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address86 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address86[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address86[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 87th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR86_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR86_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address86 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR86_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR86_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR86_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_OFST        0xa30
/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR86_HIGH_OFST))

/*
 * Register : Register 653 (MAC Address86 Low Register) - MAC_Address86_Low
 * 
 * The MAC Address86 Low register holds the lower 32 bits of the 87th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address86 [31:0]
 * 
 */
/*
 * Field : MAC Address86 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 87th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR86_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR86_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address86 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR86_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR86_LOW_s  ALT_EMAC_GMAC_MAC_ADDR86_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_OFST        0xa34
/* The address of the ALT_EMAC_GMAC_MAC_ADDR86_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR86_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR86_LOW_OFST))

/*
 * Register : Register 654 (MAC Address87 High Register) - MAC_Address87_High
 * 
 * The MAC Address87 High register holds the upper 16 bits of the 88th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address87 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address87 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address87 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 88th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address87 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address87 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address87 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address87 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address87 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address87 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address87[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address87[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 88th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR87_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR87_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address87 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR87_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR87_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR87_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_OFST        0xa38
/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR87_HIGH_OFST))

/*
 * Register : Register 655 (MAC Address87 Low Register) - MAC_Address87_Low
 * 
 * The MAC Address87 Low register holds the lower 32 bits of the 88th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address87 [31:0]
 * 
 */
/*
 * Field : MAC Address87 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 88th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR87_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR87_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address87 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR87_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR87_LOW_s  ALT_EMAC_GMAC_MAC_ADDR87_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_OFST        0xa3c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR87_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR87_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR87_LOW_OFST))

/*
 * Register : Register 656 (MAC Address88 High Register) - MAC_Address88_High
 * 
 * The MAC Address88 High register holds the upper 16 bits of the 89th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address88 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address88 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address88 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 89th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address88 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address88 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address88 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address88 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address88 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address88 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address88[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address88[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 89th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR88_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR88_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address88 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR88_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR88_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR88_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_OFST        0xa40
/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR88_HIGH_OFST))

/*
 * Register : Register 657 (MAC Address88 Low Register) - MAC_Address88_Low
 * 
 * The MAC Address88 Low register holds the lower 32 bits of the 89th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address88 [31:0]
 * 
 */
/*
 * Field : MAC Address88 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 89th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR88_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR88_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address88 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR88_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR88_LOW_s  ALT_EMAC_GMAC_MAC_ADDR88_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_OFST        0xa44
/* The address of the ALT_EMAC_GMAC_MAC_ADDR88_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR88_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR88_LOW_OFST))

/*
 * Register : Register 658 (MAC Address89 High Register) - MAC_Address89_High
 * 
 * The MAC Address89 High register holds the upper 16 bits of the 90th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address89 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address89 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address89 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 90th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address89 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address89 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address89 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address89 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address89 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address89 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address89[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address89[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 90th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR89_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR89_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address89 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR89_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR89_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR89_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_OFST        0xa48
/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR89_HIGH_OFST))

/*
 * Register : Register 659 (MAC Address89 Low Register) - MAC_Address89_Low
 * 
 * The MAC Address89 Low register holds the lower 32 bits of the 90th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address89 [31:0]
 * 
 */
/*
 * Field : MAC Address89 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 90th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR89_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR89_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address89 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR89_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR89_LOW_s  ALT_EMAC_GMAC_MAC_ADDR89_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_OFST        0xa4c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR89_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR89_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR89_LOW_OFST))

/*
 * Register : Register 660 (MAC Address90 High Register) - MAC_Address90_High
 * 
 * The MAC Address90 High register holds the upper 16 bits of the 91th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address90 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address90 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address90 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 91th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address90 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address90 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address90 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address90 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address90 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address90 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address90[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address90[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 91th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR90_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR90_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address90 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR90_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR90_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR90_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_OFST        0xa50
/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR90_HIGH_OFST))

/*
 * Register : Register 661 (MAC Address90 Low Register) - MAC_Address90_Low
 * 
 * The MAC Address90 Low register holds the lower 32 bits of the 91th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address90 [31:0]
 * 
 */
/*
 * Field : MAC Address90 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 91th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR90_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR90_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address90 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR90_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR90_LOW_s  ALT_EMAC_GMAC_MAC_ADDR90_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_OFST        0xa54
/* The address of the ALT_EMAC_GMAC_MAC_ADDR90_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR90_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR90_LOW_OFST))

/*
 * Register : Register 662 (MAC Address91 High Register) - MAC_Address91_High
 * 
 * The MAC Address91 High register holds the upper 16 bits of the 92th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address91 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address91 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address91 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 92th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address91 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address91 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address91 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address91 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address91 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address91 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address91[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address91[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 92th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR91_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR91_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address91 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR91_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR91_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR91_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_OFST        0xa58
/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR91_HIGH_OFST))

/*
 * Register : Register 663 (MAC Address91 Low Register) - MAC_Address91_Low
 * 
 * The MAC Address91 Low register holds the lower 32 bits of the 92th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address91 [31:0]
 * 
 */
/*
 * Field : MAC Address91 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 92th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR91_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR91_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address91 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR91_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR91_LOW_s  ALT_EMAC_GMAC_MAC_ADDR91_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_OFST        0xa5c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR91_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR91_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR91_LOW_OFST))

/*
 * Register : Register 664 (MAC Address92 High Register) - MAC_Address92_High
 * 
 * The MAC Address92 High register holds the upper 16 bits of the 93th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address92 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address92 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address92 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 93th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address92 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address92 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address92 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address92 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address92 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address92 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address92[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address92[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 93th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR92_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR92_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address92 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR92_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR92_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR92_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_OFST        0xa60
/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR92_HIGH_OFST))

/*
 * Register : Register 665 (MAC Address92 Low Register) - MAC_Address92_Low
 * 
 * The MAC Address92 Low register holds the lower 32 bits of the 93th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address92 [31:0]
 * 
 */
/*
 * Field : MAC Address92 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 93th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR92_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR92_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address92 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR92_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR92_LOW_s  ALT_EMAC_GMAC_MAC_ADDR92_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_OFST        0xa64
/* The address of the ALT_EMAC_GMAC_MAC_ADDR92_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR92_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR92_LOW_OFST))

/*
 * Register : Register 666 (MAC Address93 High Register) - MAC_Address93_High
 * 
 * The MAC Address93 High register holds the upper 16 bits of the 94th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address93 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address93 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address93 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 94th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address93 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address93 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address93 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address93 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address93 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address93 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address93[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address93[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 94th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR93_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR93_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address93 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR93_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR93_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR93_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_OFST        0xa68
/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR93_HIGH_OFST))

/*
 * Register : Register 667 (MAC Address93 Low Register) - MAC_Address93_Low
 * 
 * The MAC Address93 Low register holds the lower 32 bits of the 94th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address93 [31:0]
 * 
 */
/*
 * Field : MAC Address93 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 94th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR93_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR93_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address93 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR93_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR93_LOW_s  ALT_EMAC_GMAC_MAC_ADDR93_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_OFST        0xa6c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR93_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR93_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR93_LOW_OFST))

/*
 * Register : Register 668 (MAC Address94 High Register) - MAC_Address94_High
 * 
 * The MAC Address94 High register holds the upper 16 bits of the 95th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address94 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address94 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address94 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 95th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address94 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address94 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address94 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address94 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address94 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address94 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address94[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address94[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 95th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR94_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR94_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address94 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR94_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR94_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR94_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_OFST        0xa70
/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR94_HIGH_OFST))

/*
 * Register : Register 669 (MAC Address94 Low Register) - MAC_Address94_Low
 * 
 * The MAC Address94 Low register holds the lower 32 bits of the 95th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address94 [31:0]
 * 
 */
/*
 * Field : MAC Address94 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 95th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR94_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR94_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address94 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR94_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR94_LOW_s  ALT_EMAC_GMAC_MAC_ADDR94_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_OFST        0xa74
/* The address of the ALT_EMAC_GMAC_MAC_ADDR94_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR94_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR94_LOW_OFST))

/*
 * Register : Register 670 (MAC Address95 High Register) - MAC_Address95_High
 * 
 * The MAC Address95 High register holds the upper 16 bits of the 96th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address95 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address95 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address95 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 96th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address95 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address95 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address95 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address95 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address95 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address95 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address95[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address95[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 96th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR95_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR95_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address95 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR95_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR95_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR95_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_OFST        0xa78
/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR95_HIGH_OFST))

/*
 * Register : Register 671 (MAC Address95 Low Register) - MAC_Address95_Low
 * 
 * The MAC Address95 Low register holds the lower 32 bits of the 96th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address95 [31:0]
 * 
 */
/*
 * Field : MAC Address95 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 96th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR95_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR95_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address95 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR95_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR95_LOW_s  ALT_EMAC_GMAC_MAC_ADDR95_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_OFST        0xa7c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR95_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR95_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR95_LOW_OFST))

/*
 * Register : Register 672 (MAC Address96 High Register) - MAC_Address96_High
 * 
 * The MAC Address96 High register holds the upper 16 bits of the 97th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address96 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address96 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address96 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 97th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address96 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address96 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address96 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address96 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address96 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address96 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address96[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address96[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 97th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR96_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR96_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address96 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR96_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR96_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR96_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_OFST        0xa80
/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR96_HIGH_OFST))

/*
 * Register : Register 673 (MAC Address96 Low Register) - MAC_Address96_Low
 * 
 * The MAC Address96 Low register holds the lower 32 bits of the 97th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address96 [31:0]
 * 
 */
/*
 * Field : MAC Address96 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 97th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR96_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR96_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address96 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR96_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR96_LOW_s  ALT_EMAC_GMAC_MAC_ADDR96_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_OFST        0xa84
/* The address of the ALT_EMAC_GMAC_MAC_ADDR96_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR96_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR96_LOW_OFST))

/*
 * Register : Register 674 (MAC Address97 High Register) - MAC_Address97_High
 * 
 * The MAC Address97 High register holds the upper 16 bits of the 98th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address97 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address97 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address97 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 98th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address97 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address97 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address97 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address97 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address97 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address97 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address97[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address97[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 98th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR97_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR97_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address97 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR97_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR97_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR97_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_OFST        0xa88
/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR97_HIGH_OFST))

/*
 * Register : Register 675 (MAC Address97 Low Register) - MAC_Address97_Low
 * 
 * The MAC Address97 Low register holds the lower 32 bits of the 98th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address97 [31:0]
 * 
 */
/*
 * Field : MAC Address97 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 98th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR97_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR97_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address97 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR97_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR97_LOW_s  ALT_EMAC_GMAC_MAC_ADDR97_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_OFST        0xa8c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR97_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR97_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR97_LOW_OFST))

/*
 * Register : Register 676 (MAC Address98 High Register) - MAC_Address98_High
 * 
 * The MAC Address98 High register holds the upper 16 bits of the 99th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address98 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address98 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address98 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 99th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address98 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address98 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address98 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address98 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address98 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address98 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address98[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address98[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 99th MAC address for
 * perfect filtering. When this bit is disabled, the address filter block ignores
 * the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR98_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR98_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address98 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR98_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR98_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR98_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_OFST        0xa90
/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR98_HIGH_OFST))

/*
 * Register : Register 677 (MAC Address98 Low Register) - MAC_Address98_Low
 * 
 * The MAC Address98 Low register holds the lower 32 bits of the 99th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address98 [31:0]
 * 
 */
/*
 * Field : MAC Address98 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 99th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR98_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR98_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address98 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR98_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR98_LOW_s  ALT_EMAC_GMAC_MAC_ADDR98_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_OFST        0xa94
/* The address of the ALT_EMAC_GMAC_MAC_ADDR98_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR98_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR98_LOW_OFST))

/*
 * Register : Register 678 (MAC Address99 High Register) - MAC_Address99_High
 * 
 * The MAC Address99 High register holds the upper 16 bits of the 100th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address99 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description          
 * :--------|:-------|:-------|:----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address99 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*          
 *  [24]    | RW     | 0x0    | Mask Byte Control    
 *  [25]    | RW     | 0x0    | Mask Byte Control    
 *  [26]    | RW     | 0x0    | Mask Byte Control    
 *  [27]    | RW     | 0x0    | Mask Byte Control    
 *  [28]    | RW     | 0x0    | Mask Byte Control    
 *  [29]    | RW     | 0x0    | Mask Byte Control    
 *  [30]    | RW     | 0x0    | Source Address       
 *  [31]    | RW     | 0x0    | Address Enable       
 * 
 */
/*
 * Field : MAC Address99 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 100th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address99 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address99 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address99 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address99 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address99 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address99 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                          | Value | Description                        
 * :----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_UNMSKED   0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_E_MSKED     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address99[47:0] is used to compare with the SA
 * fields of the received frame. When this bit is disabled, the MAC Address99[47:0]
 * is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                 
 * :----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 100th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                          
 * :----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR99_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR99_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address99 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR99_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR99_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR99_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_OFST        0xa98
/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR99_HIGH_OFST))

/*
 * Register : Register 679 (MAC Address99 Low Register) - MAC_Address99_Low
 * 
 * The MAC Address99 Low register holds the lower 32 bits of the 100th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description         
 * :-------|:-------|:-----------|:---------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address99 [31:0]
 * 
 */
/*
 * Field : MAC Address99 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 100th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR99_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR99_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address99 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR99_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR99_LOW_s  ALT_EMAC_GMAC_MAC_ADDR99_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_OFST        0xa9c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR99_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR99_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR99_LOW_OFST))

/*
 * Register : Register 680 (MAC Address100 High Register) - MAC_Address100_High
 * 
 * The MAC Address100 High register holds the upper 16 bits of the 101th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address100 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address100 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address100 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 101th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address100 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address100 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address100 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address100 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address100 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address100 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address100[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address100[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 101th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR100_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR100_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address100 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR100_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR100_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR100_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_OFST        0xaa0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR100_HIGH_OFST))

/*
 * Register : Register 681 (MAC Address100 Low Register) - MAC_Address100_Low
 * 
 * The MAC Address100 Low register holds the lower 32 bits of the 101th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address100 [31:0]
 * 
 */
/*
 * Field : MAC Address100 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 101th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR100_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR100_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address100 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR100_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR100_LOW_s  ALT_EMAC_GMAC_MAC_ADDR100_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_OFST        0xaa4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR100_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR100_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR100_LOW_OFST))

/*
 * Register : Register 682 (MAC Address101 High Register) - MAC_Address101_High
 * 
 * The MAC Address101 High register holds the upper 16 bits of the 102th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address101 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address101 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address101 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 102th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address101 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address101 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address101 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address101 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address101 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address101 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address101[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address101[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 102th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR101_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR101_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address101 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR101_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR101_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR101_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_OFST        0xaa8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR101_HIGH_OFST))

/*
 * Register : Register 683 (MAC Address101 Low Register) - MAC_Address101_Low
 * 
 * The MAC Address101 Low register holds the lower 32 bits of the 102th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address101 [31:0]
 * 
 */
/*
 * Field : MAC Address101 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 102th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR101_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR101_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address101 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR101_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR101_LOW_s  ALT_EMAC_GMAC_MAC_ADDR101_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_OFST        0xaac
/* The address of the ALT_EMAC_GMAC_MAC_ADDR101_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR101_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR101_LOW_OFST))

/*
 * Register : Register 684 (MAC Address102 High Register) - MAC_Address102_High
 * 
 * The MAC Address102 High register holds the upper 16 bits of the 103th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address102 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address102 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address102 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 103th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address102 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address102 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address102 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address102 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address102 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address102 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address102[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address102[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 103th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR102_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR102_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address102 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR102_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR102_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR102_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_OFST        0xab0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR102_HIGH_OFST))

/*
 * Register : Register 685 (MAC Address102 Low Register) - MAC_Address102_Low
 * 
 * The MAC Address102 Low register holds the lower 32 bits of the 103th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address102 [31:0]
 * 
 */
/*
 * Field : MAC Address102 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 103th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR102_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR102_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address102 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR102_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR102_LOW_s  ALT_EMAC_GMAC_MAC_ADDR102_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_OFST        0xab4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR102_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR102_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR102_LOW_OFST))

/*
 * Register : Register 686 (MAC Address103 High Register) - MAC_Address103_High
 * 
 * The MAC Address103 High register holds the upper 16 bits of the 104th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address103 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address103 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address103 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 104th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address103 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address103 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address103 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address103 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address103 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address103 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address103[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address103[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 104th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR103_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR103_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address103 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR103_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR103_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR103_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_OFST        0xab8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR103_HIGH_OFST))

/*
 * Register : Register 687 (MAC Address103 Low Register) - MAC_Address103_Low
 * 
 * The MAC Address103 Low register holds the lower 32 bits of the 104th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address103 [31:0]
 * 
 */
/*
 * Field : MAC Address103 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 104th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR103_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR103_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address103 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR103_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR103_LOW_s  ALT_EMAC_GMAC_MAC_ADDR103_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_OFST        0xabc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR103_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR103_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR103_LOW_OFST))

/*
 * Register : Register 688 (MAC Address104 High Register) - MAC_Address104_High
 * 
 * The MAC Address104 High register holds the upper 16 bits of the 105th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address104 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address104 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address104 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 105th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address104 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address104 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address104 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address104 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address104 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address104 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address104[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address104[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 105th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR104_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR104_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address104 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR104_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR104_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR104_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_OFST        0xac0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR104_HIGH_OFST))

/*
 * Register : Register 689 (MAC Address104 Low Register) - MAC_Address104_Low
 * 
 * The MAC Address104 Low register holds the lower 32 bits of the 105th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address104 [31:0]
 * 
 */
/*
 * Field : MAC Address104 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 105th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR104_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR104_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address104 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR104_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR104_LOW_s  ALT_EMAC_GMAC_MAC_ADDR104_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_OFST        0xac4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR104_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR104_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR104_LOW_OFST))

/*
 * Register : Register 690 (MAC Address105 High Register) - MAC_Address105_High
 * 
 * The MAC Address105 High register holds the upper 16 bits of the 106th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address105 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address105 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address105 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 106th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address105 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address105 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address105 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address105 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address105 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address105 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address105[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address105[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 106th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR105_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR105_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address105 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR105_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR105_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR105_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_OFST        0xac8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR105_HIGH_OFST))

/*
 * Register : Register 691 (MAC Address105 Low Register) - MAC_Address105_Low
 * 
 * The MAC Address105 Low register holds the lower 32 bits of the 106th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address105 [31:0]
 * 
 */
/*
 * Field : MAC Address105 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 106th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR105_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR105_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address105 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR105_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR105_LOW_s  ALT_EMAC_GMAC_MAC_ADDR105_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_OFST        0xacc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR105_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR105_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR105_LOW_OFST))

/*
 * Register : Register 692 (MAC Address106 High Register) - MAC_Address106_High
 * 
 * The MAC Address106 High register holds the upper 16 bits of the 107th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address106 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address106 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address106 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 107th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address106 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address106 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address106 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address106 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address106 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address106 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address106[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address106[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 107th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR106_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR106_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address106 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR106_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR106_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR106_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_OFST        0xad0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR106_HIGH_OFST))

/*
 * Register : Register 693 (MAC Address106 Low Register) - MAC_Address106_Low
 * 
 * The MAC Address106 Low register holds the lower 32 bits of the 107th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address106 [31:0]
 * 
 */
/*
 * Field : MAC Address106 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 107th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR106_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR106_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address106 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR106_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR106_LOW_s  ALT_EMAC_GMAC_MAC_ADDR106_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_OFST        0xad4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR106_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR106_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR106_LOW_OFST))

/*
 * Register : Register 694 (MAC Address107 High Register) - MAC_Address107_High
 * 
 * The MAC Address107 High register holds the upper 16 bits of the 108th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address107 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address107 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address107 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 108th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address107 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address107 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address107 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address107 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address107 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address107 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address107[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address107[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 108th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR107_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR107_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address107 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR107_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR107_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR107_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_OFST        0xad8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR107_HIGH_OFST))

/*
 * Register : Register 695 (MAC Address107 Low Register) - MAC_Address107_Low
 * 
 * The MAC Address107 Low register holds the lower 32 bits of the 108th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address107 [31:0]
 * 
 */
/*
 * Field : MAC Address107 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 108th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR107_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR107_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address107 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR107_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR107_LOW_s  ALT_EMAC_GMAC_MAC_ADDR107_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_OFST        0xadc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR107_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR107_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR107_LOW_OFST))

/*
 * Register : Register 696 (MAC Address108 High Register) - MAC_Address108_High
 * 
 * The MAC Address108 High register holds the upper 16 bits of the 109th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address108 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address108 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address108 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 109th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address108 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address108 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address108 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address108 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address108 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address108 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address108[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address108[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 109th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR108_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR108_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address108 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR108_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR108_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR108_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_OFST        0xae0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR108_HIGH_OFST))

/*
 * Register : Register 697 (MAC Address108 Low Register) - MAC_Address108_Low
 * 
 * The MAC Address108 Low register holds the lower 32 bits of the 109th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address108 [31:0]
 * 
 */
/*
 * Field : MAC Address108 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 109th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR108_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR108_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address108 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR108_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR108_LOW_s  ALT_EMAC_GMAC_MAC_ADDR108_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_OFST        0xae4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR108_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR108_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR108_LOW_OFST))

/*
 * Register : Register 698 (MAC Address109 High Register) - MAC_Address109_High
 * 
 * The MAC Address109 High register holds the upper 16 bits of the 110th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address109 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address109 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address109 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 110th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address109 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address109 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address109 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address109 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address109 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address109 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address109[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address109[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 110th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR109_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR109_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address109 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR109_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR109_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR109_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_OFST        0xae8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR109_HIGH_OFST))

/*
 * Register : Register 699 (MAC Address109 Low Register) - MAC_Address109_Low
 * 
 * The MAC Address109 Low register holds the lower 32 bits of the 110th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address109 [31:0]
 * 
 */
/*
 * Field : MAC Address109 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 110th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR109_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR109_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address109 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR109_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR109_LOW_s  ALT_EMAC_GMAC_MAC_ADDR109_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_OFST        0xaec
/* The address of the ALT_EMAC_GMAC_MAC_ADDR109_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR109_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR109_LOW_OFST))

/*
 * Register : Register 700 (MAC Address110 High Register) - MAC_Address110_High
 * 
 * The MAC Address110 High register holds the upper 16 bits of the 111th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address110 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address110 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address110 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 111th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address110 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address110 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address110 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address110 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address110 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address110 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address110[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address110[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 111th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR110_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR110_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address110 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR110_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR110_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR110_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_OFST        0xaf0
/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR110_HIGH_OFST))

/*
 * Register : Register 701 (MAC Address110 Low Register) - MAC_Address110_Low
 * 
 * The MAC Address110 Low register holds the lower 32 bits of the 111th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address110 [31:0]
 * 
 */
/*
 * Field : MAC Address110 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 111th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR110_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR110_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address110 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR110_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR110_LOW_s  ALT_EMAC_GMAC_MAC_ADDR110_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_OFST        0xaf4
/* The address of the ALT_EMAC_GMAC_MAC_ADDR110_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR110_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR110_LOW_OFST))

/*
 * Register : Register 702 (MAC Address111 High Register) - MAC_Address111_High
 * 
 * The MAC Address111 High register holds the upper 16 bits of the 112th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address111 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address111 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address111 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 112th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address111 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address111 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address111 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address111 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address111 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address111 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address111[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address111[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 112th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR111_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR111_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address111 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR111_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR111_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR111_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_OFST        0xaf8
/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR111_HIGH_OFST))

/*
 * Register : Register 703 (MAC Address111 Low Register) - MAC_Address111_Low
 * 
 * The MAC Address111 Low register holds the lower 32 bits of the 112th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address111 [31:0]
 * 
 */
/*
 * Field : MAC Address111 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 112th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR111_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR111_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address111 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR111_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR111_LOW_s  ALT_EMAC_GMAC_MAC_ADDR111_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_OFST        0xafc
/* The address of the ALT_EMAC_GMAC_MAC_ADDR111_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR111_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR111_LOW_OFST))

/*
 * Register : Register 704 (MAC Address112 High Register) - MAC_Address112_High
 * 
 * The MAC Address112 High register holds the upper 16 bits of the 113th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address112 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address112 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address112 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 113th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address112 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address112 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address112 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address112 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address112 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address112 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address112[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address112[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 113th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR112_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR112_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address112 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR112_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR112_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR112_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_OFST        0xb00
/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR112_HIGH_OFST))

/*
 * Register : Register 705 (MAC Address112 Low Register) - MAC_Address112_Low
 * 
 * The MAC Address112 Low register holds the lower 32 bits of the 113th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address112 [31:0]
 * 
 */
/*
 * Field : MAC Address112 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 113th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR112_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR112_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address112 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR112_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR112_LOW_s  ALT_EMAC_GMAC_MAC_ADDR112_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_OFST        0xb04
/* The address of the ALT_EMAC_GMAC_MAC_ADDR112_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR112_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR112_LOW_OFST))

/*
 * Register : Register 706 (MAC Address113 High Register) - MAC_Address113_High
 * 
 * The MAC Address113 High register holds the upper 16 bits of the 114th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address113 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address113 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address113 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 114th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address113 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address113 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address113 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address113 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address113 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address113 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address113[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address113[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 114th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR113_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR113_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address113 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR113_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR113_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR113_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_OFST        0xb08
/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR113_HIGH_OFST))

/*
 * Register : Register 707 (MAC Address113 Low Register) - MAC_Address113_Low
 * 
 * The MAC Address113 Low register holds the lower 32 bits of the 114th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address113 [31:0]
 * 
 */
/*
 * Field : MAC Address113 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 114th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR113_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR113_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address113 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR113_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR113_LOW_s  ALT_EMAC_GMAC_MAC_ADDR113_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_OFST        0xb0c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR113_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR113_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR113_LOW_OFST))

/*
 * Register : Register 708 (MAC Address114 High Register) - MAC_Address114_High
 * 
 * The MAC Address114 High register holds the upper 16 bits of the 115th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address114 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address114 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address114 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 115th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address114 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address114 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address114 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address114 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address114 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address114 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address114[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address114[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 115th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR114_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR114_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address114 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR114_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR114_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR114_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_OFST        0xb10
/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR114_HIGH_OFST))

/*
 * Register : Register 709 (MAC Address114 Low Register) - MAC_Address114_Low
 * 
 * The MAC Address114 Low register holds the lower 32 bits of the 115th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address114 [31:0]
 * 
 */
/*
 * Field : MAC Address114 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 115th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR114_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR114_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address114 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR114_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR114_LOW_s  ALT_EMAC_GMAC_MAC_ADDR114_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_OFST        0xb14
/* The address of the ALT_EMAC_GMAC_MAC_ADDR114_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR114_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR114_LOW_OFST))

/*
 * Register : Register 710 (MAC Address115 High Register) - MAC_Address115_High
 * 
 * The MAC Address115 High register holds the upper 16 bits of the 116th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address115 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address115 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address115 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 116th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address115 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address115 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address115 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address115 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address115 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address115 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address115[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address115[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 116th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR115_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR115_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address115 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR115_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR115_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR115_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_OFST        0xb18
/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR115_HIGH_OFST))

/*
 * Register : Register 711 (MAC Address115 Low Register) - MAC_Address115_Low
 * 
 * The MAC Address115 Low register holds the lower 32 bits of the 116th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address115 [31:0]
 * 
 */
/*
 * Field : MAC Address115 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 116th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR115_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR115_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address115 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR115_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR115_LOW_s  ALT_EMAC_GMAC_MAC_ADDR115_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_OFST        0xb1c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR115_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR115_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR115_LOW_OFST))

/*
 * Register : Register 712 (MAC Address116 High Register) - MAC_Address116_High
 * 
 * The MAC Address116 High register holds the upper 16 bits of the 117th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address116 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address116 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address116 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 117th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address116 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address116 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address116 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address116 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address116 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address116 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address116[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address116[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 117th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR116_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR116_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address116 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR116_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR116_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR116_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_OFST        0xb20
/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR116_HIGH_OFST))

/*
 * Register : Register 713 (MAC Address116 Low Register) - MAC_Address116_Low
 * 
 * The MAC Address116 Low register holds the lower 32 bits of the 117th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address116 [31:0]
 * 
 */
/*
 * Field : MAC Address116 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 117th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR116_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR116_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address116 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR116_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR116_LOW_s  ALT_EMAC_GMAC_MAC_ADDR116_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_OFST        0xb24
/* The address of the ALT_EMAC_GMAC_MAC_ADDR116_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR116_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR116_LOW_OFST))

/*
 * Register : Register 714 (MAC Address117 High Register) - MAC_Address117_High
 * 
 * The MAC Address117 High register holds the upper 16 bits of the 118th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address117 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address117 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address117 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 118th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address117 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address117 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address117 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address117 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address117 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address117 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address117[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address117[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 118th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR117_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR117_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address117 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR117_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR117_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR117_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_OFST        0xb28
/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR117_HIGH_OFST))

/*
 * Register : Register 715 (MAC Address117 Low Register) - MAC_Address117_Low
 * 
 * The MAC Address117 Low register holds the lower 32 bits of the 118th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address117 [31:0]
 * 
 */
/*
 * Field : MAC Address117 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 118th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR117_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR117_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address117 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR117_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR117_LOW_s  ALT_EMAC_GMAC_MAC_ADDR117_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_OFST        0xb2c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR117_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR117_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR117_LOW_OFST))

/*
 * Register : Register 716 (MAC Address118 High Register) - MAC_Address118_High
 * 
 * The MAC Address118 High register holds the upper 16 bits of the 119th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address118 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address118 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address118 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 119th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address118 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address118 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address118 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address118 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address118 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address118 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address118[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address118[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 119th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR118_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR118_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address118 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR118_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR118_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR118_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_OFST        0xb30
/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR118_HIGH_OFST))

/*
 * Register : Register 717 (MAC Address118 Low Register) - MAC_Address118_Low
 * 
 * The MAC Address118 Low register holds the lower 32 bits of the 119th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address118 [31:0]
 * 
 */
/*
 * Field : MAC Address118 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 119th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR118_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR118_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address118 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR118_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR118_LOW_s  ALT_EMAC_GMAC_MAC_ADDR118_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_OFST        0xb34
/* The address of the ALT_EMAC_GMAC_MAC_ADDR118_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR118_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR118_LOW_OFST))

/*
 * Register : Register 718 (MAC Address119 High Register) - MAC_Address119_High
 * 
 * The MAC Address119 High register holds the upper 16 bits of the 120th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address119 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address119 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address119 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 120th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address119 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address119 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address119 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address119 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address119 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address119 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address119[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address119[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 120th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR119_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR119_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address119 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR119_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR119_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR119_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_OFST        0xb38
/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR119_HIGH_OFST))

/*
 * Register : Register 719 (MAC Address119 Low Register) - MAC_Address119_Low
 * 
 * The MAC Address119 Low register holds the lower 32 bits of the 120th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address119 [31:0]
 * 
 */
/*
 * Field : MAC Address119 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 120th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR119_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR119_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address119 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR119_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR119_LOW_s  ALT_EMAC_GMAC_MAC_ADDR119_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_OFST        0xb3c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR119_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR119_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR119_LOW_OFST))

/*
 * Register : Register 720 (MAC Address120 High Register) - MAC_Address120_High
 * 
 * The MAC Address120 High register holds the upper 16 bits of the 121th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address120 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address120 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address120 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 121th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address120 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address120 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address120 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address120 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address120 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address120 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address120[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address120[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 121th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR120_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR120_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address120 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR120_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR120_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR120_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_OFST        0xb40
/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR120_HIGH_OFST))

/*
 * Register : Register 721 (MAC Address120 Low Register) - MAC_Address120_Low
 * 
 * The MAC Address120 Low register holds the lower 32 bits of the 121th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address120 [31:0]
 * 
 */
/*
 * Field : MAC Address120 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 121th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR120_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR120_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address120 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR120_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR120_LOW_s  ALT_EMAC_GMAC_MAC_ADDR120_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_OFST        0xb44
/* The address of the ALT_EMAC_GMAC_MAC_ADDR120_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR120_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR120_LOW_OFST))

/*
 * Register : Register 722 (MAC Address121 High Register) - MAC_Address121_High
 * 
 * The MAC Address121 High register holds the upper 16 bits of the 122th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address121 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address121 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address121 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 122th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address121 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address121 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address121 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address121 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address121 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address121 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address121[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address121[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 122th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR121_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR121_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address121 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR121_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR121_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR121_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_OFST        0xb48
/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR121_HIGH_OFST))

/*
 * Register : Register 723 (MAC Address121 Low Register) - MAC_Address121_Low
 * 
 * The MAC Address121 Low register holds the lower 32 bits of the 122th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address121 [31:0]
 * 
 */
/*
 * Field : MAC Address121 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 122th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR121_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR121_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address121 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR121_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR121_LOW_s  ALT_EMAC_GMAC_MAC_ADDR121_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_OFST        0xb4c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR121_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR121_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR121_LOW_OFST))

/*
 * Register : Register 724 (MAC Address122 High Register) - MAC_Address122_High
 * 
 * The MAC Address122 High register holds the upper 16 bits of the 123th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address122 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address122 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address122 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 123th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address122 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address122 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address122 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address122 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address122 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address122 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address122[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address122[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 123th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR122_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR122_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address122 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR122_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR122_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR122_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_OFST        0xb50
/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR122_HIGH_OFST))

/*
 * Register : Register 725 (MAC Address122 Low Register) - MAC_Address122_Low
 * 
 * The MAC Address122 Low register holds the lower 32 bits of the 123th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address122 [31:0]
 * 
 */
/*
 * Field : MAC Address122 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 123th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR122_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR122_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address122 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR122_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR122_LOW_s  ALT_EMAC_GMAC_MAC_ADDR122_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_OFST        0xb54
/* The address of the ALT_EMAC_GMAC_MAC_ADDR122_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR122_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR122_LOW_OFST))

/*
 * Register : Register 726 (MAC Address123 High Register) - MAC_Address123_High
 * 
 * The MAC Address123 High register holds the upper 16 bits of the 124th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address123 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address123 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address123 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 124th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address123 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address123 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address123 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address123 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address123 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address123 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address123[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address123[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 124th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR123_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR123_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address123 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR123_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR123_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR123_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_OFST        0xb58
/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR123_HIGH_OFST))

/*
 * Register : Register 727 (MAC Address123 Low Register) - MAC_Address123_Low
 * 
 * The MAC Address123 Low register holds the lower 32 bits of the 124th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address123 [31:0]
 * 
 */
/*
 * Field : MAC Address123 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 124th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR123_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR123_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address123 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR123_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR123_LOW_s  ALT_EMAC_GMAC_MAC_ADDR123_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_OFST        0xb5c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR123_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR123_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR123_LOW_OFST))

/*
 * Register : Register 728 (MAC Address124 High Register) - MAC_Address124_High
 * 
 * The MAC Address124 High register holds the upper 16 bits of the 125th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address124 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address124 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address124 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 125th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address124 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address124 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address124 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address124 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address124 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address124 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address124[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address124[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 125th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR124_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR124_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address124 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR124_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR124_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR124_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_OFST        0xb60
/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR124_HIGH_OFST))

/*
 * Register : Register 729 (MAC Address124 Low Register) - MAC_Address124_Low
 * 
 * The MAC Address124 Low register holds the lower 32 bits of the 125th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address124 [31:0]
 * 
 */
/*
 * Field : MAC Address124 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 125th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR124_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR124_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address124 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR124_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR124_LOW_s  ALT_EMAC_GMAC_MAC_ADDR124_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_OFST        0xb64
/* The address of the ALT_EMAC_GMAC_MAC_ADDR124_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR124_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR124_LOW_OFST))

/*
 * Register : Register 730 (MAC Address125 High Register) - MAC_Address125_High
 * 
 * The MAC Address125 High register holds the upper 16 bits of the 126th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address125 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address125 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address125 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 126th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address125 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address125 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address125 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address125 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address125 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address125 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address125[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address125[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 126th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR125_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR125_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address125 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR125_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR125_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR125_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_OFST        0xb68
/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR125_HIGH_OFST))

/*
 * Register : Register 731 (MAC Address125 Low Register) - MAC_Address125_Low
 * 
 * The MAC Address125 Low register holds the lower 32 bits of the 126th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address125 [31:0]
 * 
 */
/*
 * Field : MAC Address125 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 126th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR125_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR125_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address125 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR125_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR125_LOW_s  ALT_EMAC_GMAC_MAC_ADDR125_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_OFST        0xb6c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR125_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR125_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR125_LOW_OFST))

/*
 * Register : Register 732 (MAC Address126 High Register) - MAC_Address126_High
 * 
 * The MAC Address126 High register holds the upper 16 bits of the 127th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address126 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address126 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address126 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 127th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address126 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address126 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address126 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address126 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address126 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address126 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address126[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address126[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 127th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR126_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR126_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address126 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR126_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR126_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR126_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_OFST        0xb70
/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR126_HIGH_OFST))

/*
 * Register : Register 733 (MAC Address126 Low Register) - MAC_Address126_Low
 * 
 * The MAC Address126 Low register holds the lower 32 bits of the 127th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address126 [31:0]
 * 
 */
/*
 * Field : MAC Address126 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 127th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR126_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR126_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address126 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR126_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR126_LOW_s  ALT_EMAC_GMAC_MAC_ADDR126_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_OFST        0xb74
/* The address of the ALT_EMAC_GMAC_MAC_ADDR126_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR126_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR126_LOW_OFST))

/*
 * Register : Register 734 (MAC Address127 High Register) - MAC_Address127_High
 * 
 * The MAC Address127 High register holds the upper 16 bits of the 128th 6-byte MAC
 * address of the station. Because the MAC address registers are configured to be
 * double-synchronized to the (G)MII clock domains, the synchronization is
 * triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in big-
 * endian mode) of the MAC Address127 Low Register are written. For proper
 * synchronization updates, the consecutive writes to this Address Low Register
 * should be performed after at least four clock cycles in the destination clock
 * domain.
 * 
 * Note that all MAC Address High registers (except MAC Address0 High) have the
 * same format.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset  | Description           
 * :--------|:-------|:-------|:-----------------------
 *  [15:0]  | RW     | 0xffff | MAC Address127 [47:32]
 *  [23:16] | ???    | 0x0    | *UNDEFINED*           
 *  [24]    | RW     | 0x0    | Mask Byte Control     
 *  [25]    | RW     | 0x0    | Mask Byte Control     
 *  [26]    | RW     | 0x0    | Mask Byte Control     
 *  [27]    | RW     | 0x0    | Mask Byte Control     
 *  [28]    | RW     | 0x0    | Mask Byte Control     
 *  [29]    | RW     | 0x0    | Mask Byte Control     
 *  [30]    | RW     | 0x0    | Source Address        
 *  [31]    | RW     | 0x0    | Address Enable        
 * 
 */
/*
 * Field : MAC Address127 [47:32] - addrhi
 * 
 * This field contains the upper 16 bits (47:32) of the 128th 6-byte MAC address.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_MSB        15
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_WIDTH      16
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_RESET      0xffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDRHI_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : Mask Byte Control - mbc_0
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address127 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_MSB        24
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_0_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Mask Byte Control - mbc_1
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address127 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_MSB        25
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_1_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Mask Byte Control - mbc_2
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address127 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_MSB        26
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_2_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : Mask Byte Control - mbc_3
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address127 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_MSB        27
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_3_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Mask Byte Control - mbc_4
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address127 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_MSB        28
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_4_SET(value) (((value) << 28) & 0x10000000)

/*
 * Field : Mask Byte Control - mbc_5
 * 
 * This array of bits are mask control bits for comparison of each of the MAC
 * Address bytes. When masked, the MAC does not compare the corresponding byte of
 * received DA or SA with the contents of MAC Address127 high and low registers.
 * Each bit controls the masking of the bytes. You can filter a group of addresses
 * (known as group address filtering) by masking one or more bytes of the address.
 * 
 * The array index corresponds to the byte (e.g. index 0 is for bits 7:0).
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                           | Value | Description                        
 * :-----------------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_UNMSKED | 0x0   | Byte is unmasked (i.e. is compared)
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_MSKED   | 0x1   | Byte is masked (i.e. not compared) 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5
 * 
 * Byte is unmasked (i.e. is compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_UNMSKED  0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5
 * 
 * Byte is masked (i.e. not compared)
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_E_MSKED    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_MSB        29
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5 register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_MBC_5_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : Source Address - sa
 * 
 * When this bit is enabled, the MAC Address127[47:0] is used to compare with the
 * SA fields of the received frame. When this bit is disabled, the MAC
 * Address127[47:0] is used to compare with the DA fields of the received frame.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                 
 * :-----------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_DISD | 0x0   | MAC address compare disabled
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_END  | 0x1   | MAC address compare enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA
 * 
 * MAC address compare disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA
 * 
 * MAC address compare enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_MSB        30
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_SA_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Address Enable - ae
 * 
 * When this bit is enabled, the address filter block uses the 128th MAC address
 * for perfect filtering. When this bit is disabled, the address filter block
 * ignores the address for filtering.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                          
 * :-----------------------------------------|:------|:--------------------------------------
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_DISD | 0x0   | Second MAC address filtering disabled
 *  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_END  | 0x1   | Second MAC address filtering enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE
 * 
 * Second MAC address filtering disabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE
 * 
 * Second MAC address filtering enabled
 */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_WIDTH      1
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_RESET      0x0
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_AE_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR127_HIGH.
 */
struct ALT_EMAC_GMAC_MAC_ADDR127_HIGH_s
{
    uint32_t  addrhi : 16;  /* MAC Address127 [47:32] */
    uint32_t         :  8;  /* *UNDEFINED* */
    uint32_t  mbc_0  :  1;  /* Mask Byte Control */
    uint32_t  mbc_1  :  1;  /* Mask Byte Control */
    uint32_t  mbc_2  :  1;  /* Mask Byte Control */
    uint32_t  mbc_3  :  1;  /* Mask Byte Control */
    uint32_t  mbc_4  :  1;  /* Mask Byte Control */
    uint32_t  mbc_5  :  1;  /* Mask Byte Control */
    uint32_t  sa     :  1;  /* Source Address */
    uint32_t  ae     :  1;  /* Address Enable */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR127_HIGH. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR127_HIGH_s  ALT_EMAC_GMAC_MAC_ADDR127_HIGH_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_OFST        0xb78
/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_HIGH register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_HIGH_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR127_HIGH_OFST))

/*
 * Register : Register 735 (MAC Address127 Low Register) - MAC_Address127_Low
 * 
 * The MAC Address127 Low register holds the lower 32 bits of the 128th 6-byte MAC
 * address of the station.
 * 
 * Note that all MAC Address Low registers (except MAC Address0 Low) have the same
 * format.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset      | Description          
 * :-------|:-------|:-----------|:----------------------
 *  [31:0] | RW     | 0xffffffff | MAC Address127 [31:0]
 * 
 */
/*
 * Field : MAC Address127 [31:0] - addrlo
 * 
 * This field contains the lower 32 bits of the 128th 6-byte MAC address. The
 * content of this field is undefined until loaded by software after the
 * initialization process.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_MSB        31
/* The width in bits of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_WIDTH      32
/* The mask used to set the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value. */
#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field. */
#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_RESET      0xffffffff
/* Extracts the ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO field value from a register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO register field value suitable for setting the register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDRLO_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_GMAC_MAC_ADDR127_LOW.
 */
struct ALT_EMAC_GMAC_MAC_ADDR127_LOW_s
{
    uint32_t  addrlo : 32;  /* MAC Address127 [31:0] */
};

/* The typedef declaration for register ALT_EMAC_GMAC_MAC_ADDR127_LOW. */
typedef volatile struct ALT_EMAC_GMAC_MAC_ADDR127_LOW_s  ALT_EMAC_GMAC_MAC_ADDR127_LOW_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register from the beginning of the component. */
#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_OFST        0xb7c
/* The address of the ALT_EMAC_GMAC_MAC_ADDR127_LOW register. */
#define ALT_EMAC_GMAC_MAC_ADDR127_LOW_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_ADDR127_LOW_OFST))

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register group ALT_EMAC_GMAC.
 */
struct ALT_EMAC_GMAC_s
{
    volatile ALT_EMAC_GMAC_MAC_CFG_t                    MAC_Configuration;                /* ALT_EMAC_GMAC_MAC_CFG */
    volatile ALT_EMAC_GMAC_MAC_FRM_FLT_t                MAC_Frame_Filter;                 /* ALT_EMAC_GMAC_MAC_FRM_FLT */
    volatile uint32_t                                   _pad_0x8_0xf[2];                  /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_GMII_ADDR_t                  GMII_Address;                     /* ALT_EMAC_GMAC_GMII_ADDR */
    volatile ALT_EMAC_GMAC_GMII_DATA_t                  GMII_Data;                        /* ALT_EMAC_GMAC_GMII_DATA */
    volatile ALT_EMAC_GMAC_FLOW_CTL_t                   Flow_Control;                     /* ALT_EMAC_GMAC_FLOW_CTL */
    volatile ALT_EMAC_GMAC_VLAN_TAG_t                   VLAN_Tag;                         /* ALT_EMAC_GMAC_VLAN_TAG */
    volatile ALT_EMAC_GMAC_VER_t                        Version;                          /* ALT_EMAC_GMAC_VER */
    volatile ALT_EMAC_GMAC_DBG_t                        Debug;                            /* ALT_EMAC_GMAC_DBG */
    volatile uint32_t                                   _pad_0x28_0x2f[2];                /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_LPI_CTL_STAT_t               LPI_Control_Status;               /* ALT_EMAC_GMAC_LPI_CTL_STAT */
    volatile ALT_EMAC_GMAC_LPI_TMRS_CTL_t               LPI_Timers_Control;               /* ALT_EMAC_GMAC_LPI_TMRS_CTL */
    volatile ALT_EMAC_GMAC_INT_STAT_t                   Interrupt_Status;                 /* ALT_EMAC_GMAC_INT_STAT */
    volatile ALT_EMAC_GMAC_INT_MSK_t                    Interrupt_Mask;                   /* ALT_EMAC_GMAC_INT_MSK */
    volatile ALT_EMAC_GMAC_MAC_ADDR0_HIGH_t             MAC_Address0_High;                /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR0_LOW_t              MAC_Address0_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR0_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR1_HIGH_t             MAC_Address1_High;                /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR1_LOW_t              MAC_Address1_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR1_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR2_HIGH_t             MAC_Address2_High;                /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR2_LOW_t              MAC_Address2_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR2_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR3_HIGH_t             MAC_Address3_High;                /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR3_LOW_t              MAC_Address3_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR3_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR4_HIGH_t             MAC_Address4_High;                /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR4_LOW_t              MAC_Address4_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR4_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR5_HIGH_t             MAC_Address5_High;                /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR5_LOW_t              MAC_Address5_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR5_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR6_HIGH_t             MAC_Address6_High;                /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR6_LOW_t              MAC_Address6_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR6_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR7_HIGH_t             MAC_Address7_High;                /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR7_LOW_t              MAC_Address7_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR7_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR8_HIGH_t             MAC_Address8_High;                /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR8_LOW_t              MAC_Address8_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR8_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR9_HIGH_t             MAC_Address9_High;                /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR9_LOW_t              MAC_Address9_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR9_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR10_HIGH_t            MAC_Address10_High;               /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR10_LOW_t             MAC_Address10_Low;                /* ALT_EMAC_GMAC_MAC_ADDR10_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR11_HIGH_t            MAC_Address11_High;               /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR11_LOW_t             MAC_Address11_Low;                /* ALT_EMAC_GMAC_MAC_ADDR11_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR12_HIGH_t            MAC_Address12_High;               /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR12_LOW_t             MAC_Address12_Low;                /* ALT_EMAC_GMAC_MAC_ADDR12_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR13_HIGH_t            MAC_Address13_High;               /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR13_LOW_t             MAC_Address13_Low;                /* ALT_EMAC_GMAC_MAC_ADDR13_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR14_HIGH_t            MAC_Address14_High;               /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR14_LOW_t             MAC_Address14_Low;                /* ALT_EMAC_GMAC_MAC_ADDR14_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR15_HIGH_t            MAC_Address15_High;               /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR15_LOW_t             MAC_Address15_Low;                /* ALT_EMAC_GMAC_MAC_ADDR15_LOW */
    volatile uint32_t                                   _pad_0xc0_0xd7[6];                /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_MII_CTL_STAT_t               SGMII_RGMII_SMII_Control_Status;  /* ALT_EMAC_GMAC_MII_CTL_STAT */
    volatile uint32_t                                   _pad_0xdc_0xff[9];                /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_MMC_CTL_t                    MMC_Control;                      /* ALT_EMAC_GMAC_MMC_CTL */
    volatile ALT_EMAC_GMAC_MMC_RX_INT_t                 MMC_Receive_Interrupt;            /* ALT_EMAC_GMAC_MMC_RX_INT */
    volatile ALT_EMAC_GMAC_MMC_TX_INT_t                 MMC_Transmit_Interrupt;           /* ALT_EMAC_GMAC_MMC_TX_INT */
    volatile ALT_EMAC_GMAC_MMC_RX_INT_MSK_t             MMC_Receive_Interrupt_Mask;       /* ALT_EMAC_GMAC_MMC_RX_INT_MSK */
    volatile ALT_EMAC_GMAC_MMC_TX_INT_MSK_t             MMC_Transmit_Interrupt_Mask;      /* ALT_EMAC_GMAC_MMC_TX_INT_MSK */
    volatile ALT_EMAC_GMAC_TXOCTETCOUNT_GB_t            txoctetcount_gb;                  /* ALT_EMAC_GMAC_TXOCTETCOUNT_GB */
    volatile ALT_EMAC_GMAC_TXFRMCOUNT_GB_t              txframecount_gb;                  /* ALT_EMAC_GMAC_TXFRMCOUNT_GB */
    volatile ALT_EMAC_GMAC_TXBCASTFRMS_G_t              txbroadcastframes_g;              /* ALT_EMAC_GMAC_TXBCASTFRMS_G */
    volatile ALT_EMAC_GMAC_TXMCASTFRMS_G_t              txmulticastframes_g;              /* ALT_EMAC_GMAC_TXMCASTFRMS_G */
    volatile ALT_EMAC_GMAC_TX64OCTETS_GB_t              tx64octets_gb;                    /* ALT_EMAC_GMAC_TX64OCTETS_GB */
    volatile ALT_EMAC_GMAC_TX65TO127OCTETS_GB_t         tx65to127octets_gb;               /* ALT_EMAC_GMAC_TX65TO127OCTETS_GB */
    volatile ALT_EMAC_GMAC_TX128TO255OCTETS_GB_t        tx128to255octets_gb;              /* ALT_EMAC_GMAC_TX128TO255OCTETS_GB */
    volatile ALT_EMAC_GMAC_TX256TO511OCTETS_GB_t        tx256to511octets_gb;              /* ALT_EMAC_GMAC_TX256TO511OCTETS_GB */
    volatile ALT_EMAC_GMAC_TX512TO1023OCTETS_GB_t       tx512to1023octets_gb;             /* ALT_EMAC_GMAC_TX512TO1023OCTETS_GB */
    volatile ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB_t       tx1024tomaxoctets_gb;             /* ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB */
    volatile ALT_EMAC_GMAC_TXUNICASTFRMS_GB_t           txunicastframes_gb;               /* ALT_EMAC_GMAC_TXUNICASTFRMS_GB */
    volatile ALT_EMAC_GMAC_TXMCASTFRMS_GB_t             txmulticastframes_gb;             /* ALT_EMAC_GMAC_TXMCASTFRMS_GB */
    volatile ALT_EMAC_GMAC_TXBCASTFRMS_GB_t             txbroadcastframes_gb;             /* ALT_EMAC_GMAC_TXBCASTFRMS_GB */
    volatile ALT_EMAC_GMAC_TXUNDERFLOWERROR_t           txunderflowerror;                 /* ALT_EMAC_GMAC_TXUNDERFLOWERROR */
    volatile ALT_EMAC_GMAC_TXSINGLECOL_G_t              txsinglecol_g;                    /* ALT_EMAC_GMAC_TXSINGLECOL_G */
    volatile ALT_EMAC_GMAC_TXMULTICOL_G_t               txmulticol_g;                     /* ALT_EMAC_GMAC_TXMULTICOL_G */
    volatile ALT_EMAC_GMAC_TXDEFERRED_t                 txdeferred;                       /* ALT_EMAC_GMAC_TXDEFERRED */
    volatile ALT_EMAC_GMAC_TXLATECOL_t                  txlatecol;                        /* ALT_EMAC_GMAC_TXLATECOL */
    volatile ALT_EMAC_GMAC_TXEXESSCOL_t                 txexesscol;                       /* ALT_EMAC_GMAC_TXEXESSCOL */
    volatile ALT_EMAC_GMAC_TXCARRIERERR_t               txcarriererr;                     /* ALT_EMAC_GMAC_TXCARRIERERR */
    volatile ALT_EMAC_GMAC_TXOCTETCNT_t                 txoctetcnt;                       /* ALT_EMAC_GMAC_TXOCTETCNT */
    volatile ALT_EMAC_GMAC_TXFRMCOUNT_G_t               txframecount_g;                   /* ALT_EMAC_GMAC_TXFRMCOUNT_G */
    volatile ALT_EMAC_GMAC_TXEXCESSDEF_t                txexcessdef;                      /* ALT_EMAC_GMAC_TXEXCESSDEF */
    volatile ALT_EMAC_GMAC_TXPAUSEFRMS_t                txpauseframes;                    /* ALT_EMAC_GMAC_TXPAUSEFRMS */
    volatile ALT_EMAC_GMAC_TXVLANFRMS_G_t               txvlanframes_g;                   /* ALT_EMAC_GMAC_TXVLANFRMS_G */
    volatile ALT_EMAC_GMAC_TXOVERSIZE_G_t               txoversize_g;                     /* ALT_EMAC_GMAC_TXOVERSIZE_G */
    volatile uint32_t                                   _pad_0x17c_0x17f;                 /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_RXFRMCOUNT_GB_t              rxframecount_gb;                  /* ALT_EMAC_GMAC_RXFRMCOUNT_GB */
    volatile ALT_EMAC_GMAC_RXOCTETCOUNT_GB_t            rxoctetcount_gb;                  /* ALT_EMAC_GMAC_RXOCTETCOUNT_GB */
    volatile ALT_EMAC_GMAC_RXOCTETCOUNT_G_t             rxoctetcount_g;                   /* ALT_EMAC_GMAC_RXOCTETCOUNT_G */
    volatile ALT_EMAC_GMAC_RXBCASTFRMS_G_t              rxbroadcastframes_g;              /* ALT_EMAC_GMAC_RXBCASTFRMS_G */
    volatile ALT_EMAC_GMAC_RXMCASTFRMS_G_t              rxmulticastframes_g;              /* ALT_EMAC_GMAC_RXMCASTFRMS_G */
    volatile ALT_EMAC_GMAC_RXCRCERROR_t                 rxcrcerror;                       /* ALT_EMAC_GMAC_RXCRCERROR */
    volatile ALT_EMAC_GMAC_RXALIGNMENTERROR_t           rxalignmenterror;                 /* ALT_EMAC_GMAC_RXALIGNMENTERROR */
    volatile ALT_EMAC_GMAC_RXRUNTERROR_t                rxrunterror;                      /* ALT_EMAC_GMAC_RXRUNTERROR */
    volatile ALT_EMAC_GMAC_RXJABBERERROR_t              rxjabbererror;                    /* ALT_EMAC_GMAC_RXJABBERERROR */
    volatile ALT_EMAC_GMAC_RXUNDERSIZE_G_t              rxundersize_g;                    /* ALT_EMAC_GMAC_RXUNDERSIZE_G */
    volatile ALT_EMAC_GMAC_RXOVERSIZE_G_t               rxoversize_g;                     /* ALT_EMAC_GMAC_RXOVERSIZE_G */
    volatile ALT_EMAC_GMAC_RX64OCTETS_GB_t              rx64octets_gb;                    /* ALT_EMAC_GMAC_RX64OCTETS_GB */
    volatile ALT_EMAC_GMAC_RX65TO127OCTETS_GB_t         rx65to127octets_gb;               /* ALT_EMAC_GMAC_RX65TO127OCTETS_GB */
    volatile ALT_EMAC_GMAC_RX128TO255OCTETS_GB_t        rx128to255octets_gb;              /* ALT_EMAC_GMAC_RX128TO255OCTETS_GB */
    volatile ALT_EMAC_GMAC_RX256TO511OCTETS_GB_t        rx256to511octets_gb;              /* ALT_EMAC_GMAC_RX256TO511OCTETS_GB */
    volatile ALT_EMAC_GMAC_RX512TO1023OCTETS_GB_t       rx512to1023octets_gb;             /* ALT_EMAC_GMAC_RX512TO1023OCTETS_GB */
    volatile ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB_t       rx1024tomaxoctets_gb;             /* ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB */
    volatile ALT_EMAC_GMAC_RXUNICASTFRMS_G_t            rxunicastframes_g;                /* ALT_EMAC_GMAC_RXUNICASTFRMS_G */
    volatile ALT_EMAC_GMAC_RXLENERROR_t                 rxlengtherror;                    /* ALT_EMAC_GMAC_RXLENERROR */
    volatile ALT_EMAC_GMAC_RXOUTOFRANGETYPE_t           rxoutofrangetype;                 /* ALT_EMAC_GMAC_RXOUTOFRANGETYPE */
    volatile ALT_EMAC_GMAC_RXPAUSEFRMS_t                rxpauseframes;                    /* ALT_EMAC_GMAC_RXPAUSEFRMS */
    volatile ALT_EMAC_GMAC_RXFIFOOVF_t                  rxfifooverflow;                   /* ALT_EMAC_GMAC_RXFIFOOVF */
    volatile ALT_EMAC_GMAC_RXVLANFRMS_GB_t              rxvlanframes_gb;                  /* ALT_EMAC_GMAC_RXVLANFRMS_GB */
    volatile ALT_EMAC_GMAC_RXWDERROR_t                  rxwatchdogerror;                  /* ALT_EMAC_GMAC_RXWDERROR */
    volatile ALT_EMAC_GMAC_RXRCVERROR_t                 rxrcverror;                       /* ALT_EMAC_GMAC_RXRCVERROR */
    volatile ALT_EMAC_GMAC_RXCTLFRMS_G_t                rxctrlframes_g;                   /* ALT_EMAC_GMAC_RXCTLFRMS_G */
    volatile uint32_t                                   _pad_0x1e8_0x1ff[6];              /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_t         MMC_IPC_Receive_Interrupt_Mask;   /* ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK */
    volatile uint32_t                                   _pad_0x204_0x207;                 /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_MMC_IPC_RX_INT_t             MMC_IPC_Receive_Interrupt;        /* ALT_EMAC_GMAC_MMC_IPC_RX_INT */
    volatile uint32_t                                   _pad_0x20c_0x20f;                 /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_RXIPV4_GD_FRMS_t             rxipv4_gd_frms;                   /* ALT_EMAC_GMAC_RXIPV4_GD_FRMS */
    volatile ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS_t         rxipv4_hdrerr_frms;               /* ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS */
    volatile ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS_t          rxipv4_nopay_frms;                /* ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS */
    volatile ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS_t           rxipv4_frag_frms;                 /* ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS */
    volatile ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS_t          rxipv4_udsbl_frms;                /* ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS */
    volatile ALT_EMAC_GMAC_RXIPV6_GD_FRMS_t             rxipv6_gd_frms;                   /* ALT_EMAC_GMAC_RXIPV6_GD_FRMS */
    volatile ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS_t         rxipv6_hdrerr_frms;               /* ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS */
    volatile ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS_t          rxipv6_nopay_frms;                /* ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS */
    volatile ALT_EMAC_GMAC_RXUDP_GD_FRMS_t              rxudp_gd_frms;                    /* ALT_EMAC_GMAC_RXUDP_GD_FRMS */
    volatile ALT_EMAC_GMAC_RXUDP_ERR_FRMS_t             rxudp_err_frms;                   /* ALT_EMAC_GMAC_RXUDP_ERR_FRMS */
    volatile ALT_EMAC_GMAC_RXTCP_GD_FRMS_t              rxtcp_gd_frms;                    /* ALT_EMAC_GMAC_RXTCP_GD_FRMS */
    volatile ALT_EMAC_GMAC_RXTCP_ERR_FRMS_t             rxtcp_err_frms;                   /* ALT_EMAC_GMAC_RXTCP_ERR_FRMS */
    volatile ALT_EMAC_GMAC_RXICMP_GD_FRMS_t             rxicmp_gd_frms;                   /* ALT_EMAC_GMAC_RXICMP_GD_FRMS */
    volatile ALT_EMAC_GMAC_RXICMP_ERR_FRMS_t            rxicmp_err_frms;                  /* ALT_EMAC_GMAC_RXICMP_ERR_FRMS */
    volatile uint32_t                                   _pad_0x248_0x24f[2];              /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_RXIPV4_GD_OCTETS_t           rxipv4_gd_octets;                 /* ALT_EMAC_GMAC_RXIPV4_GD_OCTETS */
    volatile ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS_t       rxipv4_hdrerr_octets;             /* ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS */
    volatile ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS_t        rxipv4_nopay_octets;              /* ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS */
    volatile ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS_t         rxipv4_frag_octets;               /* ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS */
    volatile ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS_t        rxipv4_udsbl_octets;              /* ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS */
    volatile ALT_EMAC_GMAC_RXIPV6_GD_OCTETS_t           rxipv6_gd_octets;                 /* ALT_EMAC_GMAC_RXIPV6_GD_OCTETS */
    volatile ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS_t       rxipv6_hdrerr_octets;             /* ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS */
    volatile ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS_t        rxipv6_nopay_octets;              /* ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS */
    volatile ALT_EMAC_GMAC_RXUDP_GD_OCTETS_t            rxudp_gd_octets;                  /* ALT_EMAC_GMAC_RXUDP_GD_OCTETS */
    volatile ALT_EMAC_GMAC_RXUDP_ERR_OCTETS_t           rxudp_err_octets;                 /* ALT_EMAC_GMAC_RXUDP_ERR_OCTETS */
    volatile ALT_EMAC_GMAC_RXTCP_GD_OCTETS_t            rxtcp_gd_octets;                  /* ALT_EMAC_GMAC_RXTCP_GD_OCTETS */
    volatile ALT_EMAC_GMAC_RXTCPERROCTETS_t             rxtcperroctets;                   /* ALT_EMAC_GMAC_RXTCPERROCTETS */
    volatile ALT_EMAC_GMAC_RXICMP_GD_OCTETS_t           rxicmp_gd_octets;                 /* ALT_EMAC_GMAC_RXICMP_GD_OCTETS */
    volatile ALT_EMAC_GMAC_RXICMP_ERR_OCTETS_t          rxicmp_err_octets;                /* ALT_EMAC_GMAC_RXICMP_ERR_OCTETS */
    volatile uint32_t                                   _pad_0x288_0x3ff[94];             /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_L3_L4_CTL0_t                 L3_L4_Control0;                   /* ALT_EMAC_GMAC_L3_L4_CTL0 */
    volatile ALT_EMAC_GMAC_LYR4_ADDR0_t                 Layer4_Address0;                  /* ALT_EMAC_GMAC_LYR4_ADDR0 */
    volatile uint32_t                                   _pad_0x408_0x40f[2];              /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_LYR3_ADDR0_REG0_t            Layer3_Addr0_Reg0;                /* ALT_EMAC_GMAC_LYR3_ADDR0_REG0 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR1_REG0_t            Layer3_Addr1_Reg0;                /* ALT_EMAC_GMAC_LYR3_ADDR1_REG0 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR2_REG0_t            Layer3_Addr2_Reg0;                /* ALT_EMAC_GMAC_LYR3_ADDR2_REG0 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR3_REG0_t            Layer3_Addr3_Reg0;                /* ALT_EMAC_GMAC_LYR3_ADDR3_REG0 */
    volatile uint32_t                                   _pad_0x420_0x42f[4];              /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_L3_L4_CTL1_t                 L3_L4_Control1;                   /* ALT_EMAC_GMAC_L3_L4_CTL1 */
    volatile ALT_EMAC_GMAC_LYR4_ADDR1_t                 Layer4_Address1;                  /* ALT_EMAC_GMAC_LYR4_ADDR1 */
    volatile uint32_t                                   _pad_0x438_0x43f[2];              /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_LYR3_ADDR0_REG1_t            Layer3_Addr0_Reg1;                /* ALT_EMAC_GMAC_LYR3_ADDR0_REG1 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR1_REG1_t            Layer3_Addr1_Reg1;                /* ALT_EMAC_GMAC_LYR3_ADDR1_REG1 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR2_REG1_t            Layer3_Addr2_Reg1;                /* ALT_EMAC_GMAC_LYR3_ADDR2_REG1 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR3_REG1_t            Layer3_Addr3_Reg1;                /* ALT_EMAC_GMAC_LYR3_ADDR3_REG1 */
    volatile uint32_t                                   _pad_0x450_0x45f[4];              /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_L3_L4_CTL2_t                 L3_L4_Control2;                   /* ALT_EMAC_GMAC_L3_L4_CTL2 */
    volatile ALT_EMAC_GMAC_LYR4_ADDR2_t                 Layer4_Address2;                  /* ALT_EMAC_GMAC_LYR4_ADDR2 */
    volatile uint32_t                                   _pad_0x468_0x46f[2];              /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_LYR3_ADDR0_REG2_t            Layer3_Addr0_Reg2;                /* ALT_EMAC_GMAC_LYR3_ADDR0_REG2 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR1_REG2_t            Layer3_Addr1_Reg2;                /* ALT_EMAC_GMAC_LYR3_ADDR1_REG2 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR2_REG2_t            Layer3_Addr2_Reg2;                /* ALT_EMAC_GMAC_LYR3_ADDR2_REG2 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR3_REG2_t            Layer3_Addr3_Reg2;                /* ALT_EMAC_GMAC_LYR3_ADDR3_REG2 */
    volatile uint32_t                                   _pad_0x480_0x48f[4];              /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_L3_L4_CTL3_t                 L3_L4_Control3;                   /* ALT_EMAC_GMAC_L3_L4_CTL3 */
    volatile ALT_EMAC_GMAC_LYR4_ADDR3_t                 Layer4_Address3;                  /* ALT_EMAC_GMAC_LYR4_ADDR3 */
    volatile uint32_t                                   _pad_0x498_0x49f[2];              /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_LYR3_ADDR0_REG3_t            Layer3_Addr0_Reg3;                /* ALT_EMAC_GMAC_LYR3_ADDR0_REG3 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR1_REG3_t            Layer3_Addr1_Reg3;                /* ALT_EMAC_GMAC_LYR3_ADDR1_REG3 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR2_REG3_t            Layer3_Addr2_Reg3;                /* ALT_EMAC_GMAC_LYR3_ADDR2_REG3 */
    volatile ALT_EMAC_GMAC_LYR3_ADDR3_REG3_t            Layer3_Addr3_Reg3;                /* ALT_EMAC_GMAC_LYR3_ADDR3_REG3 */
    volatile uint32_t                                   _pad_0x4b0_0x4ff[20];             /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_HASH_TABLE_REG0_t            Hash_Table_Reg0;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG0 */
    volatile ALT_EMAC_GMAC_HASH_TABLE_REG1_t            Hash_Table_Reg1;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG1 */
    volatile ALT_EMAC_GMAC_HASH_TABLE_REG2_t            Hash_Table_Reg2;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG2 */
    volatile ALT_EMAC_GMAC_HASH_TABLE_REG3_t            Hash_Table_Reg3;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG3 */
    volatile ALT_EMAC_GMAC_HASH_TABLE_REG4_t            Hash_Table_Reg4;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG4 */
    volatile ALT_EMAC_GMAC_HASH_TABLE_REG5_t            Hash_Table_Reg5;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG5 */
    volatile ALT_EMAC_GMAC_HASH_TABLE_REG6_t            Hash_Table_Reg6;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG6 */
    volatile ALT_EMAC_GMAC_HASH_TABLE_REG7_t            Hash_Table_Reg7;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG7 */
    volatile uint32_t                                   _pad_0x520_0x583[25];             /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_VLAN_INCL_REG_t              VLAN_Incl_Reg;                    /* ALT_EMAC_GMAC_VLAN_INCL_REG */
    volatile ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG_t        VLAN_Hash_Table_Reg;              /* ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG */
    volatile uint32_t                                   _pad_0x58c_0x6ff[93];             /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_TS_CTL_t                     Timestamp_Control;                /* ALT_EMAC_GMAC_TS_CTL */
    volatile ALT_EMAC_GMAC_SUB_SEC_INCREMENT_t          Sub_Second_Increment;             /* ALT_EMAC_GMAC_SUB_SEC_INCREMENT */
    volatile ALT_EMAC_GMAC_SYS_TIME_SECS_t              System_Time_Seconds;              /* ALT_EMAC_GMAC_SYS_TIME_SECS */
    volatile ALT_EMAC_GMAC_SYS_TIME_NANOSECS_t          System_Time_Nanoseconds;          /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS */
    volatile ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE_t       System_Time_Seconds_Update;       /* ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE */
    volatile ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE_t   System_Time_Nanoseconds_Update;   /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE */
    volatile ALT_EMAC_GMAC_TS_ADDEND_t                  Timestamp_Addend;                 /* ALT_EMAC_GMAC_TS_ADDEND */
    volatile ALT_EMAC_GMAC_TGT_TIME_SECS_t              Target_Time_Seconds;              /* ALT_EMAC_GMAC_TGT_TIME_SECS */
    volatile ALT_EMAC_GMAC_TGT_TIME_NANOSECS_t          Target_Time_Nanoseconds;          /* ALT_EMAC_GMAC_TGT_TIME_NANOSECS */
    volatile ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS_t  System_Time_Higher_Word_Seconds;  /* ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS */
    volatile ALT_EMAC_GMAC_TS_STAT_t                    Timestamp_Status;                 /* ALT_EMAC_GMAC_TS_STAT */
    volatile ALT_EMAC_GMAC_PPS_CTL_t                    PPS_Control;                      /* ALT_EMAC_GMAC_PPS_CTL */
    volatile ALT_EMAC_GMAC_AUX_TS_NANOSECS_t            Auxiliary_Timestamp_Nanoseconds;  /* ALT_EMAC_GMAC_AUX_TS_NANOSECS */
    volatile ALT_EMAC_GMAC_AUX_TS_SECS_t                Auxiliary_Timestamp_Seconds;      /* ALT_EMAC_GMAC_AUX_TS_SECS */
    volatile uint32_t                                   _pad_0x738_0x75f[10];             /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_PPS0_INTERVAL_t              PPS0_Interval;                    /* ALT_EMAC_GMAC_PPS0_INTERVAL */
    volatile ALT_EMAC_GMAC_PPS0_WIDTH_t                 PPS0_Width;                       /* ALT_EMAC_GMAC_PPS0_WIDTH */
    volatile uint32_t                                   _pad_0x768_0x7ff[38];             /* *UNDEFINED* */
    volatile ALT_EMAC_GMAC_MAC_ADDR16_HIGH_t            MAC_Address16_High;               /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR16_LOW_t             MAC_Address16_Low;                /* ALT_EMAC_GMAC_MAC_ADDR16_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR17_HIGH_t            MAC_Address17_High;               /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR17_LOW_t             MAC_Address17_Low;                /* ALT_EMAC_GMAC_MAC_ADDR17_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR18_HIGH_t            MAC_Address18_High;               /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR18_LOW_t             MAC_Address18_Low;                /* ALT_EMAC_GMAC_MAC_ADDR18_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR19_HIGH_t            MAC_Address19_High;               /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR19_LOW_t             MAC_Address19_Low;                /* ALT_EMAC_GMAC_MAC_ADDR19_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR20_HIGH_t            MAC_Address20_High;               /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR20_LOW_t             MAC_Address20_Low;                /* ALT_EMAC_GMAC_MAC_ADDR20_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR21_HIGH_t            MAC_Address21_High;               /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR21_LOW_t             MAC_Address21_Low;                /* ALT_EMAC_GMAC_MAC_ADDR21_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR22_HIGH_t            MAC_Address22_High;               /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR22_LOW_t             MAC_Address22_Low;                /* ALT_EMAC_GMAC_MAC_ADDR22_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR23_HIGH_t            MAC_Address23_High;               /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR23_LOW_t             MAC_Address23_Low;                /* ALT_EMAC_GMAC_MAC_ADDR23_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR24_HIGH_t            MAC_Address24_High;               /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR24_LOW_t             MAC_Address24_Low;                /* ALT_EMAC_GMAC_MAC_ADDR24_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR25_HIGH_t            MAC_Address25_High;               /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR25_LOW_t             MAC_Address25_Low;                /* ALT_EMAC_GMAC_MAC_ADDR25_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR26_HIGH_t            MAC_Address26_High;               /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR26_LOW_t             MAC_Address26_Low;                /* ALT_EMAC_GMAC_MAC_ADDR26_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR27_HIGH_t            MAC_Address27_High;               /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR27_LOW_t             MAC_Address27_Low;                /* ALT_EMAC_GMAC_MAC_ADDR27_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR28_HIGH_t            MAC_Address28_High;               /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR28_LOW_t             MAC_Address28_Low;                /* ALT_EMAC_GMAC_MAC_ADDR28_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR29_HIGH_t            MAC_Address29_High;               /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR29_LOW_t             MAC_Address29_Low;                /* ALT_EMAC_GMAC_MAC_ADDR29_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR30_HIGH_t            MAC_Address30_High;               /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR30_LOW_t             MAC_Address30_Low;                /* ALT_EMAC_GMAC_MAC_ADDR30_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR31_HIGH_t            MAC_Address31_High;               /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR31_LOW_t             MAC_Address31_Low;                /* ALT_EMAC_GMAC_MAC_ADDR31_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR32_HIGH_t            MAC_Address32_High;               /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR32_LOW_t             MAC_Address32_Low;                /* ALT_EMAC_GMAC_MAC_ADDR32_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR33_HIGH_t            MAC_Address33_High;               /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR33_LOW_t             MAC_Address33_Low;                /* ALT_EMAC_GMAC_MAC_ADDR33_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR34_HIGH_t            MAC_Address34_High;               /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR34_LOW_t             MAC_Address34_Low;                /* ALT_EMAC_GMAC_MAC_ADDR34_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR35_HIGH_t            MAC_Address35_High;               /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR35_LOW_t             MAC_Address35_Low;                /* ALT_EMAC_GMAC_MAC_ADDR35_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR36_HIGH_t            MAC_Address36_High;               /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR36_LOW_t             MAC_Address36_Low;                /* ALT_EMAC_GMAC_MAC_ADDR36_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR37_HIGH_t            MAC_Address37_High;               /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR37_LOW_t             MAC_Address37_Low;                /* ALT_EMAC_GMAC_MAC_ADDR37_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR38_HIGH_t            MAC_Address38_High;               /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR38_LOW_t             MAC_Address38_Low;                /* ALT_EMAC_GMAC_MAC_ADDR38_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR39_HIGH_t            MAC_Address39_High;               /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR39_LOW_t             MAC_Address39_Low;                /* ALT_EMAC_GMAC_MAC_ADDR39_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR40_HIGH_t            MAC_Address40_High;               /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR40_LOW_t             MAC_Address40_Low;                /* ALT_EMAC_GMAC_MAC_ADDR40_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR41_HIGH_t            MAC_Address41_High;               /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR41_LOW_t             MAC_Address41_Low;                /* ALT_EMAC_GMAC_MAC_ADDR41_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR42_HIGH_t            MAC_Address42_High;               /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR42_LOW_t             MAC_Address42_Low;                /* ALT_EMAC_GMAC_MAC_ADDR42_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR43_HIGH_t            MAC_Address43_High;               /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR43_LOW_t             MAC_Address43_Low;                /* ALT_EMAC_GMAC_MAC_ADDR43_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR44_HIGH_t            MAC_Address44_High;               /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR44_LOW_t             MAC_Address44_Low;                /* ALT_EMAC_GMAC_MAC_ADDR44_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR45_HIGH_t            MAC_Address45_High;               /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR45_LOW_t             MAC_Address45_Low;                /* ALT_EMAC_GMAC_MAC_ADDR45_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR46_HIGH_t            MAC_Address46_High;               /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR46_LOW_t             MAC_Address46_Low;                /* ALT_EMAC_GMAC_MAC_ADDR46_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR47_HIGH_t            MAC_Address47_High;               /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR47_LOW_t             MAC_Address47_Low;                /* ALT_EMAC_GMAC_MAC_ADDR47_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR48_HIGH_t            MAC_Address48_High;               /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR48_LOW_t             MAC_Address48_Low;                /* ALT_EMAC_GMAC_MAC_ADDR48_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR49_HIGH_t            MAC_Address49_High;               /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR49_LOW_t             MAC_Address49_Low;                /* ALT_EMAC_GMAC_MAC_ADDR49_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR50_HIGH_t            MAC_Address50_High;               /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR50_LOW_t             MAC_Address50_Low;                /* ALT_EMAC_GMAC_MAC_ADDR50_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR51_HIGH_t            MAC_Address51_High;               /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR51_LOW_t             MAC_Address51_Low;                /* ALT_EMAC_GMAC_MAC_ADDR51_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR52_HIGH_t            MAC_Address52_High;               /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR52_LOW_t             MAC_Address52_Low;                /* ALT_EMAC_GMAC_MAC_ADDR52_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR53_HIGH_t            MAC_Address53_High;               /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR53_LOW_t             MAC_Address53_Low;                /* ALT_EMAC_GMAC_MAC_ADDR53_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR54_HIGH_t            MAC_Address54_High;               /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR54_LOW_t             MAC_Address54_Low;                /* ALT_EMAC_GMAC_MAC_ADDR54_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR55_HIGH_t            MAC_Address55_High;               /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR55_LOW_t             MAC_Address55_Low;                /* ALT_EMAC_GMAC_MAC_ADDR55_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR56_HIGH_t            MAC_Address56_High;               /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR56_LOW_t             MAC_Address56_Low;                /* ALT_EMAC_GMAC_MAC_ADDR56_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR57_HIGH_t            MAC_Address57_High;               /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR57_LOW_t             MAC_Address57_Low;                /* ALT_EMAC_GMAC_MAC_ADDR57_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR58_HIGH_t            MAC_Address58_High;               /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR58_LOW_t             MAC_Address58_Low;                /* ALT_EMAC_GMAC_MAC_ADDR58_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR59_HIGH_t            MAC_Address59_High;               /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR59_LOW_t             MAC_Address59_Low;                /* ALT_EMAC_GMAC_MAC_ADDR59_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR60_HIGH_t            MAC_Address60_High;               /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR60_LOW_t             MAC_Address60_Low;                /* ALT_EMAC_GMAC_MAC_ADDR60_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR61_HIGH_t            MAC_Address61_High;               /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR61_LOW_t             MAC_Address61_Low;                /* ALT_EMAC_GMAC_MAC_ADDR61_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR62_HIGH_t            MAC_Address62_High;               /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR62_LOW_t             MAC_Address62_Low;                /* ALT_EMAC_GMAC_MAC_ADDR62_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR63_HIGH_t            MAC_Address63_High;               /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR63_LOW_t             MAC_Address63_Low;                /* ALT_EMAC_GMAC_MAC_ADDR63_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR64_HIGH_t            MAC_Address64_High;               /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR64_LOW_t             MAC_Address64_Low;                /* ALT_EMAC_GMAC_MAC_ADDR64_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR65_HIGH_t            MAC_Address65_High;               /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR65_LOW_t             MAC_Address65_Low;                /* ALT_EMAC_GMAC_MAC_ADDR65_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR66_HIGH_t            MAC_Address66_High;               /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR66_LOW_t             MAC_Address66_Low;                /* ALT_EMAC_GMAC_MAC_ADDR66_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR67_HIGH_t            MAC_Address67_High;               /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR67_LOW_t             MAC_Address67_Low;                /* ALT_EMAC_GMAC_MAC_ADDR67_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR68_HIGH_t            MAC_Address68_High;               /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR68_LOW_t             MAC_Address68_Low;                /* ALT_EMAC_GMAC_MAC_ADDR68_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR69_HIGH_t            MAC_Address69_High;               /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR69_LOW_t             MAC_Address69_Low;                /* ALT_EMAC_GMAC_MAC_ADDR69_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR70_HIGH_t            MAC_Address70_High;               /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR70_LOW_t             MAC_Address70_Low;                /* ALT_EMAC_GMAC_MAC_ADDR70_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR71_HIGH_t            MAC_Address71_High;               /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR71_LOW_t             MAC_Address71_Low;                /* ALT_EMAC_GMAC_MAC_ADDR71_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR72_HIGH_t            MAC_Address72_High;               /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR72_LOW_t             MAC_Address72_Low;                /* ALT_EMAC_GMAC_MAC_ADDR72_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR73_HIGH_t            MAC_Address73_High;               /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR73_LOW_t             MAC_Address73_Low;                /* ALT_EMAC_GMAC_MAC_ADDR73_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR74_HIGH_t            MAC_Address74_High;               /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR74_LOW_t             MAC_Address74_Low;                /* ALT_EMAC_GMAC_MAC_ADDR74_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR75_HIGH_t            MAC_Address75_High;               /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR75_LOW_t             MAC_Address75_Low;                /* ALT_EMAC_GMAC_MAC_ADDR75_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR76_HIGH_t            MAC_Address76_High;               /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR76_LOW_t             MAC_Address76_Low;                /* ALT_EMAC_GMAC_MAC_ADDR76_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR77_HIGH_t            MAC_Address77_High;               /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR77_LOW_t             MAC_Address77_Low;                /* ALT_EMAC_GMAC_MAC_ADDR77_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR78_HIGH_t            MAC_Address78_High;               /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR78_LOW_t             MAC_Address78_Low;                /* ALT_EMAC_GMAC_MAC_ADDR78_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR79_HIGH_t            MAC_Address79_High;               /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR79_LOW_t             MAC_Address79_Low;                /* ALT_EMAC_GMAC_MAC_ADDR79_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR80_HIGH_t            MAC_Address80_High;               /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR80_LOW_t             MAC_Address80_Low;                /* ALT_EMAC_GMAC_MAC_ADDR80_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR81_HIGH_t            MAC_Address81_High;               /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR81_LOW_t             MAC_Address81_Low;                /* ALT_EMAC_GMAC_MAC_ADDR81_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR82_HIGH_t            MAC_Address82_High;               /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR82_LOW_t             MAC_Address82_Low;                /* ALT_EMAC_GMAC_MAC_ADDR82_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR83_HIGH_t            MAC_Address83_High;               /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR83_LOW_t             MAC_Address83_Low;                /* ALT_EMAC_GMAC_MAC_ADDR83_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR84_HIGH_t            MAC_Address84_High;               /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR84_LOW_t             MAC_Address84_Low;                /* ALT_EMAC_GMAC_MAC_ADDR84_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR85_HIGH_t            MAC_Address85_High;               /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR85_LOW_t             MAC_Address85_Low;                /* ALT_EMAC_GMAC_MAC_ADDR85_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR86_HIGH_t            MAC_Address86_High;               /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR86_LOW_t             MAC_Address86_Low;                /* ALT_EMAC_GMAC_MAC_ADDR86_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR87_HIGH_t            MAC_Address87_High;               /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR87_LOW_t             MAC_Address87_Low;                /* ALT_EMAC_GMAC_MAC_ADDR87_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR88_HIGH_t            MAC_Address88_High;               /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR88_LOW_t             MAC_Address88_Low;                /* ALT_EMAC_GMAC_MAC_ADDR88_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR89_HIGH_t            MAC_Address89_High;               /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR89_LOW_t             MAC_Address89_Low;                /* ALT_EMAC_GMAC_MAC_ADDR89_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR90_HIGH_t            MAC_Address90_High;               /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR90_LOW_t             MAC_Address90_Low;                /* ALT_EMAC_GMAC_MAC_ADDR90_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR91_HIGH_t            MAC_Address91_High;               /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR91_LOW_t             MAC_Address91_Low;                /* ALT_EMAC_GMAC_MAC_ADDR91_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR92_HIGH_t            MAC_Address92_High;               /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR92_LOW_t             MAC_Address92_Low;                /* ALT_EMAC_GMAC_MAC_ADDR92_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR93_HIGH_t            MAC_Address93_High;               /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR93_LOW_t             MAC_Address93_Low;                /* ALT_EMAC_GMAC_MAC_ADDR93_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR94_HIGH_t            MAC_Address94_High;               /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR94_LOW_t             MAC_Address94_Low;                /* ALT_EMAC_GMAC_MAC_ADDR94_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR95_HIGH_t            MAC_Address95_High;               /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR95_LOW_t             MAC_Address95_Low;                /* ALT_EMAC_GMAC_MAC_ADDR95_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR96_HIGH_t            MAC_Address96_High;               /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR96_LOW_t             MAC_Address96_Low;                /* ALT_EMAC_GMAC_MAC_ADDR96_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR97_HIGH_t            MAC_Address97_High;               /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR97_LOW_t             MAC_Address97_Low;                /* ALT_EMAC_GMAC_MAC_ADDR97_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR98_HIGH_t            MAC_Address98_High;               /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR98_LOW_t             MAC_Address98_Low;                /* ALT_EMAC_GMAC_MAC_ADDR98_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR99_HIGH_t            MAC_Address99_High;               /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR99_LOW_t             MAC_Address99_Low;                /* ALT_EMAC_GMAC_MAC_ADDR99_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR100_HIGH_t           MAC_Address100_High;              /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR100_LOW_t            MAC_Address100_Low;               /* ALT_EMAC_GMAC_MAC_ADDR100_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR101_HIGH_t           MAC_Address101_High;              /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR101_LOW_t            MAC_Address101_Low;               /* ALT_EMAC_GMAC_MAC_ADDR101_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR102_HIGH_t           MAC_Address102_High;              /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR102_LOW_t            MAC_Address102_Low;               /* ALT_EMAC_GMAC_MAC_ADDR102_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR103_HIGH_t           MAC_Address103_High;              /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR103_LOW_t            MAC_Address103_Low;               /* ALT_EMAC_GMAC_MAC_ADDR103_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR104_HIGH_t           MAC_Address104_High;              /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR104_LOW_t            MAC_Address104_Low;               /* ALT_EMAC_GMAC_MAC_ADDR104_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR105_HIGH_t           MAC_Address105_High;              /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR105_LOW_t            MAC_Address105_Low;               /* ALT_EMAC_GMAC_MAC_ADDR105_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR106_HIGH_t           MAC_Address106_High;              /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR106_LOW_t            MAC_Address106_Low;               /* ALT_EMAC_GMAC_MAC_ADDR106_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR107_HIGH_t           MAC_Address107_High;              /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR107_LOW_t            MAC_Address107_Low;               /* ALT_EMAC_GMAC_MAC_ADDR107_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR108_HIGH_t           MAC_Address108_High;              /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR108_LOW_t            MAC_Address108_Low;               /* ALT_EMAC_GMAC_MAC_ADDR108_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR109_HIGH_t           MAC_Address109_High;              /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR109_LOW_t            MAC_Address109_Low;               /* ALT_EMAC_GMAC_MAC_ADDR109_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR110_HIGH_t           MAC_Address110_High;              /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR110_LOW_t            MAC_Address110_Low;               /* ALT_EMAC_GMAC_MAC_ADDR110_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR111_HIGH_t           MAC_Address111_High;              /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR111_LOW_t            MAC_Address111_Low;               /* ALT_EMAC_GMAC_MAC_ADDR111_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR112_HIGH_t           MAC_Address112_High;              /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR112_LOW_t            MAC_Address112_Low;               /* ALT_EMAC_GMAC_MAC_ADDR112_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR113_HIGH_t           MAC_Address113_High;              /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR113_LOW_t            MAC_Address113_Low;               /* ALT_EMAC_GMAC_MAC_ADDR113_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR114_HIGH_t           MAC_Address114_High;              /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR114_LOW_t            MAC_Address114_Low;               /* ALT_EMAC_GMAC_MAC_ADDR114_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR115_HIGH_t           MAC_Address115_High;              /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR115_LOW_t            MAC_Address115_Low;               /* ALT_EMAC_GMAC_MAC_ADDR115_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR116_HIGH_t           MAC_Address116_High;              /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR116_LOW_t            MAC_Address116_Low;               /* ALT_EMAC_GMAC_MAC_ADDR116_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR117_HIGH_t           MAC_Address117_High;              /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR117_LOW_t            MAC_Address117_Low;               /* ALT_EMAC_GMAC_MAC_ADDR117_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR118_HIGH_t           MAC_Address118_High;              /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR118_LOW_t            MAC_Address118_Low;               /* ALT_EMAC_GMAC_MAC_ADDR118_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR119_HIGH_t           MAC_Address119_High;              /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR119_LOW_t            MAC_Address119_Low;               /* ALT_EMAC_GMAC_MAC_ADDR119_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR120_HIGH_t           MAC_Address120_High;              /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR120_LOW_t            MAC_Address120_Low;               /* ALT_EMAC_GMAC_MAC_ADDR120_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR121_HIGH_t           MAC_Address121_High;              /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR121_LOW_t            MAC_Address121_Low;               /* ALT_EMAC_GMAC_MAC_ADDR121_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR122_HIGH_t           MAC_Address122_High;              /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR122_LOW_t            MAC_Address122_Low;               /* ALT_EMAC_GMAC_MAC_ADDR122_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR123_HIGH_t           MAC_Address123_High;              /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR123_LOW_t            MAC_Address123_Low;               /* ALT_EMAC_GMAC_MAC_ADDR123_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR124_HIGH_t           MAC_Address124_High;              /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR124_LOW_t            MAC_Address124_Low;               /* ALT_EMAC_GMAC_MAC_ADDR124_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR125_HIGH_t           MAC_Address125_High;              /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR125_LOW_t            MAC_Address125_Low;               /* ALT_EMAC_GMAC_MAC_ADDR125_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR126_HIGH_t           MAC_Address126_High;              /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR126_LOW_t            MAC_Address126_Low;               /* ALT_EMAC_GMAC_MAC_ADDR126_LOW */
    volatile ALT_EMAC_GMAC_MAC_ADDR127_HIGH_t           MAC_Address127_High;              /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH */
    volatile ALT_EMAC_GMAC_MAC_ADDR127_LOW_t            MAC_Address127_Low;               /* ALT_EMAC_GMAC_MAC_ADDR127_LOW */
};

/* The typedef declaration for register group ALT_EMAC_GMAC. */
typedef volatile struct ALT_EMAC_GMAC_s  ALT_EMAC_GMAC_t;
/* The struct declaration for the raw register contents of register group ALT_EMAC_GMAC. */
struct ALT_EMAC_GMAC_raw_s
{
    volatile uint32_t  MAC_Configuration;                /* ALT_EMAC_GMAC_MAC_CFG */
    volatile uint32_t  MAC_Frame_Filter;                 /* ALT_EMAC_GMAC_MAC_FRM_FLT */
    volatile uint32_t  _pad_0x8_0xf[2];                  /* *UNDEFINED* */
    volatile uint32_t  GMII_Address;                     /* ALT_EMAC_GMAC_GMII_ADDR */
    volatile uint32_t  GMII_Data;                        /* ALT_EMAC_GMAC_GMII_DATA */
    volatile uint32_t  Flow_Control;                     /* ALT_EMAC_GMAC_FLOW_CTL */
    volatile uint32_t  VLAN_Tag;                         /* ALT_EMAC_GMAC_VLAN_TAG */
    volatile uint32_t  Version;                          /* ALT_EMAC_GMAC_VER */
    volatile uint32_t  Debug;                            /* ALT_EMAC_GMAC_DBG */
    volatile uint32_t  _pad_0x28_0x2f[2];                /* *UNDEFINED* */
    volatile uint32_t  LPI_Control_Status;               /* ALT_EMAC_GMAC_LPI_CTL_STAT */
    volatile uint32_t  LPI_Timers_Control;               /* ALT_EMAC_GMAC_LPI_TMRS_CTL */
    volatile uint32_t  Interrupt_Status;                 /* ALT_EMAC_GMAC_INT_STAT */
    volatile uint32_t  Interrupt_Mask;                   /* ALT_EMAC_GMAC_INT_MSK */
    volatile uint32_t  MAC_Address0_High;                /* ALT_EMAC_GMAC_MAC_ADDR0_HIGH */
    volatile uint32_t  MAC_Address0_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR0_LOW */
    volatile uint32_t  MAC_Address1_High;                /* ALT_EMAC_GMAC_MAC_ADDR1_HIGH */
    volatile uint32_t  MAC_Address1_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR1_LOW */
    volatile uint32_t  MAC_Address2_High;                /* ALT_EMAC_GMAC_MAC_ADDR2_HIGH */
    volatile uint32_t  MAC_Address2_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR2_LOW */
    volatile uint32_t  MAC_Address3_High;                /* ALT_EMAC_GMAC_MAC_ADDR3_HIGH */
    volatile uint32_t  MAC_Address3_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR3_LOW */
    volatile uint32_t  MAC_Address4_High;                /* ALT_EMAC_GMAC_MAC_ADDR4_HIGH */
    volatile uint32_t  MAC_Address4_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR4_LOW */
    volatile uint32_t  MAC_Address5_High;                /* ALT_EMAC_GMAC_MAC_ADDR5_HIGH */
    volatile uint32_t  MAC_Address5_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR5_LOW */
    volatile uint32_t  MAC_Address6_High;                /* ALT_EMAC_GMAC_MAC_ADDR6_HIGH */
    volatile uint32_t  MAC_Address6_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR6_LOW */
    volatile uint32_t  MAC_Address7_High;                /* ALT_EMAC_GMAC_MAC_ADDR7_HIGH */
    volatile uint32_t  MAC_Address7_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR7_LOW */
    volatile uint32_t  MAC_Address8_High;                /* ALT_EMAC_GMAC_MAC_ADDR8_HIGH */
    volatile uint32_t  MAC_Address8_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR8_LOW */
    volatile uint32_t  MAC_Address9_High;                /* ALT_EMAC_GMAC_MAC_ADDR9_HIGH */
    volatile uint32_t  MAC_Address9_Low;                 /* ALT_EMAC_GMAC_MAC_ADDR9_LOW */
    volatile uint32_t  MAC_Address10_High;               /* ALT_EMAC_GMAC_MAC_ADDR10_HIGH */
    volatile uint32_t  MAC_Address10_Low;                /* ALT_EMAC_GMAC_MAC_ADDR10_LOW */
    volatile uint32_t  MAC_Address11_High;               /* ALT_EMAC_GMAC_MAC_ADDR11_HIGH */
    volatile uint32_t  MAC_Address11_Low;                /* ALT_EMAC_GMAC_MAC_ADDR11_LOW */
    volatile uint32_t  MAC_Address12_High;               /* ALT_EMAC_GMAC_MAC_ADDR12_HIGH */
    volatile uint32_t  MAC_Address12_Low;                /* ALT_EMAC_GMAC_MAC_ADDR12_LOW */
    volatile uint32_t  MAC_Address13_High;               /* ALT_EMAC_GMAC_MAC_ADDR13_HIGH */
    volatile uint32_t  MAC_Address13_Low;                /* ALT_EMAC_GMAC_MAC_ADDR13_LOW */
    volatile uint32_t  MAC_Address14_High;               /* ALT_EMAC_GMAC_MAC_ADDR14_HIGH */
    volatile uint32_t  MAC_Address14_Low;                /* ALT_EMAC_GMAC_MAC_ADDR14_LOW */
    volatile uint32_t  MAC_Address15_High;               /* ALT_EMAC_GMAC_MAC_ADDR15_HIGH */
    volatile uint32_t  MAC_Address15_Low;                /* ALT_EMAC_GMAC_MAC_ADDR15_LOW */
    volatile uint32_t  _pad_0xc0_0xd7[6];                /* *UNDEFINED* */
    volatile uint32_t  SGMII_RGMII_SMII_Control_Status;  /* ALT_EMAC_GMAC_MII_CTL_STAT */
    volatile uint32_t  _pad_0xdc_0xff[9];                /* *UNDEFINED* */
    volatile uint32_t  MMC_Control;                      /* ALT_EMAC_GMAC_MMC_CTL */
    volatile uint32_t  MMC_Receive_Interrupt;            /* ALT_EMAC_GMAC_MMC_RX_INT */
    volatile uint32_t  MMC_Transmit_Interrupt;           /* ALT_EMAC_GMAC_MMC_TX_INT */
    volatile uint32_t  MMC_Receive_Interrupt_Mask;       /* ALT_EMAC_GMAC_MMC_RX_INT_MSK */
    volatile uint32_t  MMC_Transmit_Interrupt_Mask;      /* ALT_EMAC_GMAC_MMC_TX_INT_MSK */
    volatile uint32_t  txoctetcount_gb;                  /* ALT_EMAC_GMAC_TXOCTETCOUNT_GB */
    volatile uint32_t  txframecount_gb;                  /* ALT_EMAC_GMAC_TXFRMCOUNT_GB */
    volatile uint32_t  txbroadcastframes_g;              /* ALT_EMAC_GMAC_TXBCASTFRMS_G */
    volatile uint32_t  txmulticastframes_g;              /* ALT_EMAC_GMAC_TXMCASTFRMS_G */
    volatile uint32_t  tx64octets_gb;                    /* ALT_EMAC_GMAC_TX64OCTETS_GB */
    volatile uint32_t  tx65to127octets_gb;               /* ALT_EMAC_GMAC_TX65TO127OCTETS_GB */
    volatile uint32_t  tx128to255octets_gb;              /* ALT_EMAC_GMAC_TX128TO255OCTETS_GB */
    volatile uint32_t  tx256to511octets_gb;              /* ALT_EMAC_GMAC_TX256TO511OCTETS_GB */
    volatile uint32_t  tx512to1023octets_gb;             /* ALT_EMAC_GMAC_TX512TO1023OCTETS_GB */
    volatile uint32_t  tx1024tomaxoctets_gb;             /* ALT_EMAC_GMAC_TX1024TOMAXOCTETS_GB */
    volatile uint32_t  txunicastframes_gb;               /* ALT_EMAC_GMAC_TXUNICASTFRMS_GB */
    volatile uint32_t  txmulticastframes_gb;             /* ALT_EMAC_GMAC_TXMCASTFRMS_GB */
    volatile uint32_t  txbroadcastframes_gb;             /* ALT_EMAC_GMAC_TXBCASTFRMS_GB */
    volatile uint32_t  txunderflowerror;                 /* ALT_EMAC_GMAC_TXUNDERFLOWERROR */
    volatile uint32_t  txsinglecol_g;                    /* ALT_EMAC_GMAC_TXSINGLECOL_G */
    volatile uint32_t  txmulticol_g;                     /* ALT_EMAC_GMAC_TXMULTICOL_G */
    volatile uint32_t  txdeferred;                       /* ALT_EMAC_GMAC_TXDEFERRED */
    volatile uint32_t  txlatecol;                        /* ALT_EMAC_GMAC_TXLATECOL */
    volatile uint32_t  txexesscol;                       /* ALT_EMAC_GMAC_TXEXESSCOL */
    volatile uint32_t  txcarriererr;                     /* ALT_EMAC_GMAC_TXCARRIERERR */
    volatile uint32_t  txoctetcnt;                       /* ALT_EMAC_GMAC_TXOCTETCNT */
    volatile uint32_t  txframecount_g;                   /* ALT_EMAC_GMAC_TXFRMCOUNT_G */
    volatile uint32_t  txexcessdef;                      /* ALT_EMAC_GMAC_TXEXCESSDEF */
    volatile uint32_t  txpauseframes;                    /* ALT_EMAC_GMAC_TXPAUSEFRMS */
    volatile uint32_t  txvlanframes_g;                   /* ALT_EMAC_GMAC_TXVLANFRMS_G */
    volatile uint32_t  txoversize_g;                     /* ALT_EMAC_GMAC_TXOVERSIZE_G */
    volatile uint32_t  _pad_0x17c_0x17f;                 /* *UNDEFINED* */
    volatile uint32_t  rxframecount_gb;                  /* ALT_EMAC_GMAC_RXFRMCOUNT_GB */
    volatile uint32_t  rxoctetcount_gb;                  /* ALT_EMAC_GMAC_RXOCTETCOUNT_GB */
    volatile uint32_t  rxoctetcount_g;                   /* ALT_EMAC_GMAC_RXOCTETCOUNT_G */
    volatile uint32_t  rxbroadcastframes_g;              /* ALT_EMAC_GMAC_RXBCASTFRMS_G */
    volatile uint32_t  rxmulticastframes_g;              /* ALT_EMAC_GMAC_RXMCASTFRMS_G */
    volatile uint32_t  rxcrcerror;                       /* ALT_EMAC_GMAC_RXCRCERROR */
    volatile uint32_t  rxalignmenterror;                 /* ALT_EMAC_GMAC_RXALIGNMENTERROR */
    volatile uint32_t  rxrunterror;                      /* ALT_EMAC_GMAC_RXRUNTERROR */
    volatile uint32_t  rxjabbererror;                    /* ALT_EMAC_GMAC_RXJABBERERROR */
    volatile uint32_t  rxundersize_g;                    /* ALT_EMAC_GMAC_RXUNDERSIZE_G */
    volatile uint32_t  rxoversize_g;                     /* ALT_EMAC_GMAC_RXOVERSIZE_G */
    volatile uint32_t  rx64octets_gb;                    /* ALT_EMAC_GMAC_RX64OCTETS_GB */
    volatile uint32_t  rx65to127octets_gb;               /* ALT_EMAC_GMAC_RX65TO127OCTETS_GB */
    volatile uint32_t  rx128to255octets_gb;              /* ALT_EMAC_GMAC_RX128TO255OCTETS_GB */
    volatile uint32_t  rx256to511octets_gb;              /* ALT_EMAC_GMAC_RX256TO511OCTETS_GB */
    volatile uint32_t  rx512to1023octets_gb;             /* ALT_EMAC_GMAC_RX512TO1023OCTETS_GB */
    volatile uint32_t  rx1024tomaxoctets_gb;             /* ALT_EMAC_GMAC_RX1024TOMAXOCTETS_GB */
    volatile uint32_t  rxunicastframes_g;                /* ALT_EMAC_GMAC_RXUNICASTFRMS_G */
    volatile uint32_t  rxlengtherror;                    /* ALT_EMAC_GMAC_RXLENERROR */
    volatile uint32_t  rxoutofrangetype;                 /* ALT_EMAC_GMAC_RXOUTOFRANGETYPE */
    volatile uint32_t  rxpauseframes;                    /* ALT_EMAC_GMAC_RXPAUSEFRMS */
    volatile uint32_t  rxfifooverflow;                   /* ALT_EMAC_GMAC_RXFIFOOVF */
    volatile uint32_t  rxvlanframes_gb;                  /* ALT_EMAC_GMAC_RXVLANFRMS_GB */
    volatile uint32_t  rxwatchdogerror;                  /* ALT_EMAC_GMAC_RXWDERROR */
    volatile uint32_t  rxrcverror;                       /* ALT_EMAC_GMAC_RXRCVERROR */
    volatile uint32_t  rxctrlframes_g;                   /* ALT_EMAC_GMAC_RXCTLFRMS_G */
    volatile uint32_t  _pad_0x1e8_0x1ff[6];              /* *UNDEFINED* */
    volatile uint32_t  MMC_IPC_Receive_Interrupt_Mask;   /* ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK */
    volatile uint32_t  _pad_0x204_0x207;                 /* *UNDEFINED* */
    volatile uint32_t  MMC_IPC_Receive_Interrupt;        /* ALT_EMAC_GMAC_MMC_IPC_RX_INT */
    volatile uint32_t  _pad_0x20c_0x20f;                 /* *UNDEFINED* */
    volatile uint32_t  rxipv4_gd_frms;                   /* ALT_EMAC_GMAC_RXIPV4_GD_FRMS */
    volatile uint32_t  rxipv4_hdrerr_frms;               /* ALT_EMAC_GMAC_RXIPV4_HDRERR_FRMS */
    volatile uint32_t  rxipv4_nopay_frms;                /* ALT_EMAC_GMAC_RXIPV4_NOPAY_FRMS */
    volatile uint32_t  rxipv4_frag_frms;                 /* ALT_EMAC_GMAC_RXIPV4_FRAG_FRMS */
    volatile uint32_t  rxipv4_udsbl_frms;                /* ALT_EMAC_GMAC_RXIPV4_UDSBL_FRMS */
    volatile uint32_t  rxipv6_gd_frms;                   /* ALT_EMAC_GMAC_RXIPV6_GD_FRMS */
    volatile uint32_t  rxipv6_hdrerr_frms;               /* ALT_EMAC_GMAC_RXIPV6_HDRERR_FRMS */
    volatile uint32_t  rxipv6_nopay_frms;                /* ALT_EMAC_GMAC_RXIPV6_NOPAY_FRMS */
    volatile uint32_t  rxudp_gd_frms;                    /* ALT_EMAC_GMAC_RXUDP_GD_FRMS */
    volatile uint32_t  rxudp_err_frms;                   /* ALT_EMAC_GMAC_RXUDP_ERR_FRMS */
    volatile uint32_t  rxtcp_gd_frms;                    /* ALT_EMAC_GMAC_RXTCP_GD_FRMS */
    volatile uint32_t  rxtcp_err_frms;                   /* ALT_EMAC_GMAC_RXTCP_ERR_FRMS */
    volatile uint32_t  rxicmp_gd_frms;                   /* ALT_EMAC_GMAC_RXICMP_GD_FRMS */
    volatile uint32_t  rxicmp_err_frms;                  /* ALT_EMAC_GMAC_RXICMP_ERR_FRMS */
    volatile uint32_t  _pad_0x248_0x24f[2];              /* *UNDEFINED* */
    volatile uint32_t  rxipv4_gd_octets;                 /* ALT_EMAC_GMAC_RXIPV4_GD_OCTETS */
    volatile uint32_t  rxipv4_hdrerr_octets;             /* ALT_EMAC_GMAC_RXIPV4_HDRERR_OCTETS */
    volatile uint32_t  rxipv4_nopay_octets;              /* ALT_EMAC_GMAC_RXIPV4_NOPAY_OCTETS */
    volatile uint32_t  rxipv4_frag_octets;               /* ALT_EMAC_GMAC_RXIPV4_FRAG_OCTETS */
    volatile uint32_t  rxipv4_udsbl_octets;              /* ALT_EMAC_GMAC_RXIPV4_UDSBL_OCTETS */
    volatile uint32_t  rxipv6_gd_octets;                 /* ALT_EMAC_GMAC_RXIPV6_GD_OCTETS */
    volatile uint32_t  rxipv6_hdrerr_octets;             /* ALT_EMAC_GMAC_RXIPV6_HDRERR_OCTETS */
    volatile uint32_t  rxipv6_nopay_octets;              /* ALT_EMAC_GMAC_RXIPV6_NOPAY_OCTETS */
    volatile uint32_t  rxudp_gd_octets;                  /* ALT_EMAC_GMAC_RXUDP_GD_OCTETS */
    volatile uint32_t  rxudp_err_octets;                 /* ALT_EMAC_GMAC_RXUDP_ERR_OCTETS */
    volatile uint32_t  rxtcp_gd_octets;                  /* ALT_EMAC_GMAC_RXTCP_GD_OCTETS */
    volatile uint32_t  rxtcperroctets;                   /* ALT_EMAC_GMAC_RXTCPERROCTETS */
    volatile uint32_t  rxicmp_gd_octets;                 /* ALT_EMAC_GMAC_RXICMP_GD_OCTETS */
    volatile uint32_t  rxicmp_err_octets;                /* ALT_EMAC_GMAC_RXICMP_ERR_OCTETS */
    volatile uint32_t  _pad_0x288_0x3ff[94];             /* *UNDEFINED* */
    volatile uint32_t  L3_L4_Control0;                   /* ALT_EMAC_GMAC_L3_L4_CTL0 */
    volatile uint32_t  Layer4_Address0;                  /* ALT_EMAC_GMAC_LYR4_ADDR0 */
    volatile uint32_t  _pad_0x408_0x40f[2];              /* *UNDEFINED* */
    volatile uint32_t  Layer3_Addr0_Reg0;                /* ALT_EMAC_GMAC_LYR3_ADDR0_REG0 */
    volatile uint32_t  Layer3_Addr1_Reg0;                /* ALT_EMAC_GMAC_LYR3_ADDR1_REG0 */
    volatile uint32_t  Layer3_Addr2_Reg0;                /* ALT_EMAC_GMAC_LYR3_ADDR2_REG0 */
    volatile uint32_t  Layer3_Addr3_Reg0;                /* ALT_EMAC_GMAC_LYR3_ADDR3_REG0 */
    volatile uint32_t  _pad_0x420_0x42f[4];              /* *UNDEFINED* */
    volatile uint32_t  L3_L4_Control1;                   /* ALT_EMAC_GMAC_L3_L4_CTL1 */
    volatile uint32_t  Layer4_Address1;                  /* ALT_EMAC_GMAC_LYR4_ADDR1 */
    volatile uint32_t  _pad_0x438_0x43f[2];              /* *UNDEFINED* */
    volatile uint32_t  Layer3_Addr0_Reg1;                /* ALT_EMAC_GMAC_LYR3_ADDR0_REG1 */
    volatile uint32_t  Layer3_Addr1_Reg1;                /* ALT_EMAC_GMAC_LYR3_ADDR1_REG1 */
    volatile uint32_t  Layer3_Addr2_Reg1;                /* ALT_EMAC_GMAC_LYR3_ADDR2_REG1 */
    volatile uint32_t  Layer3_Addr3_Reg1;                /* ALT_EMAC_GMAC_LYR3_ADDR3_REG1 */
    volatile uint32_t  _pad_0x450_0x45f[4];              /* *UNDEFINED* */
    volatile uint32_t  L3_L4_Control2;                   /* ALT_EMAC_GMAC_L3_L4_CTL2 */
    volatile uint32_t  Layer4_Address2;                  /* ALT_EMAC_GMAC_LYR4_ADDR2 */
    volatile uint32_t  _pad_0x468_0x46f[2];              /* *UNDEFINED* */
    volatile uint32_t  Layer3_Addr0_Reg2;                /* ALT_EMAC_GMAC_LYR3_ADDR0_REG2 */
    volatile uint32_t  Layer3_Addr1_Reg2;                /* ALT_EMAC_GMAC_LYR3_ADDR1_REG2 */
    volatile uint32_t  Layer3_Addr2_Reg2;                /* ALT_EMAC_GMAC_LYR3_ADDR2_REG2 */
    volatile uint32_t  Layer3_Addr3_Reg2;                /* ALT_EMAC_GMAC_LYR3_ADDR3_REG2 */
    volatile uint32_t  _pad_0x480_0x48f[4];              /* *UNDEFINED* */
    volatile uint32_t  L3_L4_Control3;                   /* ALT_EMAC_GMAC_L3_L4_CTL3 */
    volatile uint32_t  Layer4_Address3;                  /* ALT_EMAC_GMAC_LYR4_ADDR3 */
    volatile uint32_t  _pad_0x498_0x49f[2];              /* *UNDEFINED* */
    volatile uint32_t  Layer3_Addr0_Reg3;                /* ALT_EMAC_GMAC_LYR3_ADDR0_REG3 */
    volatile uint32_t  Layer3_Addr1_Reg3;                /* ALT_EMAC_GMAC_LYR3_ADDR1_REG3 */
    volatile uint32_t  Layer3_Addr2_Reg3;                /* ALT_EMAC_GMAC_LYR3_ADDR2_REG3 */
    volatile uint32_t  Layer3_Addr3_Reg3;                /* ALT_EMAC_GMAC_LYR3_ADDR3_REG3 */
    volatile uint32_t  _pad_0x4b0_0x4ff[20];             /* *UNDEFINED* */
    volatile uint32_t  Hash_Table_Reg0;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG0 */
    volatile uint32_t  Hash_Table_Reg1;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG1 */
    volatile uint32_t  Hash_Table_Reg2;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG2 */
    volatile uint32_t  Hash_Table_Reg3;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG3 */
    volatile uint32_t  Hash_Table_Reg4;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG4 */
    volatile uint32_t  Hash_Table_Reg5;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG5 */
    volatile uint32_t  Hash_Table_Reg6;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG6 */
    volatile uint32_t  Hash_Table_Reg7;                  /* ALT_EMAC_GMAC_HASH_TABLE_REG7 */
    volatile uint32_t  _pad_0x520_0x583[25];             /* *UNDEFINED* */
    volatile uint32_t  VLAN_Incl_Reg;                    /* ALT_EMAC_GMAC_VLAN_INCL_REG */
    volatile uint32_t  VLAN_Hash_Table_Reg;              /* ALT_EMAC_GMAC_VLAN_HASH_TABLE_REG */
    volatile uint32_t  _pad_0x58c_0x6ff[93];             /* *UNDEFINED* */
    volatile uint32_t  Timestamp_Control;                /* ALT_EMAC_GMAC_TS_CTL */
    volatile uint32_t  Sub_Second_Increment;             /* ALT_EMAC_GMAC_SUB_SEC_INCREMENT */
    volatile uint32_t  System_Time_Seconds;              /* ALT_EMAC_GMAC_SYS_TIME_SECS */
    volatile uint32_t  System_Time_Nanoseconds;          /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS */
    volatile uint32_t  System_Time_Seconds_Update;       /* ALT_EMAC_GMAC_SYS_TIME_SECS_UPDATE */
    volatile uint32_t  System_Time_Nanoseconds_Update;   /* ALT_EMAC_GMAC_SYS_TIME_NANOSECS_UPDATE */
    volatile uint32_t  Timestamp_Addend;                 /* ALT_EMAC_GMAC_TS_ADDEND */
    volatile uint32_t  Target_Time_Seconds;              /* ALT_EMAC_GMAC_TGT_TIME_SECS */
    volatile uint32_t  Target_Time_Nanoseconds;          /* ALT_EMAC_GMAC_TGT_TIME_NANOSECS */
    volatile uint32_t  System_Time_Higher_Word_Seconds;  /* ALT_EMAC_GMAC_SYS_TIME_HIGHER_WORD_SECS */
    volatile uint32_t  Timestamp_Status;                 /* ALT_EMAC_GMAC_TS_STAT */
    volatile uint32_t  PPS_Control;                      /* ALT_EMAC_GMAC_PPS_CTL */
    volatile uint32_t  Auxiliary_Timestamp_Nanoseconds;  /* ALT_EMAC_GMAC_AUX_TS_NANOSECS */
    volatile uint32_t  Auxiliary_Timestamp_Seconds;      /* ALT_EMAC_GMAC_AUX_TS_SECS */
    volatile uint32_t  _pad_0x738_0x75f[10];             /* *UNDEFINED* */
    volatile uint32_t  PPS0_Interval;                    /* ALT_EMAC_GMAC_PPS0_INTERVAL */
    volatile uint32_t  PPS0_Width;                       /* ALT_EMAC_GMAC_PPS0_WIDTH */
    volatile uint32_t  _pad_0x768_0x7ff[38];             /* *UNDEFINED* */
    volatile uint32_t  MAC_Address16_High;               /* ALT_EMAC_GMAC_MAC_ADDR16_HIGH */
    volatile uint32_t  MAC_Address16_Low;                /* ALT_EMAC_GMAC_MAC_ADDR16_LOW */
    volatile uint32_t  MAC_Address17_High;               /* ALT_EMAC_GMAC_MAC_ADDR17_HIGH */
    volatile uint32_t  MAC_Address17_Low;                /* ALT_EMAC_GMAC_MAC_ADDR17_LOW */
    volatile uint32_t  MAC_Address18_High;               /* ALT_EMAC_GMAC_MAC_ADDR18_HIGH */
    volatile uint32_t  MAC_Address18_Low;                /* ALT_EMAC_GMAC_MAC_ADDR18_LOW */
    volatile uint32_t  MAC_Address19_High;               /* ALT_EMAC_GMAC_MAC_ADDR19_HIGH */
    volatile uint32_t  MAC_Address19_Low;                /* ALT_EMAC_GMAC_MAC_ADDR19_LOW */
    volatile uint32_t  MAC_Address20_High;               /* ALT_EMAC_GMAC_MAC_ADDR20_HIGH */
    volatile uint32_t  MAC_Address20_Low;                /* ALT_EMAC_GMAC_MAC_ADDR20_LOW */
    volatile uint32_t  MAC_Address21_High;               /* ALT_EMAC_GMAC_MAC_ADDR21_HIGH */
    volatile uint32_t  MAC_Address21_Low;                /* ALT_EMAC_GMAC_MAC_ADDR21_LOW */
    volatile uint32_t  MAC_Address22_High;               /* ALT_EMAC_GMAC_MAC_ADDR22_HIGH */
    volatile uint32_t  MAC_Address22_Low;                /* ALT_EMAC_GMAC_MAC_ADDR22_LOW */
    volatile uint32_t  MAC_Address23_High;               /* ALT_EMAC_GMAC_MAC_ADDR23_HIGH */
    volatile uint32_t  MAC_Address23_Low;                /* ALT_EMAC_GMAC_MAC_ADDR23_LOW */
    volatile uint32_t  MAC_Address24_High;               /* ALT_EMAC_GMAC_MAC_ADDR24_HIGH */
    volatile uint32_t  MAC_Address24_Low;                /* ALT_EMAC_GMAC_MAC_ADDR24_LOW */
    volatile uint32_t  MAC_Address25_High;               /* ALT_EMAC_GMAC_MAC_ADDR25_HIGH */
    volatile uint32_t  MAC_Address25_Low;                /* ALT_EMAC_GMAC_MAC_ADDR25_LOW */
    volatile uint32_t  MAC_Address26_High;               /* ALT_EMAC_GMAC_MAC_ADDR26_HIGH */
    volatile uint32_t  MAC_Address26_Low;                /* ALT_EMAC_GMAC_MAC_ADDR26_LOW */
    volatile uint32_t  MAC_Address27_High;               /* ALT_EMAC_GMAC_MAC_ADDR27_HIGH */
    volatile uint32_t  MAC_Address27_Low;                /* ALT_EMAC_GMAC_MAC_ADDR27_LOW */
    volatile uint32_t  MAC_Address28_High;               /* ALT_EMAC_GMAC_MAC_ADDR28_HIGH */
    volatile uint32_t  MAC_Address28_Low;                /* ALT_EMAC_GMAC_MAC_ADDR28_LOW */
    volatile uint32_t  MAC_Address29_High;               /* ALT_EMAC_GMAC_MAC_ADDR29_HIGH */
    volatile uint32_t  MAC_Address29_Low;                /* ALT_EMAC_GMAC_MAC_ADDR29_LOW */
    volatile uint32_t  MAC_Address30_High;               /* ALT_EMAC_GMAC_MAC_ADDR30_HIGH */
    volatile uint32_t  MAC_Address30_Low;                /* ALT_EMAC_GMAC_MAC_ADDR30_LOW */
    volatile uint32_t  MAC_Address31_High;               /* ALT_EMAC_GMAC_MAC_ADDR31_HIGH */
    volatile uint32_t  MAC_Address31_Low;                /* ALT_EMAC_GMAC_MAC_ADDR31_LOW */
    volatile uint32_t  MAC_Address32_High;               /* ALT_EMAC_GMAC_MAC_ADDR32_HIGH */
    volatile uint32_t  MAC_Address32_Low;                /* ALT_EMAC_GMAC_MAC_ADDR32_LOW */
    volatile uint32_t  MAC_Address33_High;               /* ALT_EMAC_GMAC_MAC_ADDR33_HIGH */
    volatile uint32_t  MAC_Address33_Low;                /* ALT_EMAC_GMAC_MAC_ADDR33_LOW */
    volatile uint32_t  MAC_Address34_High;               /* ALT_EMAC_GMAC_MAC_ADDR34_HIGH */
    volatile uint32_t  MAC_Address34_Low;                /* ALT_EMAC_GMAC_MAC_ADDR34_LOW */
    volatile uint32_t  MAC_Address35_High;               /* ALT_EMAC_GMAC_MAC_ADDR35_HIGH */
    volatile uint32_t  MAC_Address35_Low;                /* ALT_EMAC_GMAC_MAC_ADDR35_LOW */
    volatile uint32_t  MAC_Address36_High;               /* ALT_EMAC_GMAC_MAC_ADDR36_HIGH */
    volatile uint32_t  MAC_Address36_Low;                /* ALT_EMAC_GMAC_MAC_ADDR36_LOW */
    volatile uint32_t  MAC_Address37_High;               /* ALT_EMAC_GMAC_MAC_ADDR37_HIGH */
    volatile uint32_t  MAC_Address37_Low;                /* ALT_EMAC_GMAC_MAC_ADDR37_LOW */
    volatile uint32_t  MAC_Address38_High;               /* ALT_EMAC_GMAC_MAC_ADDR38_HIGH */
    volatile uint32_t  MAC_Address38_Low;                /* ALT_EMAC_GMAC_MAC_ADDR38_LOW */
    volatile uint32_t  MAC_Address39_High;               /* ALT_EMAC_GMAC_MAC_ADDR39_HIGH */
    volatile uint32_t  MAC_Address39_Low;                /* ALT_EMAC_GMAC_MAC_ADDR39_LOW */
    volatile uint32_t  MAC_Address40_High;               /* ALT_EMAC_GMAC_MAC_ADDR40_HIGH */
    volatile uint32_t  MAC_Address40_Low;                /* ALT_EMAC_GMAC_MAC_ADDR40_LOW */
    volatile uint32_t  MAC_Address41_High;               /* ALT_EMAC_GMAC_MAC_ADDR41_HIGH */
    volatile uint32_t  MAC_Address41_Low;                /* ALT_EMAC_GMAC_MAC_ADDR41_LOW */
    volatile uint32_t  MAC_Address42_High;               /* ALT_EMAC_GMAC_MAC_ADDR42_HIGH */
    volatile uint32_t  MAC_Address42_Low;                /* ALT_EMAC_GMAC_MAC_ADDR42_LOW */
    volatile uint32_t  MAC_Address43_High;               /* ALT_EMAC_GMAC_MAC_ADDR43_HIGH */
    volatile uint32_t  MAC_Address43_Low;                /* ALT_EMAC_GMAC_MAC_ADDR43_LOW */
    volatile uint32_t  MAC_Address44_High;               /* ALT_EMAC_GMAC_MAC_ADDR44_HIGH */
    volatile uint32_t  MAC_Address44_Low;                /* ALT_EMAC_GMAC_MAC_ADDR44_LOW */
    volatile uint32_t  MAC_Address45_High;               /* ALT_EMAC_GMAC_MAC_ADDR45_HIGH */
    volatile uint32_t  MAC_Address45_Low;                /* ALT_EMAC_GMAC_MAC_ADDR45_LOW */
    volatile uint32_t  MAC_Address46_High;               /* ALT_EMAC_GMAC_MAC_ADDR46_HIGH */
    volatile uint32_t  MAC_Address46_Low;                /* ALT_EMAC_GMAC_MAC_ADDR46_LOW */
    volatile uint32_t  MAC_Address47_High;               /* ALT_EMAC_GMAC_MAC_ADDR47_HIGH */
    volatile uint32_t  MAC_Address47_Low;                /* ALT_EMAC_GMAC_MAC_ADDR47_LOW */
    volatile uint32_t  MAC_Address48_High;               /* ALT_EMAC_GMAC_MAC_ADDR48_HIGH */
    volatile uint32_t  MAC_Address48_Low;                /* ALT_EMAC_GMAC_MAC_ADDR48_LOW */
    volatile uint32_t  MAC_Address49_High;               /* ALT_EMAC_GMAC_MAC_ADDR49_HIGH */
    volatile uint32_t  MAC_Address49_Low;                /* ALT_EMAC_GMAC_MAC_ADDR49_LOW */
    volatile uint32_t  MAC_Address50_High;               /* ALT_EMAC_GMAC_MAC_ADDR50_HIGH */
    volatile uint32_t  MAC_Address50_Low;                /* ALT_EMAC_GMAC_MAC_ADDR50_LOW */
    volatile uint32_t  MAC_Address51_High;               /* ALT_EMAC_GMAC_MAC_ADDR51_HIGH */
    volatile uint32_t  MAC_Address51_Low;                /* ALT_EMAC_GMAC_MAC_ADDR51_LOW */
    volatile uint32_t  MAC_Address52_High;               /* ALT_EMAC_GMAC_MAC_ADDR52_HIGH */
    volatile uint32_t  MAC_Address52_Low;                /* ALT_EMAC_GMAC_MAC_ADDR52_LOW */
    volatile uint32_t  MAC_Address53_High;               /* ALT_EMAC_GMAC_MAC_ADDR53_HIGH */
    volatile uint32_t  MAC_Address53_Low;                /* ALT_EMAC_GMAC_MAC_ADDR53_LOW */
    volatile uint32_t  MAC_Address54_High;               /* ALT_EMAC_GMAC_MAC_ADDR54_HIGH */
    volatile uint32_t  MAC_Address54_Low;                /* ALT_EMAC_GMAC_MAC_ADDR54_LOW */
    volatile uint32_t  MAC_Address55_High;               /* ALT_EMAC_GMAC_MAC_ADDR55_HIGH */
    volatile uint32_t  MAC_Address55_Low;                /* ALT_EMAC_GMAC_MAC_ADDR55_LOW */
    volatile uint32_t  MAC_Address56_High;               /* ALT_EMAC_GMAC_MAC_ADDR56_HIGH */
    volatile uint32_t  MAC_Address56_Low;                /* ALT_EMAC_GMAC_MAC_ADDR56_LOW */
    volatile uint32_t  MAC_Address57_High;               /* ALT_EMAC_GMAC_MAC_ADDR57_HIGH */
    volatile uint32_t  MAC_Address57_Low;                /* ALT_EMAC_GMAC_MAC_ADDR57_LOW */
    volatile uint32_t  MAC_Address58_High;               /* ALT_EMAC_GMAC_MAC_ADDR58_HIGH */
    volatile uint32_t  MAC_Address58_Low;                /* ALT_EMAC_GMAC_MAC_ADDR58_LOW */
    volatile uint32_t  MAC_Address59_High;               /* ALT_EMAC_GMAC_MAC_ADDR59_HIGH */
    volatile uint32_t  MAC_Address59_Low;                /* ALT_EMAC_GMAC_MAC_ADDR59_LOW */
    volatile uint32_t  MAC_Address60_High;               /* ALT_EMAC_GMAC_MAC_ADDR60_HIGH */
    volatile uint32_t  MAC_Address60_Low;                /* ALT_EMAC_GMAC_MAC_ADDR60_LOW */
    volatile uint32_t  MAC_Address61_High;               /* ALT_EMAC_GMAC_MAC_ADDR61_HIGH */
    volatile uint32_t  MAC_Address61_Low;                /* ALT_EMAC_GMAC_MAC_ADDR61_LOW */
    volatile uint32_t  MAC_Address62_High;               /* ALT_EMAC_GMAC_MAC_ADDR62_HIGH */
    volatile uint32_t  MAC_Address62_Low;                /* ALT_EMAC_GMAC_MAC_ADDR62_LOW */
    volatile uint32_t  MAC_Address63_High;               /* ALT_EMAC_GMAC_MAC_ADDR63_HIGH */
    volatile uint32_t  MAC_Address63_Low;                /* ALT_EMAC_GMAC_MAC_ADDR63_LOW */
    volatile uint32_t  MAC_Address64_High;               /* ALT_EMAC_GMAC_MAC_ADDR64_HIGH */
    volatile uint32_t  MAC_Address64_Low;                /* ALT_EMAC_GMAC_MAC_ADDR64_LOW */
    volatile uint32_t  MAC_Address65_High;               /* ALT_EMAC_GMAC_MAC_ADDR65_HIGH */
    volatile uint32_t  MAC_Address65_Low;                /* ALT_EMAC_GMAC_MAC_ADDR65_LOW */
    volatile uint32_t  MAC_Address66_High;               /* ALT_EMAC_GMAC_MAC_ADDR66_HIGH */
    volatile uint32_t  MAC_Address66_Low;                /* ALT_EMAC_GMAC_MAC_ADDR66_LOW */
    volatile uint32_t  MAC_Address67_High;               /* ALT_EMAC_GMAC_MAC_ADDR67_HIGH */
    volatile uint32_t  MAC_Address67_Low;                /* ALT_EMAC_GMAC_MAC_ADDR67_LOW */
    volatile uint32_t  MAC_Address68_High;               /* ALT_EMAC_GMAC_MAC_ADDR68_HIGH */
    volatile uint32_t  MAC_Address68_Low;                /* ALT_EMAC_GMAC_MAC_ADDR68_LOW */
    volatile uint32_t  MAC_Address69_High;               /* ALT_EMAC_GMAC_MAC_ADDR69_HIGH */
    volatile uint32_t  MAC_Address69_Low;                /* ALT_EMAC_GMAC_MAC_ADDR69_LOW */
    volatile uint32_t  MAC_Address70_High;               /* ALT_EMAC_GMAC_MAC_ADDR70_HIGH */
    volatile uint32_t  MAC_Address70_Low;                /* ALT_EMAC_GMAC_MAC_ADDR70_LOW */
    volatile uint32_t  MAC_Address71_High;               /* ALT_EMAC_GMAC_MAC_ADDR71_HIGH */
    volatile uint32_t  MAC_Address71_Low;                /* ALT_EMAC_GMAC_MAC_ADDR71_LOW */
    volatile uint32_t  MAC_Address72_High;               /* ALT_EMAC_GMAC_MAC_ADDR72_HIGH */
    volatile uint32_t  MAC_Address72_Low;                /* ALT_EMAC_GMAC_MAC_ADDR72_LOW */
    volatile uint32_t  MAC_Address73_High;               /* ALT_EMAC_GMAC_MAC_ADDR73_HIGH */
    volatile uint32_t  MAC_Address73_Low;                /* ALT_EMAC_GMAC_MAC_ADDR73_LOW */
    volatile uint32_t  MAC_Address74_High;               /* ALT_EMAC_GMAC_MAC_ADDR74_HIGH */
    volatile uint32_t  MAC_Address74_Low;                /* ALT_EMAC_GMAC_MAC_ADDR74_LOW */
    volatile uint32_t  MAC_Address75_High;               /* ALT_EMAC_GMAC_MAC_ADDR75_HIGH */
    volatile uint32_t  MAC_Address75_Low;                /* ALT_EMAC_GMAC_MAC_ADDR75_LOW */
    volatile uint32_t  MAC_Address76_High;               /* ALT_EMAC_GMAC_MAC_ADDR76_HIGH */
    volatile uint32_t  MAC_Address76_Low;                /* ALT_EMAC_GMAC_MAC_ADDR76_LOW */
    volatile uint32_t  MAC_Address77_High;               /* ALT_EMAC_GMAC_MAC_ADDR77_HIGH */
    volatile uint32_t  MAC_Address77_Low;                /* ALT_EMAC_GMAC_MAC_ADDR77_LOW */
    volatile uint32_t  MAC_Address78_High;               /* ALT_EMAC_GMAC_MAC_ADDR78_HIGH */
    volatile uint32_t  MAC_Address78_Low;                /* ALT_EMAC_GMAC_MAC_ADDR78_LOW */
    volatile uint32_t  MAC_Address79_High;               /* ALT_EMAC_GMAC_MAC_ADDR79_HIGH */
    volatile uint32_t  MAC_Address79_Low;                /* ALT_EMAC_GMAC_MAC_ADDR79_LOW */
    volatile uint32_t  MAC_Address80_High;               /* ALT_EMAC_GMAC_MAC_ADDR80_HIGH */
    volatile uint32_t  MAC_Address80_Low;                /* ALT_EMAC_GMAC_MAC_ADDR80_LOW */
    volatile uint32_t  MAC_Address81_High;               /* ALT_EMAC_GMAC_MAC_ADDR81_HIGH */
    volatile uint32_t  MAC_Address81_Low;                /* ALT_EMAC_GMAC_MAC_ADDR81_LOW */
    volatile uint32_t  MAC_Address82_High;               /* ALT_EMAC_GMAC_MAC_ADDR82_HIGH */
    volatile uint32_t  MAC_Address82_Low;                /* ALT_EMAC_GMAC_MAC_ADDR82_LOW */
    volatile uint32_t  MAC_Address83_High;               /* ALT_EMAC_GMAC_MAC_ADDR83_HIGH */
    volatile uint32_t  MAC_Address83_Low;                /* ALT_EMAC_GMAC_MAC_ADDR83_LOW */
    volatile uint32_t  MAC_Address84_High;               /* ALT_EMAC_GMAC_MAC_ADDR84_HIGH */
    volatile uint32_t  MAC_Address84_Low;                /* ALT_EMAC_GMAC_MAC_ADDR84_LOW */
    volatile uint32_t  MAC_Address85_High;               /* ALT_EMAC_GMAC_MAC_ADDR85_HIGH */
    volatile uint32_t  MAC_Address85_Low;                /* ALT_EMAC_GMAC_MAC_ADDR85_LOW */
    volatile uint32_t  MAC_Address86_High;               /* ALT_EMAC_GMAC_MAC_ADDR86_HIGH */
    volatile uint32_t  MAC_Address86_Low;                /* ALT_EMAC_GMAC_MAC_ADDR86_LOW */
    volatile uint32_t  MAC_Address87_High;               /* ALT_EMAC_GMAC_MAC_ADDR87_HIGH */
    volatile uint32_t  MAC_Address87_Low;                /* ALT_EMAC_GMAC_MAC_ADDR87_LOW */
    volatile uint32_t  MAC_Address88_High;               /* ALT_EMAC_GMAC_MAC_ADDR88_HIGH */
    volatile uint32_t  MAC_Address88_Low;                /* ALT_EMAC_GMAC_MAC_ADDR88_LOW */
    volatile uint32_t  MAC_Address89_High;               /* ALT_EMAC_GMAC_MAC_ADDR89_HIGH */
    volatile uint32_t  MAC_Address89_Low;                /* ALT_EMAC_GMAC_MAC_ADDR89_LOW */
    volatile uint32_t  MAC_Address90_High;               /* ALT_EMAC_GMAC_MAC_ADDR90_HIGH */
    volatile uint32_t  MAC_Address90_Low;                /* ALT_EMAC_GMAC_MAC_ADDR90_LOW */
    volatile uint32_t  MAC_Address91_High;               /* ALT_EMAC_GMAC_MAC_ADDR91_HIGH */
    volatile uint32_t  MAC_Address91_Low;                /* ALT_EMAC_GMAC_MAC_ADDR91_LOW */
    volatile uint32_t  MAC_Address92_High;               /* ALT_EMAC_GMAC_MAC_ADDR92_HIGH */
    volatile uint32_t  MAC_Address92_Low;                /* ALT_EMAC_GMAC_MAC_ADDR92_LOW */
    volatile uint32_t  MAC_Address93_High;               /* ALT_EMAC_GMAC_MAC_ADDR93_HIGH */
    volatile uint32_t  MAC_Address93_Low;                /* ALT_EMAC_GMAC_MAC_ADDR93_LOW */
    volatile uint32_t  MAC_Address94_High;               /* ALT_EMAC_GMAC_MAC_ADDR94_HIGH */
    volatile uint32_t  MAC_Address94_Low;                /* ALT_EMAC_GMAC_MAC_ADDR94_LOW */
    volatile uint32_t  MAC_Address95_High;               /* ALT_EMAC_GMAC_MAC_ADDR95_HIGH */
    volatile uint32_t  MAC_Address95_Low;                /* ALT_EMAC_GMAC_MAC_ADDR95_LOW */
    volatile uint32_t  MAC_Address96_High;               /* ALT_EMAC_GMAC_MAC_ADDR96_HIGH */
    volatile uint32_t  MAC_Address96_Low;                /* ALT_EMAC_GMAC_MAC_ADDR96_LOW */
    volatile uint32_t  MAC_Address97_High;               /* ALT_EMAC_GMAC_MAC_ADDR97_HIGH */
    volatile uint32_t  MAC_Address97_Low;                /* ALT_EMAC_GMAC_MAC_ADDR97_LOW */
    volatile uint32_t  MAC_Address98_High;               /* ALT_EMAC_GMAC_MAC_ADDR98_HIGH */
    volatile uint32_t  MAC_Address98_Low;                /* ALT_EMAC_GMAC_MAC_ADDR98_LOW */
    volatile uint32_t  MAC_Address99_High;               /* ALT_EMAC_GMAC_MAC_ADDR99_HIGH */
    volatile uint32_t  MAC_Address99_Low;                /* ALT_EMAC_GMAC_MAC_ADDR99_LOW */
    volatile uint32_t  MAC_Address100_High;              /* ALT_EMAC_GMAC_MAC_ADDR100_HIGH */
    volatile uint32_t  MAC_Address100_Low;               /* ALT_EMAC_GMAC_MAC_ADDR100_LOW */
    volatile uint32_t  MAC_Address101_High;              /* ALT_EMAC_GMAC_MAC_ADDR101_HIGH */
    volatile uint32_t  MAC_Address101_Low;               /* ALT_EMAC_GMAC_MAC_ADDR101_LOW */
    volatile uint32_t  MAC_Address102_High;              /* ALT_EMAC_GMAC_MAC_ADDR102_HIGH */
    volatile uint32_t  MAC_Address102_Low;               /* ALT_EMAC_GMAC_MAC_ADDR102_LOW */
    volatile uint32_t  MAC_Address103_High;              /* ALT_EMAC_GMAC_MAC_ADDR103_HIGH */
    volatile uint32_t  MAC_Address103_Low;               /* ALT_EMAC_GMAC_MAC_ADDR103_LOW */
    volatile uint32_t  MAC_Address104_High;              /* ALT_EMAC_GMAC_MAC_ADDR104_HIGH */
    volatile uint32_t  MAC_Address104_Low;               /* ALT_EMAC_GMAC_MAC_ADDR104_LOW */
    volatile uint32_t  MAC_Address105_High;              /* ALT_EMAC_GMAC_MAC_ADDR105_HIGH */
    volatile uint32_t  MAC_Address105_Low;               /* ALT_EMAC_GMAC_MAC_ADDR105_LOW */
    volatile uint32_t  MAC_Address106_High;              /* ALT_EMAC_GMAC_MAC_ADDR106_HIGH */
    volatile uint32_t  MAC_Address106_Low;               /* ALT_EMAC_GMAC_MAC_ADDR106_LOW */
    volatile uint32_t  MAC_Address107_High;              /* ALT_EMAC_GMAC_MAC_ADDR107_HIGH */
    volatile uint32_t  MAC_Address107_Low;               /* ALT_EMAC_GMAC_MAC_ADDR107_LOW */
    volatile uint32_t  MAC_Address108_High;              /* ALT_EMAC_GMAC_MAC_ADDR108_HIGH */
    volatile uint32_t  MAC_Address108_Low;               /* ALT_EMAC_GMAC_MAC_ADDR108_LOW */
    volatile uint32_t  MAC_Address109_High;              /* ALT_EMAC_GMAC_MAC_ADDR109_HIGH */
    volatile uint32_t  MAC_Address109_Low;               /* ALT_EMAC_GMAC_MAC_ADDR109_LOW */
    volatile uint32_t  MAC_Address110_High;              /* ALT_EMAC_GMAC_MAC_ADDR110_HIGH */
    volatile uint32_t  MAC_Address110_Low;               /* ALT_EMAC_GMAC_MAC_ADDR110_LOW */
    volatile uint32_t  MAC_Address111_High;              /* ALT_EMAC_GMAC_MAC_ADDR111_HIGH */
    volatile uint32_t  MAC_Address111_Low;               /* ALT_EMAC_GMAC_MAC_ADDR111_LOW */
    volatile uint32_t  MAC_Address112_High;              /* ALT_EMAC_GMAC_MAC_ADDR112_HIGH */
    volatile uint32_t  MAC_Address112_Low;               /* ALT_EMAC_GMAC_MAC_ADDR112_LOW */
    volatile uint32_t  MAC_Address113_High;              /* ALT_EMAC_GMAC_MAC_ADDR113_HIGH */
    volatile uint32_t  MAC_Address113_Low;               /* ALT_EMAC_GMAC_MAC_ADDR113_LOW */
    volatile uint32_t  MAC_Address114_High;              /* ALT_EMAC_GMAC_MAC_ADDR114_HIGH */
    volatile uint32_t  MAC_Address114_Low;               /* ALT_EMAC_GMAC_MAC_ADDR114_LOW */
    volatile uint32_t  MAC_Address115_High;              /* ALT_EMAC_GMAC_MAC_ADDR115_HIGH */
    volatile uint32_t  MAC_Address115_Low;               /* ALT_EMAC_GMAC_MAC_ADDR115_LOW */
    volatile uint32_t  MAC_Address116_High;              /* ALT_EMAC_GMAC_MAC_ADDR116_HIGH */
    volatile uint32_t  MAC_Address116_Low;               /* ALT_EMAC_GMAC_MAC_ADDR116_LOW */
    volatile uint32_t  MAC_Address117_High;              /* ALT_EMAC_GMAC_MAC_ADDR117_HIGH */
    volatile uint32_t  MAC_Address117_Low;               /* ALT_EMAC_GMAC_MAC_ADDR117_LOW */
    volatile uint32_t  MAC_Address118_High;              /* ALT_EMAC_GMAC_MAC_ADDR118_HIGH */
    volatile uint32_t  MAC_Address118_Low;               /* ALT_EMAC_GMAC_MAC_ADDR118_LOW */
    volatile uint32_t  MAC_Address119_High;              /* ALT_EMAC_GMAC_MAC_ADDR119_HIGH */
    volatile uint32_t  MAC_Address119_Low;               /* ALT_EMAC_GMAC_MAC_ADDR119_LOW */
    volatile uint32_t  MAC_Address120_High;              /* ALT_EMAC_GMAC_MAC_ADDR120_HIGH */
    volatile uint32_t  MAC_Address120_Low;               /* ALT_EMAC_GMAC_MAC_ADDR120_LOW */
    volatile uint32_t  MAC_Address121_High;              /* ALT_EMAC_GMAC_MAC_ADDR121_HIGH */
    volatile uint32_t  MAC_Address121_Low;               /* ALT_EMAC_GMAC_MAC_ADDR121_LOW */
    volatile uint32_t  MAC_Address122_High;              /* ALT_EMAC_GMAC_MAC_ADDR122_HIGH */
    volatile uint32_t  MAC_Address122_Low;               /* ALT_EMAC_GMAC_MAC_ADDR122_LOW */
    volatile uint32_t  MAC_Address123_High;              /* ALT_EMAC_GMAC_MAC_ADDR123_HIGH */
    volatile uint32_t  MAC_Address123_Low;               /* ALT_EMAC_GMAC_MAC_ADDR123_LOW */
    volatile uint32_t  MAC_Address124_High;              /* ALT_EMAC_GMAC_MAC_ADDR124_HIGH */
    volatile uint32_t  MAC_Address124_Low;               /* ALT_EMAC_GMAC_MAC_ADDR124_LOW */
    volatile uint32_t  MAC_Address125_High;              /* ALT_EMAC_GMAC_MAC_ADDR125_HIGH */
    volatile uint32_t  MAC_Address125_Low;               /* ALT_EMAC_GMAC_MAC_ADDR125_LOW */
    volatile uint32_t  MAC_Address126_High;              /* ALT_EMAC_GMAC_MAC_ADDR126_HIGH */
    volatile uint32_t  MAC_Address126_Low;               /* ALT_EMAC_GMAC_MAC_ADDR126_LOW */
    volatile uint32_t  MAC_Address127_High;              /* ALT_EMAC_GMAC_MAC_ADDR127_HIGH */
    volatile uint32_t  MAC_Address127_Low;               /* ALT_EMAC_GMAC_MAC_ADDR127_LOW */
};

/* The typedef declaration for the raw register contents of register group ALT_EMAC_GMAC. */
typedef volatile struct ALT_EMAC_GMAC_raw_s  ALT_EMAC_GMAC_raw_t;
#endif  /* __ASSEMBLY__ */


/*
 * Register Group : DMA Register Group - ALT_EMAC_DMA
 * DMA Register Group
 * 
 * DMA Register Group
 * 
 */
/*
 * Register : Register 0 (Bus Mode Register) - Bus_Mode
 * 
 * The Bus Mode register establishes the bus operating modes for the DMA.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description              
 * :--------|:-------|:------|:--------------------------
 *  [0]     | RW     | 0x1   | Software Reset           
 *  [1]     | ???    | 0x0   | *UNDEFINED*              
 *  [6:2]   | RW     | 0x0   | Descriptor Skip Length   
 *  [7]     | RW     | 0x0   | Alternate Descriptor Size
 *  [13:8]  | RW     | 0x1   | Programmable Burst Length
 *  [15:14] | ???    | 0x0   | *UNDEFINED*              
 *  [16]    | RW     | 0x0   | Fixed Burst              
 *  [22:17] | RW     | 0x1   | Rx DMA PBL               
 *  [23]    | RW     | 0x0   | Use Separate PBL         
 *  [24]    | RW     | 0x0   | 8xPBL Mode               
 *  [25]    | RW     | 0x0   | Address Aligned Beats    
 *  [31:26] | ???    | 0x0   | *UNDEFINED*              
 * 
 */
/*
 * Field : Software Reset - swr
 * 
 * When this bit is set, the MAC DMA Controller resets the logic and all internal
 * registers of the MAC. It is cleared automatically after the reset operation has
 * completed in all of the EMAC clock domains. Before reprogramming any register of
 * the EMAC, you should read a zero (0) value in this bit .
 * 
 * Note:
 * 
 * * The Software reset function is driven only by this bit. Bit 0 of Register 64
 *   (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register)
 *   has no impact on the Software reset function.
 * 
 * * The reset operation is completed only when all resets in all active clock
 *   domains are de-asserted. Therefore, it is essential that all the PHY inputs
 *   clocks (applicable for the selected PHY interface) are present for the
 *   software reset completion.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                              | Value | Description                    
 * :----------------------------------|:------|:--------------------------------
 *  ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST | 0x0   | MAC DMA Controller Clears Logic
 *  ALT_EMAC_DMA_BUS_MOD_SWR_E_RST    | 0x1   | MAC DMA Controller Resets Logic
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR
 * 
 * MAC DMA Controller Clears Logic
 */
#define ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR
 * 
 * MAC DMA Controller Resets Logic
 */
#define ALT_EMAC_DMA_BUS_MOD_SWR_E_RST      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
#define ALT_EMAC_DMA_BUS_MOD_SWR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
#define ALT_EMAC_DMA_BUS_MOD_SWR_MSB        0
/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
#define ALT_EMAC_DMA_BUS_MOD_SWR_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_SWR register field value. */
#define ALT_EMAC_DMA_BUS_MOD_SWR_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_SWR register field value. */
#define ALT_EMAC_DMA_BUS_MOD_SWR_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_DMA_BUS_MOD_SWR register field. */
#define ALT_EMAC_DMA_BUS_MOD_SWR_RESET      0x1
/* Extracts the ALT_EMAC_DMA_BUS_MOD_SWR field value from a register. */
#define ALT_EMAC_DMA_BUS_MOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_DMA_BUS_MOD_SWR register field value suitable for setting the register. */
#define ALT_EMAC_DMA_BUS_MOD_SWR_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Descriptor Skip Length - dsl
 * 
 * This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit,
 * 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address
 * skipping starts from the end of current descriptor to the start of next
 * descriptor. When the DSL value is equal to zero, then the descriptor table is
 * taken as contiguous by the DMA in Ring mode.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
#define ALT_EMAC_DMA_BUS_MOD_DSL_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
#define ALT_EMAC_DMA_BUS_MOD_DSL_MSB        6
/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
#define ALT_EMAC_DMA_BUS_MOD_DSL_WIDTH      5
/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_DSL register field value. */
#define ALT_EMAC_DMA_BUS_MOD_DSL_SET_MSK    0x0000007c
/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_DSL register field value. */
#define ALT_EMAC_DMA_BUS_MOD_DSL_CLR_MSK    0xffffff83
/* The reset value of the ALT_EMAC_DMA_BUS_MOD_DSL register field. */
#define ALT_EMAC_DMA_BUS_MOD_DSL_RESET      0x0
/* Extracts the ALT_EMAC_DMA_BUS_MOD_DSL field value from a register. */
#define ALT_EMAC_DMA_BUS_MOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
/* Produces a ALT_EMAC_DMA_BUS_MOD_DSL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_BUS_MOD_DSL_SET(value) (((value) << 2) & 0x0000007c)

/*
 * Field : Alternate Descriptor Size - atds
 * 
 * When set, the size of the alternate descriptor increases to 32 bytes (8 DWORDS).
 * This is required when the Advanced Timestamp feature or the IPC Full Offload
 * Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not
 * required if the Advanced Timestamp and IPC Full Checksum Offload (Type 2)
 * features are not enabled. In such cases, you can use the 16 bytes descriptor to
 * save 4 bytes of memory.
 * 
 * When reset, the descriptor size reverts back to 4 DWORDs (16 bytes).
 * 
 * This bit preserves the backward compatibility for the descriptor size. In
 * versions prior to 3.50a, the descriptor size is 16 bytes for both normal and
 * enhanced descriptor. In version 3.50a, descriptor size is increased to 32 bytes
 * because of the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2)
 * features.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                    
 * :-----------------------------------|:------|:--------------------------------
 *  ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST | 0x0   | MAC DMA Controller Clears Logic
 *  ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST    | 0x1   | MAC DMA Controller Resets Logic
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS
 * 
 * MAC DMA Controller Clears Logic
 */
#define ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS
 * 
 * MAC DMA Controller Resets Logic
 */
#define ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
#define ALT_EMAC_DMA_BUS_MOD_ATDS_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
#define ALT_EMAC_DMA_BUS_MOD_ATDS_MSB        7
/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
#define ALT_EMAC_DMA_BUS_MOD_ATDS_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_ATDS register field value. */
#define ALT_EMAC_DMA_BUS_MOD_ATDS_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_ATDS register field value. */
#define ALT_EMAC_DMA_BUS_MOD_ATDS_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_DMA_BUS_MOD_ATDS register field. */
#define ALT_EMAC_DMA_BUS_MOD_ATDS_RESET      0x0
/* Extracts the ALT_EMAC_DMA_BUS_MOD_ATDS field value from a register. */
#define ALT_EMAC_DMA_BUS_MOD_ATDS_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_DMA_BUS_MOD_ATDS register field value suitable for setting the register. */
#define ALT_EMAC_DMA_BUS_MOD_ATDS_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Programmable Burst Length - pbl
 * 
 * These bits indicate the maximum number of beats to be transferred in one DMA
 * transaction. This is the maximum value that is used in a single block Read or
 * Write. The DMA always attempts to burst as specified in PBL each time it starts
 * a Burst transfer on the host bus. PBL can be programmed with permissible values
 * of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When
 * USP is set high, this PBL value is applicable only for Tx DMA transactions.
 * 
 * If the number of beats to be transferred is more than 32, then perform the
 * following steps:
 * 
 * 1. Set the 8xPBL mode.
 * 
 * 2. Set the PBL.
 * 
 * For example, if the maximum number of beats to be transferred is 64, then first
 * set 8xPBL to 1 and then set PBL to 8. The PBL values have the following
 * limitation: The maximum number of possible beats (PBL) is limited by the size of
 * the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The
 * FIFO has a constraint that the maximum beat supported is half the depth of the
 * FIFO, except when specified.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_PBL_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_PBL_MSB        13
/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_PBL_WIDTH      6
/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_PBL register field value. */
#define ALT_EMAC_DMA_BUS_MOD_PBL_SET_MSK    0x00003f00
/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_PBL register field value. */
#define ALT_EMAC_DMA_BUS_MOD_PBL_CLR_MSK    0xffffc0ff
/* The reset value of the ALT_EMAC_DMA_BUS_MOD_PBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_PBL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_BUS_MOD_PBL field value from a register. */
#define ALT_EMAC_DMA_BUS_MOD_PBL_GET(value) (((value) & 0x00003f00) >> 8)
/* Produces a ALT_EMAC_DMA_BUS_MOD_PBL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_BUS_MOD_PBL_SET(value) (((value) << 8) & 0x00003f00)

/*
 * Field : Fixed Burst - fb
 * 
 * This bit controls whether the AXI Master interface performs fixed burst
 * transfers or not. When set, the AXI interface uses FIXED bursts during the start
 * of the normal burst transfers. When reset, the AXI interface uses SINGLE and
 * INCR burst transfer operations.
 * 
 * For more information, see Bit 0 (UNDEFINED) of the AXI Bus Mode register.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                 
 * :-------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB      | 0x0   | SINGLE or INCR Burst        
 *  ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 | 0x1   | FIXED Burst (1, 4, 8, or 16)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB
 * 
 * SINGLE or INCR Burst
 */
#define ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB         0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB
 * 
 * FIXED Burst (1, 4, 8, or 16)
 */
#define ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
#define ALT_EMAC_DMA_BUS_MOD_FB_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
#define ALT_EMAC_DMA_BUS_MOD_FB_MSB        16
/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
#define ALT_EMAC_DMA_BUS_MOD_FB_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_FB register field value. */
#define ALT_EMAC_DMA_BUS_MOD_FB_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_FB register field value. */
#define ALT_EMAC_DMA_BUS_MOD_FB_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_DMA_BUS_MOD_FB register field. */
#define ALT_EMAC_DMA_BUS_MOD_FB_RESET      0x0
/* Extracts the ALT_EMAC_DMA_BUS_MOD_FB field value from a register. */
#define ALT_EMAC_DMA_BUS_MOD_FB_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_DMA_BUS_MOD_FB register field value suitable for setting the register. */
#define ALT_EMAC_DMA_BUS_MOD_FB_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Rx DMA PBL - rpbl
 * 
 * This field indicates the maximum number of beats to be transferred in one Rx DMA
 * transaction. This is the maximum value that is used in a single block Read or
 * Write.
 * 
 * The Rx DMA always attempts to burst as specified in the RPBL bit each time it
 * starts a Burst transfer on the host bus. You can program RPBL with values of 1,
 * 2, 4, 8, 16, and 32. Any other value results in undefined behavior.
 * 
 * This field is valid and applicable only when USP is set high.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                           
 * :---------------------------------------|:------|:---------------------------------------
 *  ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1  | 0x1   | Beats Trans. in one Rx DMA Transaction
 *  ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2  | 0x2   | Beats Trans. in one Rx DMA Transaction
 *  ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4  | 0x4   | Beats Trans. in one Rx DMA Transaction
 *  ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8  | 0x8   | Beats Trans. in one Rx DMA Transaction
 *  ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6  | 0x10  | Beats Trans. in one Rx DMA Transaction
 *  ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 | 0x20  | Beats Trans. in one Rx DMA Transaction
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
 * 
 * Beats Trans. in one Rx DMA Transaction
 */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1   0x1
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
 * 
 * Beats Trans. in one Rx DMA Transaction
 */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2   0x2
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
 * 
 * Beats Trans. in one Rx DMA Transaction
 */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4   0x4
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
 * 
 * Beats Trans. in one Rx DMA Transaction
 */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8   0x8
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
 * 
 * Beats Trans. in one Rx DMA Transaction
 */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6   0x10
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
 * 
 * Beats Trans. in one Rx DMA Transaction
 */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32  0x20

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_MSB        22
/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_WIDTH      6
/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_RPBL register field value. */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_SET_MSK    0x007e0000
/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_RPBL register field value. */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_CLR_MSK    0xff81ffff
/* The reset value of the ALT_EMAC_DMA_BUS_MOD_RPBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_BUS_MOD_RPBL field value from a register. */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_GET(value) (((value) & 0x007e0000) >> 17)
/* Produces a ALT_EMAC_DMA_BUS_MOD_RPBL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_BUS_MOD_RPBL_SET(value) (((value) << 17) & 0x007e0000)

/*
 * Field : Use Separate PBL - usp
 * 
 * When set high, this bit configures the Rx DMA to use the value configured in
 * Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA
 * operations.
 * 
 * When reset to low, the PBL value in Bits[13:8] is applicable for both DMA
 * engines.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                
 * :--------------------------------|:------|:----------------------------
 *  ALT_EMAC_DMA_BUS_MOD_USP_E_DISD | 0x0   | Configures TX RX DMA to PBL
 *  ALT_EMAC_DMA_BUS_MOD_USP_E_END  | 0x1   | Configures TX DMA to PBL   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP
 * 
 * Configures TX RX DMA to PBL
 */
#define ALT_EMAC_DMA_BUS_MOD_USP_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP
 * 
 * Configures TX DMA to PBL
 */
#define ALT_EMAC_DMA_BUS_MOD_USP_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
#define ALT_EMAC_DMA_BUS_MOD_USP_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
#define ALT_EMAC_DMA_BUS_MOD_USP_MSB        23
/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
#define ALT_EMAC_DMA_BUS_MOD_USP_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_USP register field value. */
#define ALT_EMAC_DMA_BUS_MOD_USP_SET_MSK    0x00800000
/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_USP register field value. */
#define ALT_EMAC_DMA_BUS_MOD_USP_CLR_MSK    0xff7fffff
/* The reset value of the ALT_EMAC_DMA_BUS_MOD_USP register field. */
#define ALT_EMAC_DMA_BUS_MOD_USP_RESET      0x0
/* Extracts the ALT_EMAC_DMA_BUS_MOD_USP field value from a register. */
#define ALT_EMAC_DMA_BUS_MOD_USP_GET(value) (((value) & 0x00800000) >> 23)
/* Produces a ALT_EMAC_DMA_BUS_MOD_USP register field value suitable for setting the register. */
#define ALT_EMAC_DMA_BUS_MOD_USP_SET(value) (((value) << 23) & 0x00800000)

/*
 * Field : 8xPBL Mode - eightxpbl
 * 
 * When set high, this bit multiplies the programmed PBL value (Bits[22:17] and
 * Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64,
 * 128, and 256 beats depending on the PBL value.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description              
 * :--------------------------------------|:------|:--------------------------
 *  ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD | 0x0   | Non Multiply Mode        
 *  ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END  | 0x1   | Multiplies PBL value by 8
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL
 * 
 * Non Multiply Mode
 */
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL
 * 
 * Multiplies PBL value by 8
 */
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_MSB        24
/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value. */
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value. */
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field. */
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_RESET      0x0
/* Extracts the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL field value from a register. */
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Address Aligned Beats - aal
 * 
 * When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface
 * generates all bursts aligned to the start address LS bits. If the FB bit is
 * equal to 0, the first burst (accessing the data buffer's start address) is not
 * aligned, but subsequent bursts are aligned to the address.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                            
 * :--------------------------------|:------|:----------------------------------------
 *  ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD | 0x0   | No Address-Aligned Beats               
 *  ALT_EMAC_DMA_BUS_MOD_AAL_E_END  | 0x1   | Address-Aligned Beats (dependent on FB)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL
 * 
 * No Address-Aligned Beats
 */
#define ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL
 * 
 * Address-Aligned Beats (dependent on FB)
 */
#define ALT_EMAC_DMA_BUS_MOD_AAL_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
#define ALT_EMAC_DMA_BUS_MOD_AAL_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
#define ALT_EMAC_DMA_BUS_MOD_AAL_MSB        25
/* The width in bits of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
#define ALT_EMAC_DMA_BUS_MOD_AAL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_BUS_MOD_AAL register field value. */
#define ALT_EMAC_DMA_BUS_MOD_AAL_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_DMA_BUS_MOD_AAL register field value. */
#define ALT_EMAC_DMA_BUS_MOD_AAL_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_DMA_BUS_MOD_AAL register field. */
#define ALT_EMAC_DMA_BUS_MOD_AAL_RESET      0x0
/* Extracts the ALT_EMAC_DMA_BUS_MOD_AAL field value from a register. */
#define ALT_EMAC_DMA_BUS_MOD_AAL_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_DMA_BUS_MOD_AAL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_BUS_MOD_AAL_SET(value) (((value) << 25) & 0x02000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_BUS_MOD.
 */
struct ALT_EMAC_DMA_BUS_MOD_s
{
    uint32_t  swr       :  1;  /* Software Reset */
    uint32_t            :  1;  /* *UNDEFINED* */
    uint32_t  dsl       :  5;  /* Descriptor Skip Length */
    uint32_t  atds      :  1;  /* Alternate Descriptor Size */
    uint32_t  pbl       :  6;  /* Programmable Burst Length */
    uint32_t            :  2;  /* *UNDEFINED* */
    uint32_t  fb        :  1;  /* Fixed Burst */
    uint32_t  rpbl      :  6;  /* Rx DMA PBL */
    uint32_t  usp       :  1;  /* Use Separate PBL */
    uint32_t  eightxpbl :  1;  /* 8xPBL Mode */
    uint32_t  aal       :  1;  /* Address Aligned Beats */
    uint32_t            :  6;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_DMA_BUS_MOD. */
typedef volatile struct ALT_EMAC_DMA_BUS_MOD_s  ALT_EMAC_DMA_BUS_MOD_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_BUS_MOD register from the beginning of the component. */
#define ALT_EMAC_DMA_BUS_MOD_OFST        0x0
/* The address of the ALT_EMAC_DMA_BUS_MOD register. */
#define ALT_EMAC_DMA_BUS_MOD_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_BUS_MOD_OFST))

/*
 * Register : Register 1 (Transmit Poll Demand Register) - Transmit_Poll_Demand
 * 
 * The Transmit Poll Demand register enables the Tx DMA to check whether or not the
 * DMA owns the current descriptor. The Transmit Poll Demand command is given to
 * wake up the Tx DMA if it is in the Suspend mode. The Tx DMA can go into the
 * Suspend mode because of an Underflow error in a transmitted frame or the
 * unavailability of descriptors owned by it. You can give this command anytime and
 * the Tx DMA resets this command when it again starts fetching the current
 * descriptor from host memory.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description         
 * :-------|:-------|:------|:---------------------
 *  [31:0] | RW     | 0x0   | Transmit Poll Demand
 * 
 */
/*
 * Field : Transmit Poll Demand - tpd
 * 
 * When these bits are written with any value, the DMA reads the current descriptor
 * pointed to by Register 18 (Current Host Transmit Descriptor Register). If that
 * descriptor is not available (owned by the Host), the transmission returns to the
 * Suspend state and the Bit 2 (TU) of Register 5 (Status Register) is asserted. If
 * the descriptor is available, the transmission resumes.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_MSB        31
/* The width in bits of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_WIDTH      32
/* The mask used to set the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value. */
#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value. */
#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field. */
#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_RESET      0x0
/* Extracts the ALT_EMAC_DMA_TX_POLL_DEMAND_TPD field value from a register. */
#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_DMA_TX_POLL_DEMAND_TPD register field value suitable for setting the register. */
#define ALT_EMAC_DMA_TX_POLL_DEMAND_TPD_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_TX_POLL_DEMAND.
 */
struct ALT_EMAC_DMA_TX_POLL_DEMAND_s
{
    uint32_t  tpd : 32;  /* Transmit Poll Demand */
};

/* The typedef declaration for register ALT_EMAC_DMA_TX_POLL_DEMAND. */
typedef volatile struct ALT_EMAC_DMA_TX_POLL_DEMAND_s  ALT_EMAC_DMA_TX_POLL_DEMAND_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_TX_POLL_DEMAND register from the beginning of the component. */
#define ALT_EMAC_DMA_TX_POLL_DEMAND_OFST        0x4
/* The address of the ALT_EMAC_DMA_TX_POLL_DEMAND register. */
#define ALT_EMAC_DMA_TX_POLL_DEMAND_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TX_POLL_DEMAND_OFST))

/*
 * Register : Register 2 (Receive Poll Demand Register) - Receive_Poll_Demand
 * 
 * The Receive Poll Demand register enables the receive DMA to check for new
 * descriptors. This command is used to wake up the Rx DMA from the SUSPEND state.
 * The RxDMA can go into the SUSPEND state only because of the unavailability of
 * descriptors it owns.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description        
 * :-------|:-------|:------|:--------------------
 *  [31:0] | RW     | 0x0   | Receive Poll Demand
 * 
 */
/*
 * Field : Receive Poll Demand - rpd
 * 
 * When these bits are written with any value, the DMA reads the current descriptor
 * pointed to by Register 19 (Current Host Receive Descriptor Register). If that
 * descriptor is not available (owned by the Host), the reception returns to the
 * Suspended state and the Bit 7 (RU) of Register 5 (Status Register) is not
 * asserted. If the descriptor is available, the Rx DMA returns to the active
 * state.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_MSB        31
/* The width in bits of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_WIDTH      32
/* The mask used to set the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value. */
#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value. */
#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field. */
#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_RESET      0x0
/* Extracts the ALT_EMAC_DMA_RX_POLL_DEMAND_RPD field value from a register. */
#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_DMA_RX_POLL_DEMAND_RPD register field value suitable for setting the register. */
#define ALT_EMAC_DMA_RX_POLL_DEMAND_RPD_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_RX_POLL_DEMAND.
 */
struct ALT_EMAC_DMA_RX_POLL_DEMAND_s
{
    uint32_t  rpd : 32;  /* Receive Poll Demand */
};

/* The typedef declaration for register ALT_EMAC_DMA_RX_POLL_DEMAND. */
typedef volatile struct ALT_EMAC_DMA_RX_POLL_DEMAND_s  ALT_EMAC_DMA_RX_POLL_DEMAND_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_RX_POLL_DEMAND register from the beginning of the component. */
#define ALT_EMAC_DMA_RX_POLL_DEMAND_OFST        0x8
/* The address of the ALT_EMAC_DMA_RX_POLL_DEMAND register. */
#define ALT_EMAC_DMA_RX_POLL_DEMAND_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_POLL_DEMAND_OFST))

/*
 * Register : Register 3 (Receive Descriptor List Address Register) - Receive_Descriptor_List_Address
 * 
 * The Receive Descriptor List Address register points to the start of the Receive
 * Descriptor List. The descriptor lists reside in the host's physical memory space
 * and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data
 * bus). The DMA internally converts it to bus width aligned address by making the
 * corresponding LS bits low. Writing to this register is permitted only when
 * reception is stopped. When stopped, this register must be written to before the
 * receive Start command is given.
 * 
 * You can write to this register only when Rx DMA has stopped, that is, Bit 1 (SR)
 * is set to zero in Register 6 (Operation Mode Register). When stopped, this
 * register can be written with a new descriptor list address. When you set the SR
 * bit to 1, the DMA takes the newly programmed descriptor base address.
 * 
 * If this register is not changed when the SR bit is set to 0, then the DMA takes
 * the descriptor address where it was stopped earlier.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description          
 * :-------|:-------|:------|:----------------------
 *  [1:0]  | ???    | 0x0   | *UNDEFINED*          
 *  [31:2] | RW     | 0x0   | Start of Receive List
 * 
 */
/*
 * Field : Start of Receive List - rdesla_32bit
 * 
 * This field contains the base address of the first descriptor in the Receive
 * Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and internally
 * taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO).
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_MSB        31
/* The width in bits of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_WIDTH      30
/* The mask used to set the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value. */
#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_SET_MSK    0xfffffffc
/* The mask used to clear the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value. */
#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_CLR_MSK    0x00000003
/* The reset value of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field. */
#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_RESET      0x0
/* Extracts the ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT field value from a register. */
#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2)
/* Produces a ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_RDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_RX_DESC_LIST_ADDR.
 */
struct ALT_EMAC_DMA_RX_DESC_LIST_ADDR_s
{
    uint32_t               :  2;  /* *UNDEFINED* */
    uint32_t  rdesla_32bit : 30;  /* Start of Receive List */
};

/* The typedef declaration for register ALT_EMAC_DMA_RX_DESC_LIST_ADDR. */
typedef volatile struct ALT_EMAC_DMA_RX_DESC_LIST_ADDR_s  ALT_EMAC_DMA_RX_DESC_LIST_ADDR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register from the beginning of the component. */
#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_OFST        0xc
/* The address of the ALT_EMAC_DMA_RX_DESC_LIST_ADDR register. */
#define ALT_EMAC_DMA_RX_DESC_LIST_ADDR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_DESC_LIST_ADDR_OFST))

/*
 * Register : Register 4 (Transmit Descriptor List Address Register) - Transmit_Descriptor_List_Address
 * 
 * The Transmit Descriptor List Address register points to the start of the
 * Transmit Descriptor List. The descriptor lists reside in the host's physical
 * memory space and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or
 * 128-bit data bus). The DMA internally converts it to bus width aligned address
 * by making the corresponding LSB to low.
 * 
 * You can write to this register only when the Tx DMA has stopped, that is, Bit 13
 * (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this
 * register can be written with a new descriptor list address. When you set the ST
 * bit to 1, the DMA takes the newly programmed descriptor base address.
 * 
 * If this register is not changed when the ST bit is set to 0, then the DMA takes
 * the descriptor address where it was stopped earlier.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description           
 * :-------|:-------|:------|:-----------------------
 *  [1:0]  | ???    | 0x0   | *UNDEFINED*           
 *  [31:2] | RW     | 0x0   | Start of Transmit List
 * 
 */
/*
 * Field : Start of Transmit List - tdesla_32bit
 * 
 * This field contains the base address of the first descriptor in the Transmit
 * Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and are
 * internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only
 * (RO).
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_MSB        31
/* The width in bits of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_WIDTH      30
/* The mask used to set the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value. */
#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_SET_MSK    0xfffffffc
/* The mask used to clear the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value. */
#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_CLR_MSK    0x00000003
/* The reset value of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field. */
#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_RESET      0x0
/* Extracts the ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT field value from a register. */
#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_GET(value) (((value) & 0xfffffffc) >> 2)
/* Produces a ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_TDESLA_32BIT_SET(value) (((value) << 2) & 0xfffffffc)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_TX_DESC_LIST_ADDR.
 */
struct ALT_EMAC_DMA_TX_DESC_LIST_ADDR_s
{
    uint32_t               :  2;  /* *UNDEFINED* */
    uint32_t  tdesla_32bit : 30;  /* Start of Transmit List */
};

/* The typedef declaration for register ALT_EMAC_DMA_TX_DESC_LIST_ADDR. */
typedef volatile struct ALT_EMAC_DMA_TX_DESC_LIST_ADDR_s  ALT_EMAC_DMA_TX_DESC_LIST_ADDR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register from the beginning of the component. */
#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_OFST        0x10
/* The address of the ALT_EMAC_DMA_TX_DESC_LIST_ADDR register. */
#define ALT_EMAC_DMA_TX_DESC_LIST_ADDR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_TX_DESC_LIST_ADDR_OFST))

/*
 * Register : Register 5 (Status Register) - Status
 * 
 * The Status register contains all status bits that the DMA reports to the host.
 * The software driver reads this register during an interrupt service routine or
 * polling. Most of the fields in this register cause the host to be interrupted.
 * The bits of this register are not cleared when read. Writing 1'b1 to
 * (unreserved) Bits[16:0] of this register clears these bits and writing 1'b0 has
 * no effect. Each field (Bits[16:0]) can be masked by masking the appropriate bit
 * in Register 7 (Interrupt Enable Register).
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                       
 * :--------|:-------|:------|:-----------------------------------
 *  [0]     | RW     | 0x0   | Transmit Interrupt                
 *  [1]     | RW     | 0x0   | Transmit Process Stopped          
 *  [2]     | RW     | 0x0   | Transmit Buffer Unavailable       
 *  [3]     | RW     | 0x0   | Transmit Jabber Timeout           
 *  [4]     | RW     | 0x0   | Receive Overflow                  
 *  [5]     | RW     | 0x0   | Transmit Underflow                
 *  [6]     | RW     | 0x0   | Receive Interrupt                 
 *  [7]     | RW     | 0x0   | Receive Buffer Unavailable        
 *  [8]     | RW     | 0x0   | Receive Process Stopped           
 *  [9]     | RW     | 0x0   | Receive Watchdog Timeout          
 *  [10]    | RW     | 0x0   | Early Transmit Interrupt          
 *  [12:11] | ???    | 0x0   | *UNDEFINED*                       
 *  [13]    | RW     | 0x0   | Fatal Bus Error Interrupt         
 *  [14]    | RW     | 0x0   | Early Receive Interrupt           
 *  [15]    | RW     | 0x0   | Abnormal Interrupt Summary        
 *  [16]    | RW     | 0x0   | Normal Interrupt Summary          
 *  [19:17] | R      | 0x0   | Received Process State            
 *  [22:20] | R      | 0x0   | Transmit Process State            
 *  [25:23] | R      | 0x0   | Error Bits                        
 *  [26]    | R      | 0x0   | GMAC Line Interface Interrupt     
 *  [27]    | R      | 0x0   | GMAC MMC Interrupt                
 *  [28]    | ???    | 0x0   | *UNDEFINED*                       
 *  [29]    | R      | 0x0   | Timestamp Trigger Interrupt       
 *  [30]    | R      | 0x0   | GMAC LPI Interrupt (for Channel 0)
 *  [31]    | ???    | 0x0   | *UNDEFINED*                       
 * 
 */
/*
 * Field : Transmit Interrupt - ti
 * 
 * This bit indicates that the frame transmission is complete. When transmission is
 * complete, the Bit 31 (Interrupt on Completion) of TDES1 is reset in the first
 * descriptor, and the specific frame status information is updated in the
 * descriptor.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TI register field. */
#define ALT_EMAC_DMA_STAT_TI_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TI register field. */
#define ALT_EMAC_DMA_STAT_TI_MSB        0
/* The width in bits of the ALT_EMAC_DMA_STAT_TI register field. */
#define ALT_EMAC_DMA_STAT_TI_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_TI register field value. */
#define ALT_EMAC_DMA_STAT_TI_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_DMA_STAT_TI register field value. */
#define ALT_EMAC_DMA_STAT_TI_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_DMA_STAT_TI register field. */
#define ALT_EMAC_DMA_STAT_TI_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_TI field value from a register. */
#define ALT_EMAC_DMA_STAT_TI_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_DMA_STAT_TI register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_TI_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Transmit Process Stopped - tps
 * 
 * This bit is set when the transmission is stopped.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TPS register field. */
#define ALT_EMAC_DMA_STAT_TPS_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TPS register field. */
#define ALT_EMAC_DMA_STAT_TPS_MSB        1
/* The width in bits of the ALT_EMAC_DMA_STAT_TPS register field. */
#define ALT_EMAC_DMA_STAT_TPS_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_TPS register field value. */
#define ALT_EMAC_DMA_STAT_TPS_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_DMA_STAT_TPS register field value. */
#define ALT_EMAC_DMA_STAT_TPS_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_DMA_STAT_TPS register field. */
#define ALT_EMAC_DMA_STAT_TPS_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_TPS field value from a register. */
#define ALT_EMAC_DMA_STAT_TPS_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_DMA_STAT_TPS register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_TPS_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Transmit Buffer Unavailable - tu
 * 
 * This bit indicates that the host owns the Next Descriptor in the Transmit List
 * and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain
 * the Transmit Process state transitions.
 * 
 * To resume processing Transmit descriptors, the host should change the ownership
 * of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand
 * command.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TU register field. */
#define ALT_EMAC_DMA_STAT_TU_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TU register field. */
#define ALT_EMAC_DMA_STAT_TU_MSB        2
/* The width in bits of the ALT_EMAC_DMA_STAT_TU register field. */
#define ALT_EMAC_DMA_STAT_TU_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_TU register field value. */
#define ALT_EMAC_DMA_STAT_TU_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_DMA_STAT_TU register field value. */
#define ALT_EMAC_DMA_STAT_TU_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_DMA_STAT_TU register field. */
#define ALT_EMAC_DMA_STAT_TU_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_TU field value from a register. */
#define ALT_EMAC_DMA_STAT_TU_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_DMA_STAT_TU register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_TU_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Transmit Jabber Timeout - tjt
 * 
 * This bit indicates that the Transmit Jabber Timer expired, which happens when
 * the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled).
 * When the Jabber Timeout occurs, the transmission process is aborted and placed
 * in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to
 * assert.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TJT register field. */
#define ALT_EMAC_DMA_STAT_TJT_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TJT register field. */
#define ALT_EMAC_DMA_STAT_TJT_MSB        3
/* The width in bits of the ALT_EMAC_DMA_STAT_TJT register field. */
#define ALT_EMAC_DMA_STAT_TJT_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_TJT register field value. */
#define ALT_EMAC_DMA_STAT_TJT_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_DMA_STAT_TJT register field value. */
#define ALT_EMAC_DMA_STAT_TJT_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_DMA_STAT_TJT register field. */
#define ALT_EMAC_DMA_STAT_TJT_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_TJT field value from a register. */
#define ALT_EMAC_DMA_STAT_TJT_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_DMA_STAT_TJT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_TJT_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Receive Overflow - ovf
 * 
 * This bit indicates that the Receive Buffer had an Overflow during frame
 * reception. If the partial frame is transferred to the application, the overflow
 * status is set in RDES0[11].
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_OVF register field. */
#define ALT_EMAC_DMA_STAT_OVF_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_OVF register field. */
#define ALT_EMAC_DMA_STAT_OVF_MSB        4
/* The width in bits of the ALT_EMAC_DMA_STAT_OVF register field. */
#define ALT_EMAC_DMA_STAT_OVF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_OVF register field value. */
#define ALT_EMAC_DMA_STAT_OVF_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_DMA_STAT_OVF register field value. */
#define ALT_EMAC_DMA_STAT_OVF_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_DMA_STAT_OVF register field. */
#define ALT_EMAC_DMA_STAT_OVF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_OVF field value from a register. */
#define ALT_EMAC_DMA_STAT_OVF_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_DMA_STAT_OVF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_OVF_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Transmit Underflow - unf
 * 
 * This bit indicates that the Transmit Buffer had an Underflow during frame
 * transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_UNF register field. */
#define ALT_EMAC_DMA_STAT_UNF_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_UNF register field. */
#define ALT_EMAC_DMA_STAT_UNF_MSB        5
/* The width in bits of the ALT_EMAC_DMA_STAT_UNF register field. */
#define ALT_EMAC_DMA_STAT_UNF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_UNF register field value. */
#define ALT_EMAC_DMA_STAT_UNF_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_DMA_STAT_UNF register field value. */
#define ALT_EMAC_DMA_STAT_UNF_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_DMA_STAT_UNF register field. */
#define ALT_EMAC_DMA_STAT_UNF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_UNF field value from a register. */
#define ALT_EMAC_DMA_STAT_UNF_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_DMA_STAT_UNF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_UNF_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Receive Interrupt - ri
 * 
 * This bit indicates that the frame reception is complete. When reception is
 * complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the
 * last Descriptor, and the specific frame status information is updated in the
 * descriptor.
 * 
 * The reception remains in the Running state.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RI register field. */
#define ALT_EMAC_DMA_STAT_RI_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RI register field. */
#define ALT_EMAC_DMA_STAT_RI_MSB        6
/* The width in bits of the ALT_EMAC_DMA_STAT_RI register field. */
#define ALT_EMAC_DMA_STAT_RI_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_RI register field value. */
#define ALT_EMAC_DMA_STAT_RI_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_DMA_STAT_RI register field value. */
#define ALT_EMAC_DMA_STAT_RI_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_DMA_STAT_RI register field. */
#define ALT_EMAC_DMA_STAT_RI_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_RI field value from a register. */
#define ALT_EMAC_DMA_STAT_RI_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_DMA_STAT_RI register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_RI_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Receive Buffer Unavailable - ru
 * 
 * This bit indicates that the host owns the Next Descriptor in the Receive List
 * and the DMA cannot acquire it. The Receive Process is suspended. To resume
 * processing Receive descriptors, the host should change the ownership of the
 * descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is
 * issued, the Receive Process resumes when the next recognized incoming frame is
 * received. This bit is set only when the previous Receive Descriptor is owned by
 * the DMA.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RU register field. */
#define ALT_EMAC_DMA_STAT_RU_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RU register field. */
#define ALT_EMAC_DMA_STAT_RU_MSB        7
/* The width in bits of the ALT_EMAC_DMA_STAT_RU register field. */
#define ALT_EMAC_DMA_STAT_RU_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_RU register field value. */
#define ALT_EMAC_DMA_STAT_RU_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_DMA_STAT_RU register field value. */
#define ALT_EMAC_DMA_STAT_RU_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_DMA_STAT_RU register field. */
#define ALT_EMAC_DMA_STAT_RU_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_RU field value from a register. */
#define ALT_EMAC_DMA_STAT_RU_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_DMA_STAT_RU register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_RU_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Receive Process Stopped - rps
 * 
 * This bit is asserted when the Receive Process enters the Stopped state.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RPS register field. */
#define ALT_EMAC_DMA_STAT_RPS_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RPS register field. */
#define ALT_EMAC_DMA_STAT_RPS_MSB        8
/* The width in bits of the ALT_EMAC_DMA_STAT_RPS register field. */
#define ALT_EMAC_DMA_STAT_RPS_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_RPS register field value. */
#define ALT_EMAC_DMA_STAT_RPS_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_DMA_STAT_RPS register field value. */
#define ALT_EMAC_DMA_STAT_RPS_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_DMA_STAT_RPS register field. */
#define ALT_EMAC_DMA_STAT_RPS_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_RPS field value from a register. */
#define ALT_EMAC_DMA_STAT_RPS_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_DMA_STAT_RPS register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_RPS_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Receive Watchdog Timeout - rwt
 * 
 * This bit is asserted when a frame with length greater than 2,048 bytes is
 * received (10, 240 when Jumbo Frame mode is enabled).
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RWT register field. */
#define ALT_EMAC_DMA_STAT_RWT_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RWT register field. */
#define ALT_EMAC_DMA_STAT_RWT_MSB        9
/* The width in bits of the ALT_EMAC_DMA_STAT_RWT register field. */
#define ALT_EMAC_DMA_STAT_RWT_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_RWT register field value. */
#define ALT_EMAC_DMA_STAT_RWT_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_DMA_STAT_RWT register field value. */
#define ALT_EMAC_DMA_STAT_RWT_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_DMA_STAT_RWT register field. */
#define ALT_EMAC_DMA_STAT_RWT_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_RWT field value from a register. */
#define ALT_EMAC_DMA_STAT_RWT_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_DMA_STAT_RWT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_RWT_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Early Transmit Interrupt - eti
 * 
 * This bit indicates that the frame to be transmitted is fully transferred to the
 * MTL Transmit FIFO.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_ETI register field. */
#define ALT_EMAC_DMA_STAT_ETI_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_ETI register field. */
#define ALT_EMAC_DMA_STAT_ETI_MSB        10
/* The width in bits of the ALT_EMAC_DMA_STAT_ETI register field. */
#define ALT_EMAC_DMA_STAT_ETI_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_ETI register field value. */
#define ALT_EMAC_DMA_STAT_ETI_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_DMA_STAT_ETI register field value. */
#define ALT_EMAC_DMA_STAT_ETI_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_DMA_STAT_ETI register field. */
#define ALT_EMAC_DMA_STAT_ETI_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_ETI field value from a register. */
#define ALT_EMAC_DMA_STAT_ETI_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_DMA_STAT_ETI register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_ETI_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : Fatal Bus Error Interrupt - fbi
 * 
 * This bit indicates that a bus error occurred, as described in Bits[25:23]. When
 * this bit is set, the corresponding DMA engine disables all of its bus accesses.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_FBI register field. */
#define ALT_EMAC_DMA_STAT_FBI_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_FBI register field. */
#define ALT_EMAC_DMA_STAT_FBI_MSB        13
/* The width in bits of the ALT_EMAC_DMA_STAT_FBI register field. */
#define ALT_EMAC_DMA_STAT_FBI_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_FBI register field value. */
#define ALT_EMAC_DMA_STAT_FBI_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_DMA_STAT_FBI register field value. */
#define ALT_EMAC_DMA_STAT_FBI_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_DMA_STAT_FBI register field. */
#define ALT_EMAC_DMA_STAT_FBI_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_FBI field value from a register. */
#define ALT_EMAC_DMA_STAT_FBI_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_DMA_STAT_FBI register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_FBI_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : Early Receive Interrupt - eri
 * 
 * This bit indicates that the DMA had filled the first data buffer of the packet.
 * Bit 6 (RI) of this register automatically clears this bit.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_ERI register field. */
#define ALT_EMAC_DMA_STAT_ERI_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_ERI register field. */
#define ALT_EMAC_DMA_STAT_ERI_MSB        14
/* The width in bits of the ALT_EMAC_DMA_STAT_ERI register field. */
#define ALT_EMAC_DMA_STAT_ERI_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_ERI register field value. */
#define ALT_EMAC_DMA_STAT_ERI_SET_MSK    0x00004000
/* The mask used to clear the ALT_EMAC_DMA_STAT_ERI register field value. */
#define ALT_EMAC_DMA_STAT_ERI_CLR_MSK    0xffffbfff
/* The reset value of the ALT_EMAC_DMA_STAT_ERI register field. */
#define ALT_EMAC_DMA_STAT_ERI_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_ERI field value from a register. */
#define ALT_EMAC_DMA_STAT_ERI_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_EMAC_DMA_STAT_ERI register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_ERI_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : Abnormal Interrupt Summary - ais
 * 
 * Abnormal Interrupt Summary bit value is the logical OR of the following when the
 * corresponding interrupt bits are enabled in Register 7 (Interrupt Enable
 * Register):
 * 
 * * Register 5[1]: Transmit Process Stopped
 * 
 * * Register 5[3]: Transmit Jabber Timeout
 * 
 * * Register 5[4]: Receive FIFO Overflow
 * 
 * * Register 5[5]: Transmit Underflow
 * 
 * * Register 5[7]: Receive Buffer Unavailable
 * 
 * * Register 5[8]: Receive Process Stopped
 * 
 * * Register 5[9]: Receive Watchdog Timeout
 * 
 * * Register 5[10]: Early Transmit Interrupt
 * 
 * * Register 5[13]: Fatal Bus Error
 * 
 * Only unmasked bits affect the Abnormal Interrupt Summary bit.
 * 
 * This is a sticky bit and must be cleared each time a corresponding bit, which
 * causes AIS to be set, is cleared.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_AIS register field. */
#define ALT_EMAC_DMA_STAT_AIS_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_AIS register field. */
#define ALT_EMAC_DMA_STAT_AIS_MSB        15
/* The width in bits of the ALT_EMAC_DMA_STAT_AIS register field. */
#define ALT_EMAC_DMA_STAT_AIS_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_AIS register field value. */
#define ALT_EMAC_DMA_STAT_AIS_SET_MSK    0x00008000
/* The mask used to clear the ALT_EMAC_DMA_STAT_AIS register field value. */
#define ALT_EMAC_DMA_STAT_AIS_CLR_MSK    0xffff7fff
/* The reset value of the ALT_EMAC_DMA_STAT_AIS register field. */
#define ALT_EMAC_DMA_STAT_AIS_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_AIS field value from a register. */
#define ALT_EMAC_DMA_STAT_AIS_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_EMAC_DMA_STAT_AIS register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_AIS_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Normal Interrupt Summary - nis
 * 
 * Normal Interrupt Summary bit value is the logical OR of the following when the
 * corresponding interrupt bits are enabled in Register 7 (Interrupt Enable
 * Register):
 * 
 * * Register 5[0]: Transmit Interrupt
 * 
 * * Register 5[2]: Transmit Buffer Unavailable
 * 
 * * Register 5[6]: Receive Interrupt
 * 
 * * Register 5[14]: Early Receive Interrupt
 * 
 * Only unmasked bits (interrupts for which interrupt enable is set in Register 7)
 * affect the Normal Interrupt Summary bit.
 * 
 * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a
 * corresponding bit, which causes NIS to be set, is cleared.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_NIS register field. */
#define ALT_EMAC_DMA_STAT_NIS_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_NIS register field. */
#define ALT_EMAC_DMA_STAT_NIS_MSB        16
/* The width in bits of the ALT_EMAC_DMA_STAT_NIS register field. */
#define ALT_EMAC_DMA_STAT_NIS_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_NIS register field value. */
#define ALT_EMAC_DMA_STAT_NIS_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_DMA_STAT_NIS register field value. */
#define ALT_EMAC_DMA_STAT_NIS_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_DMA_STAT_NIS register field. */
#define ALT_EMAC_DMA_STAT_NIS_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_NIS field value from a register. */
#define ALT_EMAC_DMA_STAT_NIS_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_DMA_STAT_NIS register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_NIS_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Received Process State - rs
 * 
 * This field indicates the Receive DMA FSM state. This field does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                     
 * :--------------------------------|:------|:-------------------------------------------------
 *  ALT_EMAC_DMA_STAT_RS_E_STOPPED  | 0x0   | Stopped Reset or Stop Receive Command issued    
 *  ALT_EMAC_DMA_STAT_RS_E_RUNFETCH | 0x1   | Running: Fetching Receive Transfer Descriptor   
 *  ALT_EMAC_DMA_STAT_RS_E_RESERVE  | 0x2   | Reserved for future use                         
 *  ALT_EMAC_DMA_STAT_RS_E_RUNWAIT  | 0x3   | Running: Waiting for receive packet             
 *  ALT_EMAC_DMA_STAT_RS_E_SUSPEND  | 0x4   | Suspended: Receive Descriptor Unavailable       
 *  ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE | 0x5   | Running: Closing Receive Descriptor             
 *  ALT_EMAC_DMA_STAT_RS_E_TIMESTMP | 0x6   | TIME_STAMP write state                          
 *  ALT_EMAC_DMA_STAT_RS_E_RUNTRANS | 0x7   | Transferring rcv packet data from receive buffer
 * :                                |       | to host memory                                  
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
 * 
 * Stopped Reset or Stop Receive Command issued
 */
#define ALT_EMAC_DMA_STAT_RS_E_STOPPED  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
 * 
 * Running: Fetching Receive Transfer Descriptor
 */
#define ALT_EMAC_DMA_STAT_RS_E_RUNFETCH 0x1
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
 * 
 * Reserved for future use
 */
#define ALT_EMAC_DMA_STAT_RS_E_RESERVE  0x2
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
 * 
 * Running: Waiting for receive packet
 */
#define ALT_EMAC_DMA_STAT_RS_E_RUNWAIT  0x3
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
 * 
 * Suspended: Receive Descriptor Unavailable
 */
#define ALT_EMAC_DMA_STAT_RS_E_SUSPEND  0x4
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
 * 
 * Running: Closing Receive Descriptor
 */
#define ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE 0x5
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
 * 
 * TIME_STAMP write state
 */
#define ALT_EMAC_DMA_STAT_RS_E_TIMESTMP 0x6
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_RS
 * 
 * Transferring rcv packet data from receive buffer to host memory
 */
#define ALT_EMAC_DMA_STAT_RS_E_RUNTRANS 0x7

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RS register field. */
#define ALT_EMAC_DMA_STAT_RS_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RS register field. */
#define ALT_EMAC_DMA_STAT_RS_MSB        19
/* The width in bits of the ALT_EMAC_DMA_STAT_RS register field. */
#define ALT_EMAC_DMA_STAT_RS_WIDTH      3
/* The mask used to set the ALT_EMAC_DMA_STAT_RS register field value. */
#define ALT_EMAC_DMA_STAT_RS_SET_MSK    0x000e0000
/* The mask used to clear the ALT_EMAC_DMA_STAT_RS register field value. */
#define ALT_EMAC_DMA_STAT_RS_CLR_MSK    0xfff1ffff
/* The reset value of the ALT_EMAC_DMA_STAT_RS register field. */
#define ALT_EMAC_DMA_STAT_RS_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_RS field value from a register. */
#define ALT_EMAC_DMA_STAT_RS_GET(value) (((value) & 0x000e0000) >> 17)
/* Produces a ALT_EMAC_DMA_STAT_RS register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_RS_SET(value) (((value) << 17) & 0x000e0000)

/*
 * Field : Transmit Process State - ts
 * 
 * This field indicates the Transmit DMA FSM state. This field does not generate an
 * interrupt.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                            | Value | Description                                  
 * :--------------------------------|:------|:----------------------------------------------
 *  ALT_EMAC_DMA_STAT_TS_E_STOPPED  | 0x0   | Stopped Reset or Stop Transmit Command       
 *  ALT_EMAC_DMA_STAT_TS_E_RUNFETCH | 0x1   | Running: Fetching Tranmit Transfer Descriptor
 *  ALT_EMAC_DMA_STAT_TS_E_RUNWAIT  | 0x2   | Running; Waiting for status                  
 *  ALT_EMAC_DMA_STAT_TS_E_RUNRD    | 0x3   | Running; Reading Data host memory buffer and 
 * :                                |       | queuing it to transmit buffer (Tx FIFO)      
 *  ALT_EMAC_DMA_STAT_TS_E_TIMESTMP | 0x4   | TIME_STAMP write state                       
 *  ALT_EMAC_DMA_STAT_TS_E_RESERVE  | 0x5   | Reserved for future use                      
 *  ALT_EMAC_DMA_STAT_TS_E_SUSPTX   | 0x6   | Suspended; Transmit Descriptor Unavailable or
 * :                                |       | Transmit Buffer Underflow                    
 *  ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE | 0x7   | Running; Closing Transmit Descriptor         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
 * 
 * Stopped Reset or Stop Transmit Command
 */
#define ALT_EMAC_DMA_STAT_TS_E_STOPPED  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
 * 
 * Running: Fetching Tranmit Transfer Descriptor
 */
#define ALT_EMAC_DMA_STAT_TS_E_RUNFETCH 0x1
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
 * 
 * Running; Waiting for status
 */
#define ALT_EMAC_DMA_STAT_TS_E_RUNWAIT  0x2
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
 * 
 * Running; Reading Data host memory buffer and queuing it to transmit buffer (Tx
 * FIFO)
 */
#define ALT_EMAC_DMA_STAT_TS_E_RUNRD    0x3
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
 * 
 * TIME_STAMP write state
 */
#define ALT_EMAC_DMA_STAT_TS_E_TIMESTMP 0x4
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
 * 
 * Reserved for future use
 */
#define ALT_EMAC_DMA_STAT_TS_E_RESERVE  0x5
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
 * 
 * Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow
 */
#define ALT_EMAC_DMA_STAT_TS_E_SUSPTX   0x6
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_TS
 * 
 * Running; Closing Transmit Descriptor
 */
#define ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE 0x7

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TS register field. */
#define ALT_EMAC_DMA_STAT_TS_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TS register field. */
#define ALT_EMAC_DMA_STAT_TS_MSB        22
/* The width in bits of the ALT_EMAC_DMA_STAT_TS register field. */
#define ALT_EMAC_DMA_STAT_TS_WIDTH      3
/* The mask used to set the ALT_EMAC_DMA_STAT_TS register field value. */
#define ALT_EMAC_DMA_STAT_TS_SET_MSK    0x00700000
/* The mask used to clear the ALT_EMAC_DMA_STAT_TS register field value. */
#define ALT_EMAC_DMA_STAT_TS_CLR_MSK    0xff8fffff
/* The reset value of the ALT_EMAC_DMA_STAT_TS register field. */
#define ALT_EMAC_DMA_STAT_TS_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_TS field value from a register. */
#define ALT_EMAC_DMA_STAT_TS_GET(value) (((value) & 0x00700000) >> 20)
/* Produces a ALT_EMAC_DMA_STAT_TS register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_TS_SET(value) (((value) << 20) & 0x00700000)

/*
 * Field : Error Bits - eb
 * 
 * This field indicates the type of error that caused a Bus Error, for example,
 * error response on the AHB or AXI interface. This field is valid only when Bit 13
 * (FBI) is set. This field does not generate an interrupt.
 * 
 * * Bit 23
 * 
 *     - 1'b1: Error during data transfer by the Tx DMA
 * 
 *     - 1'b0: Error during data transfer by the Rx DMA
 * 
 * * Bit 24
 * 
 *     - 1'b1: Error during read transfer
 * 
 *     - 1'b0: Error during write transfer
 * 
 * * Bit 25
 * 
 *     - 1'b1: Error during descriptor access
 * 
 *     - 1'b0: Error during data buffer access
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_EB register field. */
#define ALT_EMAC_DMA_STAT_EB_LSB        23
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_EB register field. */
#define ALT_EMAC_DMA_STAT_EB_MSB        25
/* The width in bits of the ALT_EMAC_DMA_STAT_EB register field. */
#define ALT_EMAC_DMA_STAT_EB_WIDTH      3
/* The mask used to set the ALT_EMAC_DMA_STAT_EB register field value. */
#define ALT_EMAC_DMA_STAT_EB_SET_MSK    0x03800000
/* The mask used to clear the ALT_EMAC_DMA_STAT_EB register field value. */
#define ALT_EMAC_DMA_STAT_EB_CLR_MSK    0xfc7fffff
/* The reset value of the ALT_EMAC_DMA_STAT_EB register field. */
#define ALT_EMAC_DMA_STAT_EB_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_EB field value from a register. */
#define ALT_EMAC_DMA_STAT_EB_GET(value) (((value) & 0x03800000) >> 23)
/* Produces a ALT_EMAC_DMA_STAT_EB register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_EB_SET(value) (((value) << 23) & 0x03800000)

/*
 * Field : GMAC Line Interface Interrupt - gli
 * 
 * This bit reflects an interrupt event in the PCS (link change and AN complete),
 * SMII (link change), or RGMII (link change) interface block of the EMAC. The
 * software must read the corresponding registers (Register 49 for PCS or Register
 * 54 for SMII or RGMII) in the EMAC to get the exact cause of the interrupt and
 * clear the source of interrupt to make this bit as 1'b0. The interrupt signal
 * from the EMAC subsystem (sbd_intr_o) is high when this bit is high.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description        
 * :-----------------------------------|:------|:--------------------
 *  ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP | 0x0   | No Interrupt       
 *  ALT_EMAC_DMA_STAT_GLI_E_INTERRUP   | 0x1   | GMAC Line Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_GLI
 * 
 * No Interrupt
 */
#define ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_GLI
 * 
 * GMAC Line Interrupt
 */
#define ALT_EMAC_DMA_STAT_GLI_E_INTERRUP    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GLI register field. */
#define ALT_EMAC_DMA_STAT_GLI_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GLI register field. */
#define ALT_EMAC_DMA_STAT_GLI_MSB        26
/* The width in bits of the ALT_EMAC_DMA_STAT_GLI register field. */
#define ALT_EMAC_DMA_STAT_GLI_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_GLI register field value. */
#define ALT_EMAC_DMA_STAT_GLI_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_DMA_STAT_GLI register field value. */
#define ALT_EMAC_DMA_STAT_GLI_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_DMA_STAT_GLI register field. */
#define ALT_EMAC_DMA_STAT_GLI_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_GLI field value from a register. */
#define ALT_EMAC_DMA_STAT_GLI_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_DMA_STAT_GLI register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_GLI_SET(value) (((value) << 26) & 0x04000000)

/*
 * Field : GMAC MMC Interrupt - gmi
 * 
 * This bit reflects an interrupt event in the MMC block of the EMAC. The software
 * must read the corresponding registers in the EMAC to get the exact cause of
 * interrupt and clear the source of interrupt to make this bit as 1'b0. The
 * interrupt signal from the EMAC subsystem (sbd_intr_o) is high when this bit is
 * high.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description       
 * :-----------------------------------|:------|:-------------------
 *  ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP | 0x0   | No Interrupt      
 *  ALT_EMAC_DMA_STAT_GMI_E_INTERRUP   | 0x1   | GMAC MMC Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_GMI
 * 
 * No Interrupt
 */
#define ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_GMI
 * 
 * GMAC MMC Interrupt
 */
#define ALT_EMAC_DMA_STAT_GMI_E_INTERRUP    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GMI register field. */
#define ALT_EMAC_DMA_STAT_GMI_LSB        27
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GMI register field. */
#define ALT_EMAC_DMA_STAT_GMI_MSB        27
/* The width in bits of the ALT_EMAC_DMA_STAT_GMI register field. */
#define ALT_EMAC_DMA_STAT_GMI_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_GMI register field value. */
#define ALT_EMAC_DMA_STAT_GMI_SET_MSK    0x08000000
/* The mask used to clear the ALT_EMAC_DMA_STAT_GMI register field value. */
#define ALT_EMAC_DMA_STAT_GMI_CLR_MSK    0xf7ffffff
/* The reset value of the ALT_EMAC_DMA_STAT_GMI register field. */
#define ALT_EMAC_DMA_STAT_GMI_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_GMI field value from a register. */
#define ALT_EMAC_DMA_STAT_GMI_GET(value) (((value) & 0x08000000) >> 27)
/* Produces a ALT_EMAC_DMA_STAT_GMI register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_GMI_SET(value) (((value) << 27) & 0x08000000)

/*
 * Field : Timestamp Trigger Interrupt - tti
 * 
 * This bit indicates an interrupt event in the Timestamp Generator block of EMAC.
 * The software must read the corresponding registers in the EMAC to get the exact
 * cause of interrupt and clear its source to reset this bit to 1'b0. When this bit
 * is high, the interrupt signal from the EMAC subsystem (sbd_intr_o) is high.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                               | Value | Description                
 * :-----------------------------------|:------|:----------------------------
 *  ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP | 0x0   | No Interrupt               
 *  ALT_EMAC_DMA_STAT_TTI_E_INTERRUP   | 0x1   | Timestamp Trigger Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_TTI
 * 
 * No Interrupt
 */
#define ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_TTI
 * 
 * Timestamp Trigger Interrupt
 */
#define ALT_EMAC_DMA_STAT_TTI_E_INTERRUP    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TTI register field. */
#define ALT_EMAC_DMA_STAT_TTI_LSB        29
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TTI register field. */
#define ALT_EMAC_DMA_STAT_TTI_MSB        29
/* The width in bits of the ALT_EMAC_DMA_STAT_TTI register field. */
#define ALT_EMAC_DMA_STAT_TTI_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_TTI register field value. */
#define ALT_EMAC_DMA_STAT_TTI_SET_MSK    0x20000000
/* The mask used to clear the ALT_EMAC_DMA_STAT_TTI register field value. */
#define ALT_EMAC_DMA_STAT_TTI_CLR_MSK    0xdfffffff
/* The reset value of the ALT_EMAC_DMA_STAT_TTI register field. */
#define ALT_EMAC_DMA_STAT_TTI_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_TTI field value from a register. */
#define ALT_EMAC_DMA_STAT_TTI_GET(value) (((value) & 0x20000000) >> 29)
/* Produces a ALT_EMAC_DMA_STAT_TTI register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_TTI_SET(value) (((value) << 29) & 0x20000000)

/*
 * Field : GMAC LPI Interrupt (for Channel 0) - glpii
 * 
 * This bit indicates an interrupt event in the LPI logic of the EMAC. To reset
 * this bit to 1'b0, the software must read the corresponding registers in the EMAC
 * to get the exact cause of the interrupt and clear its source.
 * 
 * When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description       
 * :-------------------------------------|:------|:-------------------
 *  ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP | 0x0   | No Interrupt      
 *  ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP   | 0x1   | GMAC LPI Interrupt
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_GLPII
 * 
 * No Interrupt
 */
#define ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP    0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_STAT_GLPII
 * 
 * GMAC LPI Interrupt
 */
#define ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP      0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GLPII register field. */
#define ALT_EMAC_DMA_STAT_GLPII_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GLPII register field. */
#define ALT_EMAC_DMA_STAT_GLPII_MSB        30
/* The width in bits of the ALT_EMAC_DMA_STAT_GLPII register field. */
#define ALT_EMAC_DMA_STAT_GLPII_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_STAT_GLPII register field value. */
#define ALT_EMAC_DMA_STAT_GLPII_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_DMA_STAT_GLPII register field value. */
#define ALT_EMAC_DMA_STAT_GLPII_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_DMA_STAT_GLPII register field. */
#define ALT_EMAC_DMA_STAT_GLPII_RESET      0x0
/* Extracts the ALT_EMAC_DMA_STAT_GLPII field value from a register. */
#define ALT_EMAC_DMA_STAT_GLPII_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_DMA_STAT_GLPII register field value suitable for setting the register. */
#define ALT_EMAC_DMA_STAT_GLPII_SET(value) (((value) << 30) & 0x40000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_STAT.
 */
struct ALT_EMAC_DMA_STAT_s
{
    uint32_t        ti    :  1;  /* Transmit Interrupt */
    uint32_t        tps   :  1;  /* Transmit Process Stopped */
    uint32_t        tu    :  1;  /* Transmit Buffer Unavailable */
    uint32_t        tjt   :  1;  /* Transmit Jabber Timeout */
    uint32_t        ovf   :  1;  /* Receive Overflow */
    uint32_t        unf   :  1;  /* Transmit Underflow */
    uint32_t        ri    :  1;  /* Receive Interrupt */
    uint32_t        ru    :  1;  /* Receive Buffer Unavailable */
    uint32_t        rps   :  1;  /* Receive Process Stopped */
    uint32_t        rwt   :  1;  /* Receive Watchdog Timeout */
    uint32_t        eti   :  1;  /* Early Transmit Interrupt */
    uint32_t              :  2;  /* *UNDEFINED* */
    uint32_t        fbi   :  1;  /* Fatal Bus Error Interrupt */
    uint32_t        eri   :  1;  /* Early Receive Interrupt */
    uint32_t        ais   :  1;  /* Abnormal Interrupt Summary */
    uint32_t        nis   :  1;  /* Normal Interrupt Summary */
    const uint32_t  rs    :  3;  /* Received Process State */
    const uint32_t  ts    :  3;  /* Transmit Process State */
    const uint32_t  eb    :  3;  /* Error Bits */
    const uint32_t  gli   :  1;  /* GMAC Line Interface Interrupt */
    const uint32_t  gmi   :  1;  /* GMAC MMC Interrupt */
    uint32_t              :  1;  /* *UNDEFINED* */
    const uint32_t  tti   :  1;  /* Timestamp Trigger Interrupt */
    const uint32_t  glpii :  1;  /* GMAC LPI Interrupt (for Channel 0) */
    uint32_t              :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_DMA_STAT. */
typedef volatile struct ALT_EMAC_DMA_STAT_s  ALT_EMAC_DMA_STAT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_STAT register from the beginning of the component. */
#define ALT_EMAC_DMA_STAT_OFST        0x14
/* The address of the ALT_EMAC_DMA_STAT register. */
#define ALT_EMAC_DMA_STAT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_STAT_OFST))

/*
 * Register : Register 6 (Operation Mode Register) - Operation_Mode
 * 
 * The Operation Mode register establishes the Transmit and Receive operating modes
 * and commands. This register should be the last CSR to be written as part of the
 * DMA initialization.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                                                             
 * :--------|:-------|:------|:-------------------------------------------------------------------------
 *  [0]     | ???    | 0x0   | *UNDEFINED*                                                             
 *  [1]     | RW     | 0x0   | Start or Stop Receive                                                   
 *  [2]     | RW     | 0x0   | Operate on Second Frame                                                 
 *  [4:3]   | RW     | 0x0   | Receive Threshold Control                                               
 *  [5]     | ???    | 0x0   | *UNDEFINED*                                                             
 *  [6]     | RW     | 0x0   | Forward Undersized Good Frames                                          
 *  [7]     | RW     | 0x0   | Forward Error Frames                                                    
 *  [8]     | RW     | 0x0   | Enable HW Flow Control                                                  
 *  [10:9]  | RW     | 0x0   | Threshold for Activating Flow Control (in half-duplex and full-duplex)  
 *  [12:11] | RW     | 0x0   | Threshold for Deactivating Flow Control (in half-duplex and full-duplex)
 *  [13]    | RW     | 0x0   | Start or Stop Transmission Command                                      
 *  [16:14] | RW     | 0x0   | Transmit Threshold Control                                              
 *  [19:17] | ???    | 0x0   | *UNDEFINED*                                                             
 *  [20]    | RW     | 0x0   | Flush Transmit FIFO                                                     
 *  [21]    | RW     | 0x0   | Transmit Store and Forward                                              
 *  [23:22] | ???    | 0x0   | *UNDEFINED*                                                             
 *  [24]    | RW     | 0x0   | Disable Flushing of Received Frames                                     
 *  [25]    | RW     | 0x0   | Receive Store and Forward                                               
 *  [26]    | RW     | 0x0   | Disable Dropping of TCP/IP Checksum Error Frames                        
 *  [31:27] | ???    | 0x0   | *UNDEFINED*                                                             
 * 
 */
/*
 * Field : Start or Stop Receive - sr
 * 
 * When this bit is set, the Receive process is placed in the Running state. The
 * DMA attempts to acquire the descriptor from the Receive list and processes the
 * incoming frames. The descriptor acquisition is attempted from the current
 * position in the list, which is the address set by Register 3 (Receive Descriptor
 * List Address Register) or the position retained when the Receive process was
 * previously stopped. If the DMA does not own the descriptor, reception is
 * suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register)
 * is set. The Start Receive command is effective only when the reception has
 * stopped. If the command is issued before setting Register 3 (Receive Descriptor
 * List Address Register), the DMA behavior is unpredictable.
 * 
 * When this bit is cleared, the Rx DMA operation is stopped after the transfer of
 * the current frame. The next descriptor position in the Receive list is saved and
 * becomes the current position after the Receive process is restarted. The Stop
 * Receive command is effective only when the Receive process is in either the
 * Running (waiting for receive packet) or in the Suspended state.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                          | Value | Description                
 * :------------------------------|:------|:----------------------------
 *  ALT_EMAC_DMA_OP_MOD_SR_E_DISD | 0x0   | Rx DMA operation is stopped
 *  ALT_EMAC_DMA_OP_MOD_SR_E_END  | 0x1   | Rx DMA operation is started
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR
 * 
 * Rx DMA operation is stopped
 */
#define ALT_EMAC_DMA_OP_MOD_SR_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR
 * 
 * Rx DMA operation is started
 */
#define ALT_EMAC_DMA_OP_MOD_SR_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field. */
#define ALT_EMAC_DMA_OP_MOD_SR_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field. */
#define ALT_EMAC_DMA_OP_MOD_SR_MSB        1
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_SR register field. */
#define ALT_EMAC_DMA_OP_MOD_SR_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_SR register field value. */
#define ALT_EMAC_DMA_OP_MOD_SR_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_SR register field value. */
#define ALT_EMAC_DMA_OP_MOD_SR_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_DMA_OP_MOD_SR register field. */
#define ALT_EMAC_DMA_OP_MOD_SR_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_SR field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_SR_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_DMA_OP_MOD_SR register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_SR_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Operate on Second Frame - osf
 * 
 * When this bit is set, it instructs the DMA to process the second frame of the
 * Transmit data even before the status for the first frame is obtained.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                      
 * :-------------------------------|:------|:----------------------------------
 *  ALT_EMAC_DMA_OP_MOD_OSF_E_DISD | 0x0   | DMA Does Not Process second frame
 *  ALT_EMAC_DMA_OP_MOD_OSF_E_END  | 0x1   | DMA Processes second frame       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF
 * 
 * DMA Does Not Process second frame
 */
#define ALT_EMAC_DMA_OP_MOD_OSF_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF
 * 
 * DMA Processes second frame
 */
#define ALT_EMAC_DMA_OP_MOD_OSF_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
#define ALT_EMAC_DMA_OP_MOD_OSF_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
#define ALT_EMAC_DMA_OP_MOD_OSF_MSB        2
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
#define ALT_EMAC_DMA_OP_MOD_OSF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_OSF register field value. */
#define ALT_EMAC_DMA_OP_MOD_OSF_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_OSF register field value. */
#define ALT_EMAC_DMA_OP_MOD_OSF_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_DMA_OP_MOD_OSF register field. */
#define ALT_EMAC_DMA_OP_MOD_OSF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_OSF field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_OSF_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_DMA_OP_MOD_OSF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_OSF_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Receive Threshold Control - rtc
 * 
 * These two bits control the threshold level of the MTL Receive FIFO. Transfer
 * (request) to DMA starts when the frame size within the MTL Receive FIFO is
 * larger than the threshold. In addition, full frames with length less than the
 * threshold are transferred automatically.
 * 
 * These bits are valid only when the RSF bit is zero, and are ignored when the RSF
 * bit is set to 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description                     
 * :-------------------------------------|:------|:---------------------------------
 *  ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64  | 0x0   | MTL Rcv Fifo threshold level 64 
 *  ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32  | 0x1   | MTL Rcv Fifo threshold level 32 
 *  ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96  | 0x2   | MTL Rcv Fifo threshold level 96 
 *  ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128 | 0x3   | MTL Rcv Fifo threshold level 128
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
 * 
 * MTL Rcv Fifo threshold level 64
 */
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64     0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
 * 
 * MTL Rcv Fifo threshold level 32
 */
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32     0x1
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
 * 
 * MTL Rcv Fifo threshold level 96
 */
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96     0x2
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
 * 
 * MTL Rcv Fifo threshold level 128
 */
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128    0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
#define ALT_EMAC_DMA_OP_MOD_RTC_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
#define ALT_EMAC_DMA_OP_MOD_RTC_MSB        4
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
#define ALT_EMAC_DMA_OP_MOD_RTC_WIDTH      2
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_RTC register field value. */
#define ALT_EMAC_DMA_OP_MOD_RTC_SET_MSK    0x00000018
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RTC register field value. */
#define ALT_EMAC_DMA_OP_MOD_RTC_CLR_MSK    0xffffffe7
/* The reset value of the ALT_EMAC_DMA_OP_MOD_RTC register field. */
#define ALT_EMAC_DMA_OP_MOD_RTC_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_RTC field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_RTC_GET(value) (((value) & 0x00000018) >> 3)
/* Produces a ALT_EMAC_DMA_OP_MOD_RTC register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_RTC_SET(value) (((value) << 3) & 0x00000018)

/*
 * Field : Forward Undersized Good Frames - fuf
 * 
 * When set, the Rx FIFO forwards Undersized frames (frames with no Error and
 * length less than 64 bytes) including pad-bytes and CRC.
 * 
 * When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame
 * is already transferred because of the lower value of Receive Threshold, for
 * example, RTC = 01.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                   
 * :-------------------------------|:------|:-------------------------------
 *  ALT_EMAC_DMA_OP_MOD_FUF_E_DISD | 0x0   | Drops Frames less than 64Bytes
 *  ALT_EMAC_DMA_OP_MOD_FUF_E_END  | 0x1   | Forward Frames with no errors 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF
 * 
 * Drops Frames less than 64Bytes
 */
#define ALT_EMAC_DMA_OP_MOD_FUF_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF
 * 
 * Forward Frames with no errors
 */
#define ALT_EMAC_DMA_OP_MOD_FUF_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
#define ALT_EMAC_DMA_OP_MOD_FUF_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
#define ALT_EMAC_DMA_OP_MOD_FUF_MSB        6
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
#define ALT_EMAC_DMA_OP_MOD_FUF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_FUF register field value. */
#define ALT_EMAC_DMA_OP_MOD_FUF_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FUF register field value. */
#define ALT_EMAC_DMA_OP_MOD_FUF_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_DMA_OP_MOD_FUF register field. */
#define ALT_EMAC_DMA_OP_MOD_FUF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_FUF field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_FUF_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_DMA_OP_MOD_FUF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_FUF_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Forward Error Frames - fef
 * 
 * When this bit is reset, the Rx FIFO drops frames with error status (CRC error,
 * collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However,
 * if the start byte (write) pointer of a frame is already transferred to the read
 * controller side (in Threshold mode), then the frame is not dropped.
 * 
 * When the FEF bit is set, all frames except runt error frames are forwarded to
 * the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial
 * frame is written, then the frame is dropped irrespective of the FEF bit setting.
 * However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial
 * frame is written, then a partial frame may be forwarded to the DMA.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                    
 * :-------------------------------|:------|:--------------------------------
 *  ALT_EMAC_DMA_OP_MOD_FEF_E_DISD | 0x0   | Drops Frames with error status 
 *  ALT_EMAC_DMA_OP_MOD_FEF_E_END  | 0x1   | Forward all Frames(except runt)
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF
 * 
 * Drops Frames with error status
 */
#define ALT_EMAC_DMA_OP_MOD_FEF_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF
 * 
 * Forward all Frames(except runt)
 */
#define ALT_EMAC_DMA_OP_MOD_FEF_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
#define ALT_EMAC_DMA_OP_MOD_FEF_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
#define ALT_EMAC_DMA_OP_MOD_FEF_MSB        7
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
#define ALT_EMAC_DMA_OP_MOD_FEF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_FEF register field value. */
#define ALT_EMAC_DMA_OP_MOD_FEF_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FEF register field value. */
#define ALT_EMAC_DMA_OP_MOD_FEF_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_DMA_OP_MOD_FEF register field. */
#define ALT_EMAC_DMA_OP_MOD_FEF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_FEF field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_FEF_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_DMA_OP_MOD_FEF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_FEF_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Enable HW Flow Control - efc
 * 
 * When this bit is set, the flow control signal operation based on the fill-level
 * of Rx FIFO is enabled. When reset, the flow control operation is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                    
 * :-------------------------------|:------|:--------------------------------
 *  ALT_EMAC_DMA_OP_MOD_EFC_E_DISD | 0x0   | Rx FIFO Fill Level Disabled    
 *  ALT_EMAC_DMA_OP_MOD_EFC_E_END  | 0x1   | Rx FIFO Fill Level Enabled Ctrl
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC
 * 
 * Rx FIFO Fill Level Disabled
 */
#define ALT_EMAC_DMA_OP_MOD_EFC_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC
 * 
 * Rx FIFO Fill Level Enabled Ctrl
 */
#define ALT_EMAC_DMA_OP_MOD_EFC_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
#define ALT_EMAC_DMA_OP_MOD_EFC_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
#define ALT_EMAC_DMA_OP_MOD_EFC_MSB        8
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
#define ALT_EMAC_DMA_OP_MOD_EFC_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_EFC register field value. */
#define ALT_EMAC_DMA_OP_MOD_EFC_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_EFC register field value. */
#define ALT_EMAC_DMA_OP_MOD_EFC_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_DMA_OP_MOD_EFC register field. */
#define ALT_EMAC_DMA_OP_MOD_EFC_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_EFC field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_EFC_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_DMA_OP_MOD_EFC register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_EFC_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Threshold for Activating Flow Control (in half-duplex and full-duplex) - rfa
 * 
 * These bits control the threshold (Fill level of Rx FIFO) at which the flow
 * control is activated.
 * 
 * These values only apply to the Rx FIFO when the EFC bit is set high.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description    
 * :--------------------------------------|:------|:----------------
 *  ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K | 0x0   | Full minus 1 KB
 *  ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K | 0x1   | Full minus 2 KB
 *  ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K | 0x2   | Full minus 3 KB
 *  ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K | 0x3   | Full minus 4 KB
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
 * 
 * Full minus 1 KB
 */
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
 * 
 * Full minus 2 KB
 */
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K   0x1
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
 * 
 * Full minus 3 KB
 */
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K   0x2
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
 * 
 * Full minus 4 KB
 */
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K   0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
#define ALT_EMAC_DMA_OP_MOD_RFA_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
#define ALT_EMAC_DMA_OP_MOD_RFA_MSB        10
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
#define ALT_EMAC_DMA_OP_MOD_RFA_WIDTH      2
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_RFA register field value. */
#define ALT_EMAC_DMA_OP_MOD_RFA_SET_MSK    0x00000600
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFA register field value. */
#define ALT_EMAC_DMA_OP_MOD_RFA_CLR_MSK    0xfffff9ff
/* The reset value of the ALT_EMAC_DMA_OP_MOD_RFA register field. */
#define ALT_EMAC_DMA_OP_MOD_RFA_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_RFA field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_RFA_GET(value) (((value) & 0x00000600) >> 9)
/* Produces a ALT_EMAC_DMA_OP_MOD_RFA register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_RFA_SET(value) (((value) << 9) & 0x00000600)

/*
 * Field : Threshold for Deactivating Flow Control (in half-duplex and full-duplex) - rfd
 * 
 * These bits control the threshold (Fill-level of Rx FIFO) at which the flow
 * control is de-asserted after activation.
 * 
 * The de-assertion is effective only after flow control is asserted.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description    
 * :--------------------------------------|:------|:----------------
 *  ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K | 0x0   | Full minus 1 KB
 *  ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K | 0x1   | Full minus 2 KB
 *  ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K | 0x2   | Full minus 3 KB
 *  ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K | 0x3   | Full minus 4 KB
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
 * 
 * Full minus 1 KB
 */
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
 * 
 * Full minus 2 KB
 */
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K   0x1
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
 * 
 * Full minus 3 KB
 */
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K   0x2
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
 * 
 * Full minus 4 KB
 */
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K   0x3

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
#define ALT_EMAC_DMA_OP_MOD_RFD_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
#define ALT_EMAC_DMA_OP_MOD_RFD_MSB        12
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
#define ALT_EMAC_DMA_OP_MOD_RFD_WIDTH      2
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_RFD register field value. */
#define ALT_EMAC_DMA_OP_MOD_RFD_SET_MSK    0x00001800
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFD register field value. */
#define ALT_EMAC_DMA_OP_MOD_RFD_CLR_MSK    0xffffe7ff
/* The reset value of the ALT_EMAC_DMA_OP_MOD_RFD register field. */
#define ALT_EMAC_DMA_OP_MOD_RFD_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_RFD field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_RFD_GET(value) (((value) & 0x00001800) >> 11)
/* Produces a ALT_EMAC_DMA_OP_MOD_RFD register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_RFD_SET(value) (((value) << 11) & 0x00001800)

/*
 * Field : Start or Stop Transmission Command - st
 * 
 * When this bit is set, transmission is placed in the Running state, and the DMA
 * checks the Transmit List at the current position for a frame to be transmitted.
 * Descriptor acquisition is attempted either from the current position in the
 * list, which is the Transmit List Base Address set by Register 4 (Transmit
 * Descriptor List Address Register), or from the position retained when
 * transmission was stopped previously. If the DMA does not own the current
 * descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer
 * Unavailable) of Register 5 (Status Register) is set. The Start Transmission
 * command is effective only when transmission is stopped. If the command is issued
 * before setting Register 4 (Transmit Descriptor List Address Register), then the
 * DMA behavior is unpredictable.
 * 
 * When this bit is reset, the transmission process is placed in the Stopped state
 * after completing the transmission of the current frame. The Next Descriptor
 * position in the Transmit List is saved, and it becomes the current position when
 * transmission is restarted. To change the list address, you need to program
 * Register 4 (Transmit Descriptor List Address Register) with a new value when
 * this bit is reset. The new value is considered when this bit is set again. The
 * stop transmission command is effective only when the transmission of the current
 * frame is complete or the transmission is in the Suspended state.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                          | Value | Description               
 * :------------------------------|:------|:---------------------------
 *  ALT_EMAC_DMA_OP_MOD_ST_E_DISD | 0x0   | Transmission Stopped State
 *  ALT_EMAC_DMA_OP_MOD_ST_E_END  | 0x1   | Transmission in Run State 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST
 * 
 * Transmission Stopped State
 */
#define ALT_EMAC_DMA_OP_MOD_ST_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST
 * 
 * Transmission in Run State
 */
#define ALT_EMAC_DMA_OP_MOD_ST_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field. */
#define ALT_EMAC_DMA_OP_MOD_ST_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field. */
#define ALT_EMAC_DMA_OP_MOD_ST_MSB        13
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_ST register field. */
#define ALT_EMAC_DMA_OP_MOD_ST_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_ST register field value. */
#define ALT_EMAC_DMA_OP_MOD_ST_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_ST register field value. */
#define ALT_EMAC_DMA_OP_MOD_ST_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_DMA_OP_MOD_ST register field. */
#define ALT_EMAC_DMA_OP_MOD_ST_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_ST field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_ST_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_DMA_OP_MOD_ST register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_ST_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : Transmit Threshold Control - ttc
 * 
 * These bits control the threshold level of the MTL Transmit FIFO. Transmission
 * starts when the frame size within the MTL Transmit FIFO is larger than the
 * threshold. In addition, full frames with a length less than the threshold are
 * also transmitted. These bits are used only when Bit 21 (TSF) is reset.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                    
 * :--------------------------------------|:------|:--------------------------------
 *  ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64  | 0x0   | MTL Transmit FIFO Threshold 64 
 *  ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128 | 0x1   | MTL Transmit FIFO Threshold 128
 *  ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192 | 0x2   | MTL Transmit FIFO Threshold 192
 *  ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256 | 0x3   | MTL Transmit FIFO Threshold 256
 *  ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40  | 0x4   | MTL Transmit FIFO Threshold 40 
 *  ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32  | 0x5   | MTL Transmit FIFO Threshold 32 
 *  ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24  | 0x6   | MTL Transmit FIFO Threshold 24 
 *  ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16  | 0x7   | MTL Transmit FIFO Threshold 16 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
 * 
 * MTL Transmit FIFO Threshold 64
 */
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64    0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
 * 
 * MTL Transmit FIFO Threshold 128
 */
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128   0x1
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
 * 
 * MTL Transmit FIFO Threshold 192
 */
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192   0x2
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
 * 
 * MTL Transmit FIFO Threshold 256
 */
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256   0x3
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
 * 
 * MTL Transmit FIFO Threshold 40
 */
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40    0x4
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
 * 
 * MTL Transmit FIFO Threshold 32
 */
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32    0x5
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
 * 
 * MTL Transmit FIFO Threshold 24
 */
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24    0x6
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
 * 
 * MTL Transmit FIFO Threshold 16
 */
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16    0x7

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
#define ALT_EMAC_DMA_OP_MOD_TTC_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
#define ALT_EMAC_DMA_OP_MOD_TTC_MSB        16
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
#define ALT_EMAC_DMA_OP_MOD_TTC_WIDTH      3
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_TTC register field value. */
#define ALT_EMAC_DMA_OP_MOD_TTC_SET_MSK    0x0001c000
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_TTC register field value. */
#define ALT_EMAC_DMA_OP_MOD_TTC_CLR_MSK    0xfffe3fff
/* The reset value of the ALT_EMAC_DMA_OP_MOD_TTC register field. */
#define ALT_EMAC_DMA_OP_MOD_TTC_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_TTC field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_TTC_GET(value) (((value) & 0x0001c000) >> 14)
/* Produces a ALT_EMAC_DMA_OP_MOD_TTC register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_TTC_SET(value) (((value) << 14) & 0x0001c000)

/*
 * Field : Flush Transmit FIFO - ftf
 * 
 * When this bit is set, the transmit FIFO controller logic is reset to its default
 * values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared
 * internally when the flushing operation is completed. The Operation Mode register
 * should not be written to until this bit is cleared. The data which is already
 * accepted by the MAC transmitter is not flushed. It is scheduled for transmission
 * and results in underflow and runt frame transmission.
 * 
 * Note: The flush operation is complete only when the Tx FIFO is emptied of its
 * contents and all the pending Transmit Status of the transmitted frames are
 * accepted by the host. To complete this flush operation, the PHY transmit clock
 * is required to be active.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description             
 * :-------------------------------|:------|:-------------------------
 *  ALT_EMAC_DMA_OP_MOD_FTF_E_DISD | 0x0   | Tx FIFO Data not Flushed
 *  ALT_EMAC_DMA_OP_MOD_FTF_E_END  | 0x1   | TX FIFO Data Flushed    
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF
 * 
 * Tx FIFO Data not Flushed
 */
#define ALT_EMAC_DMA_OP_MOD_FTF_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF
 * 
 * TX FIFO Data Flushed
 */
#define ALT_EMAC_DMA_OP_MOD_FTF_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
#define ALT_EMAC_DMA_OP_MOD_FTF_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
#define ALT_EMAC_DMA_OP_MOD_FTF_MSB        20
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
#define ALT_EMAC_DMA_OP_MOD_FTF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_FTF register field value. */
#define ALT_EMAC_DMA_OP_MOD_FTF_SET_MSK    0x00100000
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_FTF register field value. */
#define ALT_EMAC_DMA_OP_MOD_FTF_CLR_MSK    0xffefffff
/* The reset value of the ALT_EMAC_DMA_OP_MOD_FTF register field. */
#define ALT_EMAC_DMA_OP_MOD_FTF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_FTF field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_FTF_GET(value) (((value) & 0x00100000) >> 20)
/* Produces a ALT_EMAC_DMA_OP_MOD_FTF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_FTF_SET(value) (((value) << 20) & 0x00100000)

/*
 * Field : Transmit Store and Forward - tsf
 * 
 * When this bit is set, transmission starts when a full frame resides in the MTL
 * Transmit FIFO. When this bit is set, the TTC values specified in Bits[16:14] are
 * ignored. This bit should be changed only when the transmission is stopped.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                      
 * :-------------------------------|:------|:----------------------------------
 *  ALT_EMAC_DMA_OP_MOD_TSF_E_DISD | 0x0   | Tx Does not Start with Full Frame
 *  ALT_EMAC_DMA_OP_MOD_TSF_E_END  | 0x1   | Tx Start with Full Frame         
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF
 * 
 * Tx Does not Start with Full Frame
 */
#define ALT_EMAC_DMA_OP_MOD_TSF_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF
 * 
 * Tx Start with Full Frame
 */
#define ALT_EMAC_DMA_OP_MOD_TSF_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
#define ALT_EMAC_DMA_OP_MOD_TSF_LSB        21
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
#define ALT_EMAC_DMA_OP_MOD_TSF_MSB        21
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
#define ALT_EMAC_DMA_OP_MOD_TSF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_TSF register field value. */
#define ALT_EMAC_DMA_OP_MOD_TSF_SET_MSK    0x00200000
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_TSF register field value. */
#define ALT_EMAC_DMA_OP_MOD_TSF_CLR_MSK    0xffdfffff
/* The reset value of the ALT_EMAC_DMA_OP_MOD_TSF register field. */
#define ALT_EMAC_DMA_OP_MOD_TSF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_TSF field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_TSF_GET(value) (((value) & 0x00200000) >> 21)
/* Produces a ALT_EMAC_DMA_OP_MOD_TSF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_TSF_SET(value) (((value) << 21) & 0x00200000)

/*
 * Field : Disable Flushing of Received Frames - dff
 * 
 * When this bit is set, the Rx DMA does not flush any frames because of the
 * unavailability of receive descriptors or buffers as it does normally when this
 * bit is reset.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description       
 * :-------------------------------|:------|:-------------------
 *  ALT_EMAC_DMA_OP_MOD_DFF_E_DISD | 0x0   | Rx DMA Flushed    
 *  ALT_EMAC_DMA_OP_MOD_DFF_E_END  | 0x1   | Rx DMA not Flushed
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF
 * 
 * Rx DMA Flushed
 */
#define ALT_EMAC_DMA_OP_MOD_DFF_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF
 * 
 * Rx DMA not Flushed
 */
#define ALT_EMAC_DMA_OP_MOD_DFF_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
#define ALT_EMAC_DMA_OP_MOD_DFF_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
#define ALT_EMAC_DMA_OP_MOD_DFF_MSB        24
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
#define ALT_EMAC_DMA_OP_MOD_DFF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_DFF register field value. */
#define ALT_EMAC_DMA_OP_MOD_DFF_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_DFF register field value. */
#define ALT_EMAC_DMA_OP_MOD_DFF_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_DMA_OP_MOD_DFF register field. */
#define ALT_EMAC_DMA_OP_MOD_DFF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_DFF field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_DFF_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_DMA_OP_MOD_DFF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_DFF_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Receive Store and Forward - rsf
 * 
 * When this bit is set, the MTL reads a frame from the Rx FIFO only after the
 * complete frame has been written to it, ignoring the RTC bits. When this bit is
 * reset, the Rx FIFO operates in the cut-through mode, subject to the threshold
 * specified by the RTC bits.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                           
 * :-------------------------------|:------|:---------------------------------------
 *  ALT_EMAC_DMA_OP_MOD_RSF_E_DISD | 0x0   | Rx Fifo cut-through mode              
 *  ALT_EMAC_DMA_OP_MOD_RSF_E_END  | 0x1   | Read Rx FIFO only after complete frame
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF
 * 
 * Rx Fifo cut-through mode
 */
#define ALT_EMAC_DMA_OP_MOD_RSF_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF
 * 
 * Read Rx FIFO only after complete frame
 */
#define ALT_EMAC_DMA_OP_MOD_RSF_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
#define ALT_EMAC_DMA_OP_MOD_RSF_LSB        25
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
#define ALT_EMAC_DMA_OP_MOD_RSF_MSB        25
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
#define ALT_EMAC_DMA_OP_MOD_RSF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_RSF register field value. */
#define ALT_EMAC_DMA_OP_MOD_RSF_SET_MSK    0x02000000
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSF register field value. */
#define ALT_EMAC_DMA_OP_MOD_RSF_CLR_MSK    0xfdffffff
/* The reset value of the ALT_EMAC_DMA_OP_MOD_RSF register field. */
#define ALT_EMAC_DMA_OP_MOD_RSF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_RSF field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_RSF_GET(value) (((value) & 0x02000000) >> 25)
/* Produces a ALT_EMAC_DMA_OP_MOD_RSF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_RSF_SET(value) (((value) << 25) & 0x02000000)

/*
 * Field : Disable Dropping of TCP/IP Checksum Error Frames - dt
 * 
 * When this bit is set, the MAC does not drop the frames which only have errors
 * detected by the Receive Checksum Offload engine. Such frames do not have any
 * errors (including FCS error) in the Ethernet frame received by the MAC but have
 * errors only in the encapsulated payload. When this bit is reset, all error
 * frames are dropped if the FEF bit is reset.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                          | Value | Description                        
 * :------------------------------|:------|:------------------------------------
 *  ALT_EMAC_DMA_OP_MOD_DT_E_DISD | 0x0   | All Error Frames Dropped           
 *  ALT_EMAC_DMA_OP_MOD_DT_E_END  | 0x1   | MAC does not drop frame with errors
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT
 * 
 * All Error Frames Dropped
 */
#define ALT_EMAC_DMA_OP_MOD_DT_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT
 * 
 * MAC does not drop frame with errors
 */
#define ALT_EMAC_DMA_OP_MOD_DT_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field. */
#define ALT_EMAC_DMA_OP_MOD_DT_LSB        26
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field. */
#define ALT_EMAC_DMA_OP_MOD_DT_MSB        26
/* The width in bits of the ALT_EMAC_DMA_OP_MOD_DT register field. */
#define ALT_EMAC_DMA_OP_MOD_DT_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_OP_MOD_DT register field value. */
#define ALT_EMAC_DMA_OP_MOD_DT_SET_MSK    0x04000000
/* The mask used to clear the ALT_EMAC_DMA_OP_MOD_DT register field value. */
#define ALT_EMAC_DMA_OP_MOD_DT_CLR_MSK    0xfbffffff
/* The reset value of the ALT_EMAC_DMA_OP_MOD_DT register field. */
#define ALT_EMAC_DMA_OP_MOD_DT_RESET      0x0
/* Extracts the ALT_EMAC_DMA_OP_MOD_DT field value from a register. */
#define ALT_EMAC_DMA_OP_MOD_DT_GET(value) (((value) & 0x04000000) >> 26)
/* Produces a ALT_EMAC_DMA_OP_MOD_DT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_OP_MOD_DT_SET(value) (((value) << 26) & 0x04000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_OP_MOD.
 */
struct ALT_EMAC_DMA_OP_MOD_s
{
    uint32_t      :  1;  /* *UNDEFINED* */
    uint32_t  sr  :  1;  /* Start or Stop Receive */
    uint32_t  osf :  1;  /* Operate on Second Frame */
    uint32_t  rtc :  2;  /* Receive Threshold Control */
    uint32_t      :  1;  /* *UNDEFINED* */
    uint32_t  fuf :  1;  /* Forward Undersized Good Frames */
    uint32_t  fef :  1;  /* Forward Error Frames */
    uint32_t  efc :  1;  /* Enable HW Flow Control */
    uint32_t  rfa :  2;  /* Threshold for Activating Flow Control (in half-duplex and full-duplex) */
    uint32_t  rfd :  2;  /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex) */
    uint32_t  st  :  1;  /* Start or Stop Transmission Command */
    uint32_t  ttc :  3;  /* Transmit Threshold Control */
    uint32_t      :  3;  /* *UNDEFINED* */
    uint32_t  ftf :  1;  /* Flush Transmit FIFO */
    uint32_t  tsf :  1;  /* Transmit Store and Forward */
    uint32_t      :  2;  /* *UNDEFINED* */
    uint32_t  dff :  1;  /* Disable Flushing of Received Frames */
    uint32_t  rsf :  1;  /* Receive Store and Forward */
    uint32_t  dt  :  1;  /* Disable Dropping of TCP/IP Checksum Error Frames */
    uint32_t      :  5;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_DMA_OP_MOD. */
typedef volatile struct ALT_EMAC_DMA_OP_MOD_s  ALT_EMAC_DMA_OP_MOD_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_OP_MOD register from the beginning of the component. */
#define ALT_EMAC_DMA_OP_MOD_OFST        0x18
/* The address of the ALT_EMAC_DMA_OP_MOD register. */
#define ALT_EMAC_DMA_OP_MOD_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_OP_MOD_OFST))

/*
 * Register : Register 7 (Interrupt Enable Register) - Interrupt_Enable
 * 
 * The Interrupt Enable register enables the interrupts reported by Register 5
 * (Status Register). Setting a bit to 1'b1 enables a corresponding interrupt.
 * After a hardware or software reset, all interrupts are disabled.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                      
 * :--------|:-------|:------|:----------------------------------
 *  [0]     | RW     | 0x0   | Transmit Interrupt Enable        
 *  [1]     | RW     | 0x0   | Transmit Stopped Enable          
 *  [2]     | RW     | 0x0   | Transmit Buffer Unvailable Enable
 *  [3]     | RW     | 0x0   | Transmit Jabber Timeout Enable   
 *  [4]     | RW     | 0x0   | Overflow Interrupt Enable        
 *  [5]     | RW     | 0x0   | Underflow Interrupt Enable       
 *  [6]     | RW     | 0x0   | Receive Interrupt Enable         
 *  [7]     | RW     | 0x0   | Receive Buffer Unavailable Enable
 *  [8]     | RW     | 0x0   | Receive Stopped Enable           
 *  [9]     | RW     | 0x0   | Receive Watchdog Timeout Enable  
 *  [10]    | RW     | 0x0   | Early Transmit Interrupt Enable  
 *  [12:11] | ???    | 0x0   | *UNDEFINED*                      
 *  [13]    | RW     | 0x0   | Fatal Bus Error Enable           
 *  [14]    | RW     | 0x0   | Early Receive Interrupt Enable   
 *  [15]    | RW     | 0x0   | Abnormal Interrupt Summary Enable
 *  [16]    | RW     | 0x0   | Normal Interrupt Summary Enable  
 *  [31:17] | ???    | 0x0   | *UNDEFINED*                      
 * 
 */
/*
 * Field : Transmit Interrupt Enable - tie
 * 
 * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit
 * Interrupt is enabled. When this bit is reset, the Transmit Interrupt is
 * disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                
 * :-------------------------------|:------|:----------------------------
 *  ALT_EMAC_DMA_INT_EN_TIE_E_DISD | 0x0   | Transmit Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_TIE_E_END  | 0x1   | Transmit Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TIE
 * 
 * Transmit Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_TIE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TIE
 * 
 * Transmit Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_TIE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TIE register field. */
#define ALT_EMAC_DMA_INT_EN_TIE_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TIE register field. */
#define ALT_EMAC_DMA_INT_EN_TIE_MSB        0
/* The width in bits of the ALT_EMAC_DMA_INT_EN_TIE register field. */
#define ALT_EMAC_DMA_INT_EN_TIE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_TIE register field value. */
#define ALT_EMAC_DMA_INT_EN_TIE_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_TIE register field value. */
#define ALT_EMAC_DMA_INT_EN_TIE_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_DMA_INT_EN_TIE register field. */
#define ALT_EMAC_DMA_INT_EN_TIE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_TIE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_TIE_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_DMA_INT_EN_TIE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_TIE_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : Transmit Stopped Enable - tse
 * 
 * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
 * Transmission Stopped Interrupt is enabled. When this bit is reset, the
 * Transmission Stopped Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                        
 * :-------------------------------|:------|:------------------------------------
 *  ALT_EMAC_DMA_INT_EN_TSE_E_DISD | 0x0   | Transmit Stopped Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_TSE_E_END  | 0x1   | Transmit Stopped Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TSE
 * 
 * Transmit Stopped Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_TSE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TSE
 * 
 * Transmit Stopped Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_TSE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TSE register field. */
#define ALT_EMAC_DMA_INT_EN_TSE_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TSE register field. */
#define ALT_EMAC_DMA_INT_EN_TSE_MSB        1
/* The width in bits of the ALT_EMAC_DMA_INT_EN_TSE register field. */
#define ALT_EMAC_DMA_INT_EN_TSE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_TSE register field value. */
#define ALT_EMAC_DMA_INT_EN_TSE_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_TSE register field value. */
#define ALT_EMAC_DMA_INT_EN_TSE_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_DMA_INT_EN_TSE register field. */
#define ALT_EMAC_DMA_INT_EN_TSE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_TSE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_TSE_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_DMA_INT_EN_TSE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_TSE_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Transmit Buffer Unvailable Enable - tue
 * 
 * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit
 * Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit
 * Buffer Unavailable Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                                   
 * :-------------------------------|:------|:-----------------------------------------------
 *  ALT_EMAC_DMA_INT_EN_TUE_E_DISD | 0x0   | Transmit Buffer Unavailable Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_TUE_E_END  | 0x1   | Transmit Buffer Unavailable Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TUE
 * 
 * Transmit Buffer Unavailable Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_TUE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TUE
 * 
 * Transmit Buffer Unavailable Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_TUE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TUE register field. */
#define ALT_EMAC_DMA_INT_EN_TUE_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TUE register field. */
#define ALT_EMAC_DMA_INT_EN_TUE_MSB        2
/* The width in bits of the ALT_EMAC_DMA_INT_EN_TUE register field. */
#define ALT_EMAC_DMA_INT_EN_TUE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_TUE register field value. */
#define ALT_EMAC_DMA_INT_EN_TUE_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_TUE register field value. */
#define ALT_EMAC_DMA_INT_EN_TUE_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_DMA_INT_EN_TUE register field. */
#define ALT_EMAC_DMA_INT_EN_TUE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_TUE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_TUE_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_DMA_INT_EN_TUE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_TUE_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Transmit Jabber Timeout Enable - tje
 * 
 * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
 * Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the
 * Transmit Jabber Timeout Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                               
 * :-------------------------------|:------|:-------------------------------------------
 *  ALT_EMAC_DMA_INT_EN_TJE_E_DISD | 0x0   | Transmit Jabber Timeout Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_TJE_E_END  | 0x1   | Transmit Jabber Timeout Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TJE
 * 
 * Transmit Jabber Timeout Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_TJE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_TJE
 * 
 * Transmit Jabber Timeout Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_TJE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TJE register field. */
#define ALT_EMAC_DMA_INT_EN_TJE_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TJE register field. */
#define ALT_EMAC_DMA_INT_EN_TJE_MSB        3
/* The width in bits of the ALT_EMAC_DMA_INT_EN_TJE register field. */
#define ALT_EMAC_DMA_INT_EN_TJE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_TJE register field value. */
#define ALT_EMAC_DMA_INT_EN_TJE_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_TJE register field value. */
#define ALT_EMAC_DMA_INT_EN_TJE_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_DMA_INT_EN_TJE register field. */
#define ALT_EMAC_DMA_INT_EN_TJE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_TJE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_TJE_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_DMA_INT_EN_TJE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_TJE_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Overflow Interrupt Enable - ove
 * 
 * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
 * Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow
 * Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                         
 * :-------------------------------|:------|:-------------------------------------
 *  ALT_EMAC_DMA_INT_EN_OVE_E_DISD | 0x0   | Transmit Overflow Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_OVE_E_END  | 0x1   | Transmit Overflow Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_OVE
 * 
 * Transmit Overflow Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_OVE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_OVE
 * 
 * Transmit Overflow Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_OVE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_OVE register field. */
#define ALT_EMAC_DMA_INT_EN_OVE_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_OVE register field. */
#define ALT_EMAC_DMA_INT_EN_OVE_MSB        4
/* The width in bits of the ALT_EMAC_DMA_INT_EN_OVE register field. */
#define ALT_EMAC_DMA_INT_EN_OVE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_OVE register field value. */
#define ALT_EMAC_DMA_INT_EN_OVE_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_OVE register field value. */
#define ALT_EMAC_DMA_INT_EN_OVE_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_DMA_INT_EN_OVE register field. */
#define ALT_EMAC_DMA_INT_EN_OVE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_OVE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_OVE_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_DMA_INT_EN_OVE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_OVE_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Underflow Interrupt Enable - une
 * 
 * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
 * Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow
 * Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                 
 * :-------------------------------|:------|:-----------------------------
 *  ALT_EMAC_DMA_INT_EN_UNE_E_DISD | 0x0   | Underflow Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_UNE_E_END  | 0x1   | Underflow Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_UNE
 * 
 * Underflow Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_UNE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_UNE
 * 
 * Underflow Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_UNE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_UNE register field. */
#define ALT_EMAC_DMA_INT_EN_UNE_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_UNE register field. */
#define ALT_EMAC_DMA_INT_EN_UNE_MSB        5
/* The width in bits of the ALT_EMAC_DMA_INT_EN_UNE register field. */
#define ALT_EMAC_DMA_INT_EN_UNE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_UNE register field value. */
#define ALT_EMAC_DMA_INT_EN_UNE_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_UNE register field value. */
#define ALT_EMAC_DMA_INT_EN_UNE_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_DMA_INT_EN_UNE register field. */
#define ALT_EMAC_DMA_INT_EN_UNE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_UNE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_UNE_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_DMA_INT_EN_UNE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_UNE_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : Receive Interrupt Enable - rie
 * 
 * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive
 * Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description               
 * :-------------------------------|:------|:---------------------------
 *  ALT_EMAC_DMA_INT_EN_RIE_E_DISD | 0x0   | Receive Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_RIE_E_END  | 0x1   | Receive Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RIE
 * 
 * Receive Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_RIE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RIE
 * 
 * Receive Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_RIE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RIE register field. */
#define ALT_EMAC_DMA_INT_EN_RIE_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RIE register field. */
#define ALT_EMAC_DMA_INT_EN_RIE_MSB        6
/* The width in bits of the ALT_EMAC_DMA_INT_EN_RIE register field. */
#define ALT_EMAC_DMA_INT_EN_RIE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_RIE register field value. */
#define ALT_EMAC_DMA_INT_EN_RIE_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_RIE register field value. */
#define ALT_EMAC_DMA_INT_EN_RIE_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_DMA_INT_EN_RIE register field. */
#define ALT_EMAC_DMA_INT_EN_RIE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_RIE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_RIE_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_DMA_INT_EN_RIE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_RIE_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : Receive Buffer Unavailable Enable - rue
 * 
 * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
 * Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the
 * Receive Buffer Unavailable Interrupt is disabled.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RUE register field. */
#define ALT_EMAC_DMA_INT_EN_RUE_LSB        7
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RUE register field. */
#define ALT_EMAC_DMA_INT_EN_RUE_MSB        7
/* The width in bits of the ALT_EMAC_DMA_INT_EN_RUE register field. */
#define ALT_EMAC_DMA_INT_EN_RUE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_RUE register field value. */
#define ALT_EMAC_DMA_INT_EN_RUE_SET_MSK    0x00000080
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_RUE register field value. */
#define ALT_EMAC_DMA_INT_EN_RUE_CLR_MSK    0xffffff7f
/* The reset value of the ALT_EMAC_DMA_INT_EN_RUE register field. */
#define ALT_EMAC_DMA_INT_EN_RUE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_RUE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_RUE_GET(value) (((value) & 0x00000080) >> 7)
/* Produces a ALT_EMAC_DMA_INT_EN_RUE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_RUE_SET(value) (((value) << 7) & 0x00000080)

/*
 * Field : Receive Stopped Enable - rse
 * 
 * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
 * Receive Stopped Interrupt is enabled. When this bit is reset, the Receive
 * Stopped Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                       
 * :-------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_DMA_INT_EN_RSE_E_DISD | 0x0   | Receive Stopped Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_RSE_E_END  | 0x1   | Receive Stopped Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RSE
 * 
 * Receive Stopped Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_RSE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RSE
 * 
 * Receive Stopped Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_RSE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RSE register field. */
#define ALT_EMAC_DMA_INT_EN_RSE_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RSE register field. */
#define ALT_EMAC_DMA_INT_EN_RSE_MSB        8
/* The width in bits of the ALT_EMAC_DMA_INT_EN_RSE register field. */
#define ALT_EMAC_DMA_INT_EN_RSE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_RSE register field value. */
#define ALT_EMAC_DMA_INT_EN_RSE_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_RSE register field value. */
#define ALT_EMAC_DMA_INT_EN_RSE_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_DMA_INT_EN_RSE register field. */
#define ALT_EMAC_DMA_INT_EN_RSE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_RSE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_RSE_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_DMA_INT_EN_RSE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_RSE_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : Receive Watchdog Timeout Enable - rwe
 * 
 * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the
 * Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the
 * Receive Watchdog Timeout Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                                
 * :-------------------------------|:------|:--------------------------------------------
 *  ALT_EMAC_DMA_INT_EN_RWE_E_DISD | 0x0   | Receive Watchdog Timeout Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_RWE_E_END  | 0x1   | Receive Watchdog Timeout Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RWE
 * 
 * Receive Watchdog Timeout Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_RWE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_RWE
 * 
 * Receive Watchdog Timeout Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_RWE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RWE register field. */
#define ALT_EMAC_DMA_INT_EN_RWE_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RWE register field. */
#define ALT_EMAC_DMA_INT_EN_RWE_MSB        9
/* The width in bits of the ALT_EMAC_DMA_INT_EN_RWE register field. */
#define ALT_EMAC_DMA_INT_EN_RWE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_RWE register field value. */
#define ALT_EMAC_DMA_INT_EN_RWE_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_RWE register field value. */
#define ALT_EMAC_DMA_INT_EN_RWE_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_DMA_INT_EN_RWE register field. */
#define ALT_EMAC_DMA_INT_EN_RWE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_RWE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_RWE_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_DMA_INT_EN_RWE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_RWE_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : Early Transmit Interrupt Enable - ete
 * 
 * When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the
 * Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit
 * Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                      
 * :-------------------------------|:------|:----------------------------------
 *  ALT_EMAC_DMA_INT_EN_ETE_E_DISD | 0x0   | Early Transmit Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_ETE_E_END  | 0x1   | Early Transmit Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ETE
 * 
 * Early Transmit Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_ETE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ETE
 * 
 * Early Transmit Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_ETE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_ETE register field. */
#define ALT_EMAC_DMA_INT_EN_ETE_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_ETE register field. */
#define ALT_EMAC_DMA_INT_EN_ETE_MSB        10
/* The width in bits of the ALT_EMAC_DMA_INT_EN_ETE register field. */
#define ALT_EMAC_DMA_INT_EN_ETE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_ETE register field value. */
#define ALT_EMAC_DMA_INT_EN_ETE_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_ETE register field value. */
#define ALT_EMAC_DMA_INT_EN_ETE_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_DMA_INT_EN_ETE register field. */
#define ALT_EMAC_DMA_INT_EN_ETE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_ETE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_ETE_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_DMA_INT_EN_ETE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_ETE_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : Fatal Bus Error Enable - fbe
 * 
 * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal
 * Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error
 * Enable Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                       
 * :-------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_DMA_INT_EN_FBE_E_DISD | 0x0   | Fatal Bus Error Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_FBE_E_END  | 0x1   | Fatal Bus Error Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_FBE
 * 
 * Fatal Bus Error Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_FBE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_FBE
 * 
 * Fatal Bus Error Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_FBE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_FBE register field. */
#define ALT_EMAC_DMA_INT_EN_FBE_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_FBE register field. */
#define ALT_EMAC_DMA_INT_EN_FBE_MSB        13
/* The width in bits of the ALT_EMAC_DMA_INT_EN_FBE register field. */
#define ALT_EMAC_DMA_INT_EN_FBE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_FBE register field value. */
#define ALT_EMAC_DMA_INT_EN_FBE_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_FBE register field value. */
#define ALT_EMAC_DMA_INT_EN_FBE_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_DMA_INT_EN_FBE register field. */
#define ALT_EMAC_DMA_INT_EN_FBE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_FBE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_FBE_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_DMA_INT_EN_FBE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_FBE_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : Early Receive Interrupt Enable - ere
 * 
 * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early
 * Receive Interrupt is enabled. When this bit is reset, the Early Receive
 * Interrupt is disabled.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                     
 * :-------------------------------|:------|:---------------------------------
 *  ALT_EMAC_DMA_INT_EN_ERE_E_DISD | 0x0   | Early Receive Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_ERE_E_END  | 0x1   | Early Receive Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ERE
 * 
 * Early Receive Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_ERE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_ERE
 * 
 * Early Receive Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_ERE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_ERE register field. */
#define ALT_EMAC_DMA_INT_EN_ERE_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_ERE register field. */
#define ALT_EMAC_DMA_INT_EN_ERE_MSB        14
/* The width in bits of the ALT_EMAC_DMA_INT_EN_ERE register field. */
#define ALT_EMAC_DMA_INT_EN_ERE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_ERE register field value. */
#define ALT_EMAC_DMA_INT_EN_ERE_SET_MSK    0x00004000
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_ERE register field value. */
#define ALT_EMAC_DMA_INT_EN_ERE_CLR_MSK    0xffffbfff
/* The reset value of the ALT_EMAC_DMA_INT_EN_ERE register field. */
#define ALT_EMAC_DMA_INT_EN_ERE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_ERE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_ERE_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_EMAC_DMA_INT_EN_ERE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_ERE_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : Abnormal Interrupt Summary Enable - aie
 * 
 * When this bit is set, abnormal interrupt summary is enabled. When this bit is
 * reset, the abnormal interrupt summary is disabled. This bit enables the
 * following interrupts in Register 5 (Status Register):
 * 
 * * Register 5[1]: Transmit Process Stopped
 * 
 * * Register 5[3]: Transmit Jabber Timeout
 * 
 * * Register 5[4]: Receive Overflow
 * 
 * * Register 5[5]: Transmit Underflow
 * 
 * * Register 5[7]: Receive Buffer Unavailable
 * 
 * * Register 5[8]: Receive Process Stopped
 * 
 * * Register 5[9]: Receive Watchdog Timeout
 * 
 * * Register 5[10]: Early Transmit Interrupt
 * 
 * * Register 5[13]: Fatal Bus Error
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                                  
 * :-------------------------------|:------|:----------------------------------------------
 *  ALT_EMAC_DMA_INT_EN_AIE_E_DISD | 0x0   | Abnormal Interrupt Summary Interrupt Disabled
 *  ALT_EMAC_DMA_INT_EN_AIE_E_END  | 0x1   | Abnormal Interrupt Summary Interrupt Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_AIE
 * 
 * Abnormal Interrupt Summary Interrupt Disabled
 */
#define ALT_EMAC_DMA_INT_EN_AIE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_AIE
 * 
 * Abnormal Interrupt Summary Interrupt Enabled
 */
#define ALT_EMAC_DMA_INT_EN_AIE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_AIE register field. */
#define ALT_EMAC_DMA_INT_EN_AIE_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_AIE register field. */
#define ALT_EMAC_DMA_INT_EN_AIE_MSB        15
/* The width in bits of the ALT_EMAC_DMA_INT_EN_AIE register field. */
#define ALT_EMAC_DMA_INT_EN_AIE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_AIE register field value. */
#define ALT_EMAC_DMA_INT_EN_AIE_SET_MSK    0x00008000
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_AIE register field value. */
#define ALT_EMAC_DMA_INT_EN_AIE_CLR_MSK    0xffff7fff
/* The reset value of the ALT_EMAC_DMA_INT_EN_AIE register field. */
#define ALT_EMAC_DMA_INT_EN_AIE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_AIE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_AIE_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_EMAC_DMA_INT_EN_AIE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_AIE_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Normal Interrupt Summary Enable - nie
 * 
 * When this bit is set, normal interrupt summary is enabled. When this bit is
 * reset, normal interrupt summary is disabled. This bit enables the following
 * interrupts in Register 5 (Status Register):
 * 
 * * Register 5[0]: Transmit Interrupt
 * 
 * * Register 5[2]: Transmit Buffer Unavailable
 * 
 * * Register 5[6]: Receive Interrupt
 * 
 * * Register 5[14]: Early Receive Interrupt
 * 
 * Field Enumeration Values:
 * 
 *  Enum                           | Value | Description                      
 * :-------------------------------|:------|:----------------------------------
 *  ALT_EMAC_DMA_INT_EN_NIE_E_DISD | 0x0   | Normal Interrupt Summary Disabled
 *  ALT_EMAC_DMA_INT_EN_NIE_E_END  | 0x1   | Normal Interrupt Summary Enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_NIE
 * 
 * Normal Interrupt Summary Disabled
 */
#define ALT_EMAC_DMA_INT_EN_NIE_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_INT_EN_NIE
 * 
 * Normal Interrupt Summary Enabled
 */
#define ALT_EMAC_DMA_INT_EN_NIE_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_NIE register field. */
#define ALT_EMAC_DMA_INT_EN_NIE_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_NIE register field. */
#define ALT_EMAC_DMA_INT_EN_NIE_MSB        16
/* The width in bits of the ALT_EMAC_DMA_INT_EN_NIE register field. */
#define ALT_EMAC_DMA_INT_EN_NIE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_INT_EN_NIE register field value. */
#define ALT_EMAC_DMA_INT_EN_NIE_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_DMA_INT_EN_NIE register field value. */
#define ALT_EMAC_DMA_INT_EN_NIE_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_DMA_INT_EN_NIE register field. */
#define ALT_EMAC_DMA_INT_EN_NIE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_INT_EN_NIE field value from a register. */
#define ALT_EMAC_DMA_INT_EN_NIE_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_DMA_INT_EN_NIE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_INT_EN_NIE_SET(value) (((value) << 16) & 0x00010000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_INT_EN.
 */
struct ALT_EMAC_DMA_INT_EN_s
{
    uint32_t  tie :  1;  /* Transmit Interrupt Enable */
    uint32_t  tse :  1;  /* Transmit Stopped Enable */
    uint32_t  tue :  1;  /* Transmit Buffer Unvailable Enable */
    uint32_t  tje :  1;  /* Transmit Jabber Timeout Enable */
    uint32_t  ove :  1;  /* Overflow Interrupt Enable */
    uint32_t  une :  1;  /* Underflow Interrupt Enable */
    uint32_t  rie :  1;  /* Receive Interrupt Enable */
    uint32_t  rue :  1;  /* Receive Buffer Unavailable Enable */
    uint32_t  rse :  1;  /* Receive Stopped Enable */
    uint32_t  rwe :  1;  /* Receive Watchdog Timeout Enable */
    uint32_t  ete :  1;  /* Early Transmit Interrupt Enable */
    uint32_t      :  2;  /* *UNDEFINED* */
    uint32_t  fbe :  1;  /* Fatal Bus Error Enable */
    uint32_t  ere :  1;  /* Early Receive Interrupt Enable */
    uint32_t  aie :  1;  /* Abnormal Interrupt Summary Enable */
    uint32_t  nie :  1;  /* Normal Interrupt Summary Enable */
    uint32_t      : 15;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_DMA_INT_EN. */
typedef volatile struct ALT_EMAC_DMA_INT_EN_s  ALT_EMAC_DMA_INT_EN_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_INT_EN register from the beginning of the component. */
#define ALT_EMAC_DMA_INT_EN_OFST        0x1c
/* The address of the ALT_EMAC_DMA_INT_EN register. */
#define ALT_EMAC_DMA_INT_EN_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_INT_EN_OFST))

/*
 * Register : Register 8 (Missed Frame and Buffer Overflow Counter Register) - Missed_Frame_And_Buffer_Overflow_Counter
 * 
 * The DMA maintains two counters to track the number of frames missed during
 * reception. This register reports the current value of the counter. The counter
 * is used for diagnostic purposes. Bits[15:0] indicate missed frames because of
 * the host buffer being unavailable. Bits[27:17] indicate missed frames because of
 * buffer overflow conditions (MTL and MAC) and runt frames (good frames of less
 * than 64 bytes) dropped by the MTL.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                             
 * :--------|:-------|:------|:-----------------------------------------
 *  [15:0]  | R      | 0x0   | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT
 *  [16]    | R      | 0x0   | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF
 *  [27:17] | R      | 0x0   | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT
 *  [28]    | R      | 0x0   | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF
 *  [31:29] | ???    | 0x0   | *UNDEFINED*                             
 * 
 */
/*
 * Field : misfrmcnt
 * 
 * This field indicates the number of frames missed by the controller because of
 * the Host Receive Buffer being unavailable. This counter is incremented each time
 * the DMA discards an incoming frame. The counter is cleared when this register is
 * read with mci_be_i[0] at 1'b1.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_MSB        15
/* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_WIDTH      16
/* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET_MSK    0x0000ffff
/* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_CLR_MSK    0xffff0000
/* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_RESET      0x0
/* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT field value from a register. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_GET(value) (((value) & 0x0000ffff) >> 0)
/* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET(value) (((value) << 0) & 0x0000ffff)

/*
 * Field : miscntovf
 * 
 * Overflow bit for Missed Frame Counter
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_MSB        16
/* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF field value from a register. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : ovffrmcnt
 * 
 * This field indicates the number of frames missed by the application. This
 * counter is incremented each time the MTL asserts the sideband signal
 * mtl_rxoverflow_o. The counter is cleared when this register is read with
 * mci_be_i[2] at 1'b1.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_MSB        27
/* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_WIDTH      11
/* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET_MSK    0x0ffe0000
/* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_CLR_MSK    0xf001ffff
/* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_RESET      0x0
/* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT field value from a register. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_GET(value) (((value) & 0x0ffe0000) >> 17)
/* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET(value) (((value) << 17) & 0x0ffe0000)

/*
 * Field : ovfcntovf
 * 
 * Overflow bit for FIFO Overflow Counter
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_MSB        28
/* The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET_MSK    0x10000000
/* The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_CLR_MSK    0xefffffff
/* The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF field value from a register. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_GET(value) (((value) & 0x10000000) >> 28)
/* Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET(value) (((value) << 28) & 0x10000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR.
 */
struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s
{
    const uint32_t  misfrmcnt : 16;  /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT */
    const uint32_t  miscntovf :  1;  /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF */
    const uint32_t  ovffrmcnt : 11;  /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT */
    const uint32_t  ovfcntovf :  1;  /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF */
    uint32_t                  :  3;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR. */
typedef volatile struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s  ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register from the beginning of the component. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST        0x20
/* The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register. */
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST))

/*
 * Register : Register 9 (Receive Interrupt Watchdog Timer Register) - Receive_Interrupt_Watchdog_Timer
 * 
 * This register, when written with non-zero value, enables the watchdog timer for
 * the Receive Interrupt (Bit 6) of Register 5 (Status Register)
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description            
 * :-------|:-------|:------|:------------------------
 *  [7:0]  | RW     | 0x0   | RI Watchdog Timer Count
 *  [31:8] | ???    | 0x0   | *UNDEFINED*            
 * 
 */
/*
 * Field : RI Watchdog Timer Count - riwt
 * 
 * This bit indicates the number of system clock cycles multiplied by 256 for which
 * the watchdog timer is set. The watchdog timer gets triggered with the programmed
 * value after the Rx DMA completes the transfer of a frame for which the RI status
 * bit is not set because of the setting in the corresponding descriptor RDES1[31].
 * When the watchdog timer runs out, the RI bit is set and the timer is stopped.
 * The watchdog timer is reset when the RI bit is set high because of automatic
 * setting of RI as per RDES1[31] of any received frame.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_MSB        7
/* The width in bits of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_WIDTH      8
/* The mask used to set the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value. */
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET_MSK    0x000000ff
/* The mask used to clear the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value. */
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_CLR_MSK    0xffffff00
/* The reset value of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field. */
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_RESET      0x0
/* Extracts the ALT_EMAC_DMA_RX_INT_WDT_RIWT field value from a register. */
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_GET(value) (((value) & 0x000000ff) >> 0)
/* Produces a ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET(value) (((value) << 0) & 0x000000ff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_RX_INT_WDT.
 */
struct ALT_EMAC_DMA_RX_INT_WDT_s
{
    uint32_t  riwt :  8;  /* RI Watchdog Timer Count */
    uint32_t       : 24;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_DMA_RX_INT_WDT. */
typedef volatile struct ALT_EMAC_DMA_RX_INT_WDT_s  ALT_EMAC_DMA_RX_INT_WDT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_RX_INT_WDT register from the beginning of the component. */
#define ALT_EMAC_DMA_RX_INT_WDT_OFST        0x24
/* The address of the ALT_EMAC_DMA_RX_INT_WDT register. */
#define ALT_EMAC_DMA_RX_INT_WDT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_INT_WDT_OFST))

/*
 * Register : Register 10 (AXI Bus Mode Register) - AXI_Bus_Mode
 * 
 * The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly
 * used to control the burst splitting and the number of outstanding requests.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                               
 * :--------|:-------|:------|:-------------------------------------------
 *  [0]     | R      | 0x1   | AXI Undefined Burst Length                
 *  [1]     | RW     | 0x0   | AXI Burst Length 4                        
 *  [2]     | RW     | 0x0   | AXI Burst Length 8                        
 *  [3]     | RW     | 0x0   | AXI Burst Length 16                       
 *  [11:4]  | ???    | 0x0   | *UNDEFINED*                               
 *  [12]    | R      | 0x0   | Address-Aligned Beats                     
 *  [13]    | RW     | 0x0   | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE          
 *  [15:14] | ???    | 0x0   | *UNDEFINED*                               
 *  [19:16] | RW     | 0x1   | AXI Maximum Read OutStanding Request Limit
 *  [23:20] | RW     | 0x1   | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT       
 *  [29:24] | ???    | 0x0   | *UNDEFINED*                               
 *  [30]    | RW     | 0x0   | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM      
 *  [31]    | RW     | 0x0   | Enable Low Power Interface (LPI)          
 * 
 */
/*
 * Field : AXI Undefined Burst Length - undefined
 * 
 * This bit is read-only bit and indicates the complement (invert) value of Bit 16
 * (FB) in Register 0 (Bus Mode Register[16]).
 * 
 * * When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length
 *   equal to or below the maximum allowed burst length programmed in Bits[7:1].
 * 
 * * When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst
 *   lengths as indicated by BLEN16, BLEN8, or BLEN4, or a burst length of 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                
 * :------------------------------------------|:------|:----------------------------
 *  ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_DISD | 0x0   | Fixed Burst Lengths 4 to 32
 *  ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_END  | 0x1   | Any Burst Length up to max 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED
 * 
 * Fixed Burst Lengths 4 to 32
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED
 * 
 * Any Burst Length up to max
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_MSB        0
/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_RESET      0x1
/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED field value from a register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : AXI Burst Length 4 - blen4
 * 
 * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4
 * on the AXI Master interface.
 * 
 * Setting this bit has no effect when UNDEFINED is set to 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description             
 * :--------------------------------------|:------|:-------------------------
 *  ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_DISD | 0x0   | AXI No Fixed Busrts     
 *  ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_END  | 0x1   | AXI Fixed Burst BLEN = 4
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4
 * 
 * AXI No Fixed Busrts
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4
 * 
 * AXI Fixed Burst BLEN = 4
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_MSB        1
/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_RESET      0x0
/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 field value from a register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : AXI Burst Length 8 - blen8
 * 
 * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8
 * on the AXI Master interface.
 * 
 * Setting this bit has no effect when UNDEFINED is set to 1.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description             
 * :--------------------------------------|:------|:-------------------------
 *  ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_DISD | 0x0   | AXI No Fixed Busrts     
 *  ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_END  | 0x1   | AXI Fixed Burst BLEN = 8
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8
 * 
 * AXI No Fixed Busrts
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8
 * 
 * AXI Fixed Burst BLEN = 8
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_MSB        2
/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_RESET      0x0
/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 field value from a register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : AXI Burst Length 16 - blen16
 * 
 * When this bit is set to 1 or UNDEFINED is set to 1, the GMAC-AXI is allowed to
 * select a burst length of 16 on the AXI Master interface.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description              
 * :---------------------------------------|:------|:--------------------------
 *  ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_DISD | 0x0   | AXI No Fixed Busrts      
 *  ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_END  | 0x1   | AXI Fixed Burst BLEN = 16
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16
 * 
 * AXI No Fixed Busrts
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16
 * 
 * AXI Fixed Burst BLEN = 16
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_LSB        3
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_MSB        3
/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET_MSK    0x00000008
/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_CLR_MSK    0xfffffff7
/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_RESET      0x0
/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 field value from a register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_GET(value) (((value) & 0x00000008) >> 3)
/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET(value) (((value) << 3) & 0x00000008)

/*
 * Field : Address-Aligned Beats - axi_aal
 * 
 * This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode
 * Register).
 * 
 * When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers
 * on both read and write channels.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                    | Value | Description                
 * :----------------------------------------|:------|:----------------------------
 *  ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_DISD | 0x0   | No Address-Alignment Bursts
 *  ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_END  | 0x1   | Address-Alignmnet Bursts   
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL
 * 
 * No Address-Alignment Bursts
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL
 * 
 * Address-Alignmnet Bursts
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_MSB        12
/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET_MSK    0x00001000
/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_CLR_MSK    0xffffefff
/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_RESET      0x0
/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL field value from a register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : onekbbe
 * 
 * 1 KB Boundary Crossing Enable for the GMAC-AXI Master
 * 
 * When set, the GMAC-AXI Master performs burst transfers that do not cross 1 KB
 * boundary. When reset, the GMAC-AXI Master performs burst transfers that do not
 * cross 4 KB boundary.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                               | Value | Description
 * :---------------------------------------------------|:------|:------------
 *  ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_FOUR_K_BOUNDARY | 0x0   | 4K boundary
 *  ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_ONE_K_BOUNDARY  | 0x1   | 1K boundary
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE
 * 
 * 4K boundary
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_FOUR_K_BOUNDARY  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE
 * 
 * 1K boundary
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_ONE_K_BOUNDARY   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_MSB        13
/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE field value from a register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : AXI Maximum Read OutStanding Request Limit - rd_osr_lmt
 * 
 * This value limits the maximum outstanding request on the AXI read interface.
 * 
 * Maximum outstanding requests = RD_OSR_LMT+1
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_MSB        19
/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_WIDTH      4
/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET_MSK    0x000f0000
/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_CLR_MSK    0xfff0ffff
/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_RESET      0x1
/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT field value from a register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_GET(value) (((value) & 0x000f0000) >> 16)
/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET(value) (((value) << 16) & 0x000f0000)

/*
 * Field : wr_osr_lmt
 * 
 * AXI Maximum Write OutStanding Request Limit
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_MSB        23
/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_WIDTH      4
/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET_MSK    0x00f00000
/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_CLR_MSK    0xff0fffff
/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_RESET      0x1
/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT field value from a register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_GET(value) (((value) & 0x00f00000) >> 20)
/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET(value) (((value) << 20) & 0x00f00000)

/*
 * Field : lpi_xit_frm
 * 
 * When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only
 * when the Magic Packet or Remote Wake Up Packet is received.
 * 
 * When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any
 * frame is received.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                           
 * :--------------------------------------------|:------|:---------------------------------------
 *  ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_DISD | 0x0   | Do Not exit LPI Mode with Magic Packet
 *  ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_END  | 0x1   | Exit LPI Mode with Magic Packet       
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM
 * 
 * Do Not exit LPI Mode with Magic Packet
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM
 * 
 * Exit LPI Mode with Magic Packet
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_LSB        30
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_MSB        30
/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET_MSK    0x40000000
/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_CLR_MSK    0xbfffffff
/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_RESET      0x0
/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM field value from a register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_GET(value) (((value) & 0x40000000) >> 30)
/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET(value) (((value) << 30) & 0x40000000)

/*
 * Field : Enable Low Power Interface (LPI) - en_lpi
 * 
 * When set to 1, this bit enables the LPI mode supported by the AXI master and
 * accepts the LPI request from the AXI System Clock controller.
 * 
 * When set to 0, this bit disables the LPI mode and always denies the LPI request
 * from the AXI System Clock controller.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description     
 * :---------------------------------------|:------|:-----------------
 *  ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_DISD | 0x0   | Disable LPI Mode
 *  ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_END  | 0x1   | Enable LPI Mode 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI
 * 
 * Disable LPI Mode
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI
 * 
 * Enable LPI Mode
 */
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_LSB        31
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_MSB        31
/* The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET_MSK    0x80000000
/* The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_CLR_MSK    0x7fffffff
/* The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_RESET      0x0
/* Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI field value from a register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_GET(value) (((value) & 0x80000000) >> 31)
/* Produces a ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET(value) (((value) << 31) & 0x80000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_AXI_BUS_MOD.
 */
struct ALT_EMAC_DMA_AXI_BUS_MOD_s
{
    const uint32_t  undefined   :  1;  /* AXI Undefined Burst Length */
    uint32_t        blen4       :  1;  /* AXI Burst Length 4 */
    uint32_t        blen8       :  1;  /* AXI Burst Length 8 */
    uint32_t        blen16      :  1;  /* AXI Burst Length 16 */
    uint32_t                    :  8;  /* *UNDEFINED* */
    const uint32_t  axi_aal     :  1;  /* Address-Aligned Beats */
    uint32_t        onekbbe     :  1;  /* ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE */
    uint32_t                    :  2;  /* *UNDEFINED* */
    uint32_t        rd_osr_lmt  :  4;  /* AXI Maximum Read OutStanding Request Limit */
    uint32_t        wr_osr_lmt  :  4;  /* ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT */
    uint32_t                    :  6;  /* *UNDEFINED* */
    uint32_t        lpi_xit_frm :  1;  /* ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM */
    uint32_t        en_lpi      :  1;  /* Enable Low Power Interface (LPI) */
};

/* The typedef declaration for register ALT_EMAC_DMA_AXI_BUS_MOD. */
typedef volatile struct ALT_EMAC_DMA_AXI_BUS_MOD_s  ALT_EMAC_DMA_AXI_BUS_MOD_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_AXI_BUS_MOD register from the beginning of the component. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_OFST        0x28
/* The address of the ALT_EMAC_DMA_AXI_BUS_MOD register. */
#define ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AXI_BUS_MOD_OFST))

/*
 * Register : Register 11 (AHB or AXI Status Register) - AHB_or_AXI_Status
 * 
 * This register provides the active status of the AXI interface's read and write
 * channels. This register is useful for debugging purposes. In addition, this
 * register is valid only in the Channel 0 DMA when multiple channels are present
 * in the AV mode.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                    
 * :-------|:-------|:------|:--------------------------------
 *  [0]    | R      | 0x0   | AXI Master Write Channel Status
 *  [1]    | R      | 0x0   | AXI Master Read Channel Status 
 *  [31:2] | ???    | 0x0   | *UNDEFINED*                    
 * 
 */
/*
 * Field : AXI Master Write Channel Status - axwhsts
 * 
 * When high, it indicates that AXI Master's write channel is active and
 * transferring data
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_MSB        0
/* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_RESET      0x0
/* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS field value from a register. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : AXI Master Read Channel Status - axirdsts
 * 
 * When high, it indicates that AXI Master's read channel is active and
 * transferring data.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_MSB        1
/* The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_RESET      0x0
/* Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS field value from a register. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value suitable for setting the register. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET(value) (((value) << 1) & 0x00000002)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STAT.
 */
struct ALT_EMAC_DMA_AHB_OR_AXI_STAT_s
{
    const uint32_t  axwhsts  :  1;  /* AXI Master Write Channel Status */
    const uint32_t  axirdsts :  1;  /* AXI Master Read Channel Status */
    uint32_t                 : 30;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STAT. */
typedef volatile struct ALT_EMAC_DMA_AHB_OR_AXI_STAT_s  ALT_EMAC_DMA_AHB_OR_AXI_STAT_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register from the beginning of the component. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST        0x2c
/* The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register. */
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST))

/*
 * Register : Register 18 (Current Host Transmit Descriptor Register) - Current_Host_Transmit_Descriptor
 * 
 * The Current Host Transmit Descriptor register points to the start address of the
 * current Transmit Descriptor read by the DMA.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                             
 * :-------|:-------|:------|:-----------------------------------------
 *  [31:0] | R      | 0x0   | Host Transmit Descriptor Address Pointer
 * 
 */
/*
 * Field : Host Transmit Descriptor Address Pointer - curtdesaptr
 * 
 * Cleared on Reset. Pointer updated by the DMA during operation.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_MSB        31
/* The width in bits of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_WIDTH      32
/* The mask used to set the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value. */
#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value. */
#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_RESET      0x0
/* Extracts the ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR field value from a register. */
#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR register field value suitable for setting the register. */
#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_CURTDESAPTR_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_TX_DESC.
 */
struct ALT_EMAC_DMA_CUR_HOST_TX_DESC_s
{
    const uint32_t  curtdesaptr : 32;  /* Host Transmit Descriptor Address Pointer */
};

/* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_TX_DESC. */
typedef volatile struct ALT_EMAC_DMA_CUR_HOST_TX_DESC_s  ALT_EMAC_DMA_CUR_HOST_TX_DESC_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register from the beginning of the component. */
#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_OFST        0x48
/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_DESC register. */
#define ALT_EMAC_DMA_CUR_HOST_TX_DESC_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_TX_DESC_OFST))

/*
 * Register : Register 19 (Current Host Receive Descriptor Register) - Current_Host_Receive_Descriptor
 * 
 * The Current Host Receive Descriptor register points to the start address of the
 * current Receive Descriptor read by the DMA.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                            
 * :-------|:-------|:------|:----------------------------------------
 *  [31:0] | R      | 0x0   | Host Receive Descriptor Address Pointer
 * 
 */
/*
 * Field : Host Receive Descriptor Address Pointer - currdesaptr
 * 
 * Cleared on Reset. Pointer updated by the DMA during operation.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_MSB        31
/* The width in bits of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_WIDTH      32
/* The mask used to set the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value. */
#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value. */
#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_RESET      0x0
/* Extracts the ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR field value from a register. */
#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR register field value suitable for setting the register. */
#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_CURRDESAPTR_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_RX_DESC.
 */
struct ALT_EMAC_DMA_CUR_HOST_RX_DESC_s
{
    const uint32_t  currdesaptr : 32;  /* Host Receive Descriptor Address Pointer */
};

/* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_RX_DESC. */
typedef volatile struct ALT_EMAC_DMA_CUR_HOST_RX_DESC_s  ALT_EMAC_DMA_CUR_HOST_RX_DESC_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register from the beginning of the component. */
#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_OFST        0x4c
/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_DESC register. */
#define ALT_EMAC_DMA_CUR_HOST_RX_DESC_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_RX_DESC_OFST))

/*
 * Register : Register 20 (Current Host Transmit Buffer Address Register) - Current_Host_Transmit_Buffer_Address
 * 
 * The Current Host Transmit Buffer Address register points to the current Transmit
 * Buffer Address being read by the DMA.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                         
 * :-------|:-------|:------|:-------------------------------------
 *  [31:0] | R      | 0x0   | Host Transmit Buffer Address Pointer
 * 
 */
/*
 * Field : Host Transmit Buffer Address Pointer - curtbufaptr
 * 
 * Cleared on Reset. Pointer updated by the DMA during operation.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_MSB        31
/* The width in bits of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_WIDTH      32
/* The mask used to set the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value. */
#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value. */
#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_RESET      0x0
/* Extracts the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR field value from a register. */
#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR register field value suitable for setting the register. */
#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_CURTBUFAPTR_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR.
 */
struct ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_s
{
    const uint32_t  curtbufaptr : 32;  /* Host Transmit Buffer Address Pointer */
};

/* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR. */
typedef volatile struct ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_s  ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register from the beginning of the component. */
#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_OFST        0x50
/* The address of the ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR register. */
#define ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_OFST))

/*
 * Register : Register 21 (Current Host Receive Buffer Address Register) - Current_Host_Receive_Buffer_Address
 * 
 * The Current Host Receive Buffer Address register points to the current Receive
 * Buffer address being read by the DMA.
 * 
 * Register Layout
 * 
 *  Bits   | Access | Reset | Description                        
 * :-------|:-------|:------|:------------------------------------
 *  [31:0] | R      | 0x0   | Host Receive Buffer Address Pointer
 * 
 */
/*
 * Field : Host Receive Buffer Address Pointer - currbufaptr
 * 
 * Cleared on Reset. Pointer updated by the DMA during operation.
 * 
 * Field Access Macros:
 * 
 */
/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_MSB        31
/* The width in bits of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_WIDTH      32
/* The mask used to set the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value. */
#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_SET_MSK    0xffffffff
/* The mask used to clear the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value. */
#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_CLR_MSK    0x00000000
/* The reset value of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field. */
#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_RESET      0x0
/* Extracts the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR field value from a register. */
#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_GET(value) (((value) & 0xffffffff) >> 0)
/* Produces a ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR register field value suitable for setting the register. */
#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_CURRBUFAPTR_SET(value) (((value) << 0) & 0xffffffff)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR.
 */
struct ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_s
{
    const uint32_t  currbufaptr : 32;  /* Host Receive Buffer Address Pointer */
};

/* The typedef declaration for register ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR. */
typedef volatile struct ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_s  ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register from the beginning of the component. */
#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_OFST        0x54
/* The address of the ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR register. */
#define ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_OFST))

/*
 * Register : Register 22 (HW Feature Register) - HW_Feature
 * 
 * This register indicates the presence of the optional features or functions of
 * the gmac. The software driver can use this register to dynamically enable or
 * disable the programs related to the optional blocks.
 * 
 * Register Layout
 * 
 *  Bits    | Access | Reset | Description                  
 * :--------|:-------|:------|:------------------------------
 *  [0]     | R      | 0x1   | MII Selection                
 *  [1]     | R      | 0x1   | GMII Selection               
 *  [2]     | R      | 0x1   | Half Duplex Selection        
 *  [3]     | ???    | 0x0   | *UNDEFINED*                  
 *  [4]     | R      | 0x1   | Hash Filter                  
 *  [5]     | R      | 0x1   | Multiple MAC Address Register
 *  [6]     | R      | 0x0   | PCS Select                   
 *  [7]     | ???    | 0x0   | *UNDEFINED*                  
 *  [8]     | R      | 0x1   | SMA Select                   
 *  [9]     | R      | 0x1   | RWK Select                   
 *  [10]    | R      | 0x1   | MGK Select                   
 *  [11]    | R      | 0x1   | MMC Select                   
 *  [12]    | R      | 0x1   | TS Version1 Select           
 *  [13]    | R      | 0x1   | TS Version2 Select           
 *  [14]    | R      | 0x1   | Energy Efficient Ethernet    
 *  [15]    | R      | 0x0   | AV Select                    
 *  [16]    | R      | 0x1   | Tx Offload Checksum          
 *  [17]    | R      | 0x0   | Rx Type 1 Checksum Offload   
 *  [18]    | R      | 0x1   | Rx Type 2 Checksum Offload   
 *  [19]    | R      | 0x1   | Rx FIFO Size                 
 *  [21:20] | R      | 0x0   | Rx Channel Count             
 *  [23:22] | R      | 0x0   | Tx Channel Count             
 *  [24]    | R      | 0x1   | Enhanced Descriptor Select   
 *  [27:25] | ???    | 0x0   | *UNDEFINED*                  
 *  [30:28] | R      | 0x0   | Selected PHY Interface       
 *  [31]    | ???    | 0x0   | *UNDEFINED*                  
 * 
 */
/*
 * Field : MII Selection - miisel
 * 
 * 10/100 Mbps support
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                 
 * :--------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD | 0x0   | 10 Mbps or 100 Mbps disabled
 *  ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END  | 0x1   | 10 Mbps or 100 Mbps  enabled
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MIISEL
 * 
 * 10 Mbps or 100 Mbps disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MIISEL
 * 
 * 10 Mbps or 100 Mbps  enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_LSB        0
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_MSB        0
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET_MSK    0x00000001
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_CLR_MSK    0xfffffffe
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_MIISEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_GET(value) (((value) & 0x00000001) >> 0)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET(value) (((value) << 0) & 0x00000001)

/*
 * Field : GMII Selection - gmiisel
 * 
 * 1000 Mbps support
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description       
 * :---------------------------------------|:------|:-------------------
 *  ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD | 0x0   | 1000 Mbps disabled
 *  ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END  | 0x1   | 1000 Mbps enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_GMIISEL
 * 
 * 1000 Mbps disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_GMIISEL
 * 
 * 1000 Mbps enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_LSB        1
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_MSB        1
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET_MSK    0x00000002
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_CLR_MSK    0xfffffffd
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_GMIISEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_GET(value) (((value) & 0x00000002) >> 1)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET(value) (((value) << 1) & 0x00000002)

/*
 * Field : Half Duplex Selection - hdsel
 * 
 * Half-Duplex support
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description         
 * :-------------------------------------|:------|:---------------------
 *  ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD | 0x0   | Half Duplex disabled
 *  ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END  | 0x1   | Half Duplex enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HDSEL
 * 
 * Half Duplex disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HDSEL
 * 
 * Half Duplex enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_LSB        2
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_MSB        2
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET_MSK    0x00000004
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_CLR_MSK    0xfffffffb
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_HDSEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_GET(value) (((value) & 0x00000004) >> 2)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET(value) (((value) << 2) & 0x00000004)

/*
 * Field : Hash Filter - hashsel
 * 
 * HASH Filter support
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description         
 * :---------------------------------------|:------|:---------------------
 *  ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD | 0x0   | Hash Filter disabled
 *  ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END  | 0x1   | Hash Filter enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HASHSEL
 * 
 * Hash Filter disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HASHSEL
 * 
 * Hash Filter enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_LSB        4
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_MSB        4
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET_MSK    0x00000010
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_CLR_MSK    0xffffffef
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_HASHSEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_GET(value) (((value) & 0x00000010) >> 4)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET(value) (((value) << 4) & 0x00000010)

/*
 * Field : Multiple MAC Address Register - addmacadrsel
 * 
 * Multiple MAC Address Registers support
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description                            
 * :--------------------------------------------|:------|:----------------------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD | 0x0   | Multiple MAC Address registers disabled
 *  ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END  | 0x1   | Multiple MAC Address registers enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL
 * 
 * Multiple MAC Address registers disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD 0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL
 * 
 * Multiple MAC Address registers enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END  0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_LSB        5
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_MSB        5
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET_MSK    0x00000020
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_CLR_MSK    0xffffffdf
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_GET(value) (((value) & 0x00000020) >> 5)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET(value) (((value) << 5) & 0x00000020)

/*
 * Field : PCS Select - pcssel
 * 
 * TBI/SGMII/RTBI PHY interface support
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description         
 * :--------------------------------------|:------|:---------------------
 *  ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD | 0x0   | PCS Support disabled
 *  ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END  | 0x1   | PCS Support enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_PCSSEL
 * 
 * PCS Support disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_PCSSEL
 * 
 * PCS Support enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_LSB        6
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_MSB        6
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET_MSK    0x00000040
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_CLR_MSK    0xffffffbf
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_RESET      0x0
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_PCSSEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_GET(value) (((value) & 0x00000040) >> 6)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET(value) (((value) << 6) & 0x00000040)

/*
 * Field : SMA Select - smasel
 * 
 * SMA (MDIO) Interface support
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                   
 * :--------------------------------------|:------|:-------------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD | 0x0   | SMA Interface Support disabled
 *  ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END  | 0x1   | SMA Interface Support enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_SMASEL
 * 
 * SMA Interface Support disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_SMASEL
 * 
 * SMA Interface Support enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_LSB        8
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_MSB        8
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET_MSK    0x00000100
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_CLR_MSK    0xfffffeff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_SMASEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_GET(value) (((value) & 0x00000100) >> 8)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET(value) (((value) << 8) & 0x00000100)

/*
 * Field : RWK Select - rwksel
 * 
 * PMT Remote Wakeup support
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                
 * :--------------------------------------|:------|:----------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD | 0x0   | PMT Remote Wake Up disabled
 *  ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END  | 0x1   | PMT Remote Wake Up enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RWKSEL
 * 
 * PMT Remote Wake Up disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RWKSEL
 * 
 * PMT Remote Wake Up enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_LSB        9
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_MSB        9
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET_MSK    0x00000200
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_CLR_MSK    0xfffffdff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_RWKSEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_GET(value) (((value) & 0x00000200) >> 9)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET(value) (((value) << 9) & 0x00000200)

/*
 * Field : MGK Select - mgksel
 * 
 * PMT Magic Packet
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description              
 * :--------------------------------------|:------|:--------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD | 0x0   | PMT Magic Packet disabled
 *  ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END  | 0x1   | PMT Magic Packet enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MGKSEL
 * 
 * PMT Magic Packet disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MGKSEL
 * 
 * PMT Magic Packet enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_LSB        10
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_MSB        10
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET_MSK    0x00000400
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_CLR_MSK    0xfffffbff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_MGKSEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_GET(value) (((value) & 0x00000400) >> 10)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET(value) (((value) << 10) & 0x00000400)

/*
 * Field : MMC Select - mmcsel
 * 
 * RMON block
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description        
 * :--------------------------------------|:------|:--------------------
 *  ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD | 0x0   | Rmon block disabled
 *  ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END  | 0x1   | Rmon block enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MMCSEL
 * 
 * Rmon block disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MMCSEL
 * 
 * Rmon block enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_LSB        11
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_MSB        11
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET_MSK    0x00000800
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_CLR_MSK    0xfffff7ff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_MMCSEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_GET(value) (((value) & 0x00000800) >> 11)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET(value) (((value) << 11) & 0x00000800)

/*
 * Field : TS Version1 Select - tsver1sel
 * 
 * Only IEEE 1588-2002 Timestamp
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD | 0x0   | TS Version1 Select disabled
 *  ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END  | 0x1   | TS Version1 Select enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL
 * 
 * TS Version1 Select disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL
 * 
 * TS Version1 Select enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_LSB        12
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_MSB        12
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET_MSK    0x00001000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_CLR_MSK    0xffffefff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_GET(value) (((value) & 0x00001000) >> 12)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET(value) (((value) << 12) & 0x00001000)

/*
 * Field : TS Version2 Select - tsver2sel
 * 
 * IEEE 1588-2008 Advanced Timestamp
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                
 * :-----------------------------------------|:------|:----------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD | 0x0   | TS Version2 Select disabled
 *  ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END  | 0x1   | TS Version2 Select enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL
 * 
 * TS Version2 Select disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL
 * 
 * TS Version2 Select enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_LSB        13
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_MSB        13
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET_MSK    0x00002000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_CLR_MSK    0xffffdfff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_GET(value) (((value) & 0x00002000) >> 13)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET(value) (((value) << 13) & 0x00002000)

/*
 * Field : Energy Efficient Ethernet - eeesel
 * 
 * Energy Efficient Ethernet Feature
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                  | Value | Description                       
 * :--------------------------------------|:------|:-----------------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD | 0x0   | Energy Efficient Ethernet disabled
 *  ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END  | 0x1   | Energy Efficient Ethernet enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_EEESEL
 * 
 * Energy Efficient Ethernet disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_EEESEL
 * 
 * Energy Efficient Ethernet enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_LSB        14
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_MSB        14
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET_MSK    0x00004000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_CLR_MSK    0xffffbfff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_EEESEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_GET(value) (((value) & 0x00004000) >> 14)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET(value) (((value) << 14) & 0x00004000)

/*
 * Field : AV Select - avsel
 * 
 * AV Feature
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                 | Value | Description       
 * :-------------------------------------|:------|:-------------------
 *  ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD | 0x0   | AV Select disabled
 *  ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END  | 0x1   | AV Select enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_AVSEL
 * 
 * AV Select disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_AVSEL
 * 
 * AV Select enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_LSB        15
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_MSB        15
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET_MSK    0x00008000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_CLR_MSK    0xffff7fff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_RESET      0x0
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_AVSEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_GET(value) (((value) & 0x00008000) >> 15)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET(value) (((value) << 15) & 0x00008000)

/*
 * Field : Tx Offload Checksum - txoesel
 * 
 * Checksum Offload in Tx
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description                 
 * :---------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD | 0x0   | Tx Offload Checksum disabled
 *  ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END  | 0x1   | Tx Offload Checksum enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXOESEL
 * 
 * Tx Offload Checksum disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXOESEL
 * 
 * Tx Offload Checksum enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_LSB        16
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_MSB        16
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET_MSK    0x00010000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_CLR_MSK    0xfffeffff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_TXOESEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_GET(value) (((value) & 0x00010000) >> 16)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET(value) (((value) << 16) & 0x00010000)

/*
 * Field : Rx Type 1 Checksum Offload - rxtyp1coe
 * 
 * IP Checksum Offload (Type 1) in Rx
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                        
 * :-----------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD | 0x0   | Rx Type 1 Checksum Offload disabled
 *  ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END  | 0x1   | Rx Type 1 Checksum Offload enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE
 * 
 * Rx Type 1 Checksum Offload disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE
 * 
 * Rx Type 1 Checksum Offload enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_LSB        17
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_MSB        17
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET_MSK    0x00020000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_CLR_MSK    0xfffdffff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_RESET      0x0
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_GET(value) (((value) & 0x00020000) >> 17)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET(value) (((value) << 17) & 0x00020000)

/*
 * Field : Rx Type 2 Checksum Offload - rxtyp2coe
 * 
 * IP Checksum Offload (Type 2) in Rx
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                        
 * :-----------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD | 0x0   | Rx Type 2 Checksum Offload disabled
 *  ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END  | 0x1   | Rx Type 2 Checksum Offload enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE
 * 
 * Rx Type 2 Checksum Offload disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE
 * 
 * Rx Type 2 Checksum Offload enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_LSB        18
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_MSB        18
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET_MSK    0x00040000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_CLR_MSK    0xfffbffff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_GET(value) (((value) & 0x00040000) >> 18)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET(value) (((value) << 18) & 0x00040000)

/*
 * Field : Rx FIFO Size - rxfifosize
 * 
 * RxFIFO > 2048 Bytes
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                      | Value | Description                 
 * :------------------------------------------|:------|:-----------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD | 0x0   | RxFIFO > 2048 bytes disabled
 *  ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END  | 0x1   | RxFIFO > 2048 bytes enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE
 * 
 * RxFIFO > 2048 bytes disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD   0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE
 * 
 * RxFIFO > 2048 bytes enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END    0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_LSB        19
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_MSB        19
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET_MSK    0x00080000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_CLR_MSK    0xfff7ffff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_GET(value) (((value) & 0x00080000) >> 19)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET(value) (((value) << 19) & 0x00080000)

/*
 * Field : Rx Channel Count - rxchcnt
 * 
 * Number of additional Rx channels
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description              
 * :---------------------------------------|:------|:--------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD | 0x0   | Rx Channel Count disabled
 *  ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END  | 0x1   | Rx Channel Count enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXCHCNT
 * 
 * Rx Channel Count disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXCHCNT
 * 
 * Rx Channel Count enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_LSB        20
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_MSB        21
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_WIDTH      2
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET_MSK    0x00300000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_CLR_MSK    0xffcfffff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field. */
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_RESET      0x0
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_GET(value) (((value) & 0x00300000) >> 20)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET(value) (((value) << 20) & 0x00300000)

/*
 * Field : Tx Channel Count - txchcnt
 * 
 * Number of additional Tx channels
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                   | Value | Description              
 * :---------------------------------------|:------|:--------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD | 0x0   | Tx Channel Count disabled
 *  ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END  | 0x1   | Tx Channel Count enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXCHCNT
 * 
 * Tx Channel Count disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD  0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXCHCNT
 * 
 * Tx Channel Count enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END   0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_LSB        22
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_MSB        23
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_WIDTH      2
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET_MSK    0x00c00000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_CLR_MSK    0xff3fffff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field. */
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_RESET      0x0
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_GET(value) (((value) & 0x00c00000) >> 22)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET(value) (((value) << 22) & 0x00c00000)

/*
 * Field : Enhanced Descriptor Select - enhdessel
 * 
 * Alternate (Enhanced Descriptor)
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                     | Value | Description                        
 * :-----------------------------------------|:------|:------------------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD | 0x0   | Enhanced Descriptor Select disabled
 *  ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END  | 0x1   | Enhanced Descriptor Select enabled 
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL
 * 
 * Enhanced Descriptor Select disabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD    0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL
 * 
 * Enhanced Descriptor Select enabled
 */
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END     0x1

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_LSB        24
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_MSB        24
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_WIDTH      1
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET_MSK    0x01000000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_CLR_MSK    0xfeffffff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_RESET      0x1
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_GET(value) (((value) & 0x01000000) >> 24)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET(value) (((value) << 24) & 0x01000000)

/*
 * Field : Selected PHY Interface - actphyif
 * 
 * When you have multiple PHY interfaces in your configuration, this field
 * indicates the sampled value of emacx_phy_if_selduring reset de-assertion.
 * 
 * Field Enumeration Values:
 * 
 *  Enum                                        | Value | Description              
 * :--------------------------------------------|:------|:--------------------------
 *  ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0 | 0x0   | Sampled Value GMII or MII
 *  ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1   | 0x1   | Sampled Value RGMII      
 *  ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2   | 0x2   | Sampled Value SGMII      
 *  ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3     | 0x3   | Sampled Value TBI        
 *  ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4    | 0x4   | Sampled Value RMII       
 *  ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5    | 0x5   | Sampled Value RTBI       
 *  ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6    | 0x6   | Sampled Value SMII       
 *  ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7  | 0x7   | Sampled Value RevMII     
 * 
 * Field Access Macros:
 * 
 */
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
 * 
 * Sampled Value GMII or MII
 */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0 0x0
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
 * 
 * Sampled Value RGMII
 */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1   0x1
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
 * 
 * Sampled Value SGMII
 */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2   0x2
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
 * 
 * Sampled Value TBI
 */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3     0x3
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
 * 
 * Sampled Value RMII
 */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4    0x4
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
 * 
 * Sampled Value RTBI
 */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5    0x5
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
 * 
 * Sampled Value SMII
 */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6    0x6
/*
 * Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF
 * 
 * Sampled Value RevMII
 */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7  0x7

/* The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_LSB        28
/* The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_MSB        30
/* The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_WIDTH      3
/* The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET_MSK    0x70000000
/* The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value. */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_CLR_MSK    0x8fffffff
/* The reset value of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field. */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_RESET      0x0
/* Extracts the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF field value from a register. */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_GET(value) (((value) & 0x70000000) >> 28)
/* Produces a ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value suitable for setting the register. */
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET(value) (((value) << 28) & 0x70000000)

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register ALT_EMAC_DMA_HW_FEATURE.
 */
struct ALT_EMAC_DMA_HW_FEATURE_s
{
    const uint32_t  miisel       :  1;  /* MII Selection */
    const uint32_t  gmiisel      :  1;  /* GMII Selection */
    const uint32_t  hdsel        :  1;  /* Half Duplex Selection */
    uint32_t                     :  1;  /* *UNDEFINED* */
    const uint32_t  hashsel      :  1;  /* Hash Filter */
    const uint32_t  addmacadrsel :  1;  /* Multiple MAC Address Register */
    const uint32_t  pcssel       :  1;  /* PCS Select */
    uint32_t                     :  1;  /* *UNDEFINED* */
    const uint32_t  smasel       :  1;  /* SMA Select */
    const uint32_t  rwksel       :  1;  /* RWK Select */
    const uint32_t  mgksel       :  1;  /* MGK Select */
    const uint32_t  mmcsel       :  1;  /* MMC Select */
    const uint32_t  tsver1sel    :  1;  /* TS Version1 Select */
    const uint32_t  tsver2sel    :  1;  /* TS Version2 Select */
    const uint32_t  eeesel       :  1;  /* Energy Efficient Ethernet */
    const uint32_t  avsel        :  1;  /* AV Select */
    const uint32_t  txoesel      :  1;  /* Tx Offload Checksum */
    const uint32_t  rxtyp1coe    :  1;  /* Rx Type 1 Checksum Offload */
    const uint32_t  rxtyp2coe    :  1;  /* Rx Type 2 Checksum Offload */
    const uint32_t  rxfifosize   :  1;  /* Rx FIFO Size */
    const uint32_t  rxchcnt      :  2;  /* Rx Channel Count */
    const uint32_t  txchcnt      :  2;  /* Tx Channel Count */
    const uint32_t  enhdessel    :  1;  /* Enhanced Descriptor Select */
    uint32_t                     :  3;  /* *UNDEFINED* */
    const uint32_t  actphyif     :  3;  /* Selected PHY Interface */
    uint32_t                     :  1;  /* *UNDEFINED* */
};

/* The typedef declaration for register ALT_EMAC_DMA_HW_FEATURE. */
typedef volatile struct ALT_EMAC_DMA_HW_FEATURE_s  ALT_EMAC_DMA_HW_FEATURE_t;
#endif  /* __ASSEMBLY__ */

/* The byte offset of the ALT_EMAC_DMA_HW_FEATURE register from the beginning of the component. */
#define ALT_EMAC_DMA_HW_FEATURE_OFST        0x58
/* The address of the ALT_EMAC_DMA_HW_FEATURE register. */
#define ALT_EMAC_DMA_HW_FEATURE_ADDR(base)  ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_HW_FEATURE_OFST))

#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register group ALT_EMAC_DMA.
 */
struct ALT_EMAC_DMA_s
{
    volatile ALT_EMAC_DMA_BUS_MOD_t               Bus_Mode;                                  /* ALT_EMAC_DMA_BUS_MOD */
    volatile ALT_EMAC_DMA_TX_POLL_DEMAND_t        Transmit_Poll_Demand;                      /* ALT_EMAC_DMA_TX_POLL_DEMAND */
    volatile ALT_EMAC_DMA_RX_POLL_DEMAND_t        Receive_Poll_Demand;                       /* ALT_EMAC_DMA_RX_POLL_DEMAND */
    volatile ALT_EMAC_DMA_RX_DESC_LIST_ADDR_t     Receive_Descriptor_List_Address;           /* ALT_EMAC_DMA_RX_DESC_LIST_ADDR */
    volatile ALT_EMAC_DMA_TX_DESC_LIST_ADDR_t     Transmit_Descriptor_List_Address;          /* ALT_EMAC_DMA_TX_DESC_LIST_ADDR */
    volatile ALT_EMAC_DMA_STAT_t                  Status;                                    /* ALT_EMAC_DMA_STAT */
    volatile ALT_EMAC_DMA_OP_MOD_t                Operation_Mode;                            /* ALT_EMAC_DMA_OP_MOD */
    volatile ALT_EMAC_DMA_INT_EN_t                Interrupt_Enable;                          /* ALT_EMAC_DMA_INT_EN */
    volatile ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_t     Missed_Frame_And_Buffer_Overflow_Counter;  /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR */
    volatile ALT_EMAC_DMA_RX_INT_WDT_t            Receive_Interrupt_Watchdog_Timer;          /* ALT_EMAC_DMA_RX_INT_WDT */
    volatile ALT_EMAC_DMA_AXI_BUS_MOD_t           AXI_Bus_Mode;                              /* ALT_EMAC_DMA_AXI_BUS_MOD */
    volatile ALT_EMAC_DMA_AHB_OR_AXI_STAT_t       AHB_or_AXI_Status;                         /* ALT_EMAC_DMA_AHB_OR_AXI_STAT */
    volatile uint32_t                             _pad_0x30_0x47[6];                         /* *UNDEFINED* */
    volatile ALT_EMAC_DMA_CUR_HOST_TX_DESC_t      Current_Host_Transmit_Descriptor;          /* ALT_EMAC_DMA_CUR_HOST_TX_DESC */
    volatile ALT_EMAC_DMA_CUR_HOST_RX_DESC_t      Current_Host_Receive_Descriptor;           /* ALT_EMAC_DMA_CUR_HOST_RX_DESC */
    volatile ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR_t  Current_Host_Transmit_Buffer_Address;      /* ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR */
    volatile ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR_t  Current_Host_Receive_Buffer_Address;       /* ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR */
    volatile ALT_EMAC_DMA_HW_FEATURE_t            HW_Feature;                                /* ALT_EMAC_DMA_HW_FEATURE */
};

/* The typedef declaration for register group ALT_EMAC_DMA. */
typedef volatile struct ALT_EMAC_DMA_s  ALT_EMAC_DMA_t;
/* The struct declaration for the raw register contents of register group ALT_EMAC_DMA. */
struct ALT_EMAC_DMA_raw_s
{
    volatile uint32_t  Bus_Mode;                                  /* ALT_EMAC_DMA_BUS_MOD */
    volatile uint32_t  Transmit_Poll_Demand;                      /* ALT_EMAC_DMA_TX_POLL_DEMAND */
    volatile uint32_t  Receive_Poll_Demand;                       /* ALT_EMAC_DMA_RX_POLL_DEMAND */
    volatile uint32_t  Receive_Descriptor_List_Address;           /* ALT_EMAC_DMA_RX_DESC_LIST_ADDR */
    volatile uint32_t  Transmit_Descriptor_List_Address;          /* ALT_EMAC_DMA_TX_DESC_LIST_ADDR */
    volatile uint32_t  Status;                                    /* ALT_EMAC_DMA_STAT */
    volatile uint32_t  Operation_Mode;                            /* ALT_EMAC_DMA_OP_MOD */
    volatile uint32_t  Interrupt_Enable;                          /* ALT_EMAC_DMA_INT_EN */
    volatile uint32_t  Missed_Frame_And_Buffer_Overflow_Counter;  /* ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR */
    volatile uint32_t  Receive_Interrupt_Watchdog_Timer;          /* ALT_EMAC_DMA_RX_INT_WDT */
    volatile uint32_t  AXI_Bus_Mode;                              /* ALT_EMAC_DMA_AXI_BUS_MOD */
    volatile uint32_t  AHB_or_AXI_Status;                         /* ALT_EMAC_DMA_AHB_OR_AXI_STAT */
    volatile uint32_t  _pad_0x30_0x47[6];                         /* *UNDEFINED* */
    volatile uint32_t  Current_Host_Transmit_Descriptor;          /* ALT_EMAC_DMA_CUR_HOST_TX_DESC */
    volatile uint32_t  Current_Host_Receive_Descriptor;           /* ALT_EMAC_DMA_CUR_HOST_RX_DESC */
    volatile uint32_t  Current_Host_Transmit_Buffer_Address;      /* ALT_EMAC_DMA_CUR_HOST_TX_BUF_ADDR */
    volatile uint32_t  Current_Host_Receive_Buffer_Address;       /* ALT_EMAC_DMA_CUR_HOST_RX_BUF_ADDR */
    volatile uint32_t  HW_Feature;                                /* ALT_EMAC_DMA_HW_FEATURE */
};

/* The typedef declaration for the raw register contents of register group ALT_EMAC_DMA. */
typedef volatile struct ALT_EMAC_DMA_raw_s  ALT_EMAC_DMA_raw_t;
#endif  /* __ASSEMBLY__ */


#ifndef __ASSEMBLY__
/*
 * WARNING: The C register and register group struct declarations are provided for
 * convenience and illustrative purposes. They should, however, be used with
 * caution as the C language standard provides no guarantees about the alignment or
 * atomicity of device memory accesses. The recommended practice for writing
 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
 * alt_write_word() functions.
 * 
 * The struct declaration for register group ALT_EMAC.
 */
struct ALT_EMAC_s
{
    volatile ALT_EMAC_GMAC_t  gmacgrp;                   /* ALT_EMAC_GMAC */
    volatile uint32_t         _pad_0xb80_0xfff[288];     /* *UNDEFINED* */
    volatile ALT_EMAC_DMA_t   dmagrp;                    /* ALT_EMAC_DMA */
    volatile uint32_t         _pad_0x105c_0x2000[1001];  /* *UNDEFINED* */
};

/* The typedef declaration for register group ALT_EMAC. */
typedef volatile struct ALT_EMAC_s  ALT_EMAC_t;
/* The struct declaration for the raw register contents of register group ALT_EMAC. */
struct ALT_EMAC_raw_s
{
    volatile ALT_EMAC_GMAC_raw_t  gmacgrp;                   /* ALT_EMAC_GMAC */
    volatile uint32_t             _pad_0xb80_0xfff[288];     /* *UNDEFINED* */
    volatile ALT_EMAC_DMA_raw_t   dmagrp;                    /* ALT_EMAC_DMA */
    volatile uint32_t             _pad_0x105c_0x2000[1001];  /* *UNDEFINED* */
};

/* The typedef declaration for the raw register contents of register group ALT_EMAC. */
typedef volatile struct ALT_EMAC_raw_s  ALT_EMAC_raw_t;
#endif  /* __ASSEMBLY__ */


#ifdef __cplusplus
}
#endif  /* __cplusplus */
#endif  /* __ALTERA_ALT_EMAC_H__ */